Model { Name "PID_SYSGEN" Version 5.0 SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ExecutionOrder off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Mon Feb 07 14:38:26 2005" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "WinXp" ModifiedDateFormat "%" LastModifiedDate "Mon Apr 04 15:23:09 2005" ModelVersionFormat "1.%" ConfigurationManager "None" SimParamPage "Solver" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeMexFile "ext_comm" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on RTWExpressionDepthLimit 5 SimulationMode "normal" Solver "ode45" SolverMode "Auto" StartTime "0.0" StopTime "30.0" MaxOrder 5 MaxStep "auto" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "auto" RelTol "1e-3" AbsTol "auto" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" LoadExternalInput off ExternalInput "[t, u]" LoadInitialState off InitialState "xInitial" SaveTime on TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput on OutputSaveName "yout" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" Decimation "1" LimitDataPoints on MaxDataPoints "1000" SignalLoggingName "sigsOut" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" CheckForMatrixSingularity "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SfunCompatibilityCheckMsg "none" RTWInlineParameters off BlockReductionOpt on BooleanDataType on ConditionallyExecuteInputs on ParameterPooling on OptimizeBlockIOStorage on ZeroCross on AssertionControl "UseLocalSettings" ProdHWDeviceType "Microprocessor" ProdHWWordLengths "8,16,32,32" RTWSystemTargetFile "grt.tlc" RTWTemplateMakefile "grt_default_tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off RTWRetainRTWFile off TLCProfiler off TLCDebug off TLCCoverage off TLCAssertion off BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Derivative } Block { BlockType DiscretePulseGenerator PulseType "Sample based" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Gain Gain "1" Multiplication "Element-wise(K.*u)" ShowAdditionalParam off ParameterDataTypeMode "Same as input" ParameterDataType "sfix(16)" ParameterScalingMode "Best Precision: Matrix-wise" ParameterScaling "2^0" OutDataTypeMode "Same as input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } Block { BlockType Integrator ExternalReset "none" InitialConditionSource "internal" InitialCondition "0" LimitOutput off UpperSaturationLimit "inf" LowerSaturationLimit "-inf" ShowSaturationPort off ShowStatePort off AbsoluteTolerance "auto" ZeroCross on } Block { BlockType Mux Inputs "4" DisplayOption "none" } Block { BlockType Scope Floating off ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "0" } Block { BlockType "S-Function" FunctionName "system" PortCounts "[]" SFunctionModules "''" } Block { BlockType SignalGenerator WaveForm "sine" Amplitude "1" Frequency "1" Units "Hertz" VectorParams1D on } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Sum IconShape "rectangular" Inputs "++" ShowAdditionalParam off InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } Block { BlockType Terminator } Block { BlockType ZeroOrderHold SampleTime "1" } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "PID_SYSGEN" Location [2, 84, 1014, 724] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "80" ReportName "simulink-default.rpt" Block { BlockType Reference Name " System Generator" Tag "genX" Ports [] Position [527, 63, 578, 113] ShowName off AttributesFormatString "System\\nGenerator" UserDataPersistent on UserData "DataTag0" SourceBlock "xbsIndex_r3/ System Generator" SourceType "Xilinx System Generator" xilinxfamily "Spartan2" part "xc2s50" speed "-6" package "pq208" synthesis_tool "XST" directory "C:/Matlab6p5/work/xpid_sg_full_001" testbench off simulink_period "1/100" sysclk_period "100" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" } Block { BlockType Reference Name "AddSub1" Ports [2, 1] Position [430, 331, 475, 389] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Subtraction" precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "4" quantization "Truncate" overflow "Wrap" latency "0" explicit_period on period "0.01" use_carryin off use_carryout off en off dbl_ovrd off show_param off use_core on pipeline off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "AddSub2" Ports [2, 1] Position [525, 368, 555, 417] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "4" quantization "Truncate" overflow "Wrap" latency "0" explicit_period on period "0.01" use_carryin off use_carryout off en off dbl_ovrd off show_param off use_core on pipeline off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "AddSub3" Ports [2, 1] Position [390, 577, 430, 628] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Subtraction" precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "4" quantization "Truncate" overflow "Wrap" latency "0" explicit_period on period "0.01" use_carryin off use_carryout off en off dbl_ovrd off show_param off use_core on pipeline off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "AddSub4" Ports [2, 1] Position [685, 566, 725, 619] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "10" quantization "Truncate" overflow "Wrap" latency "0" explicit_period on period "0.01" use_carryin off use_carryout off en off dbl_ovrd off show_param off use_core on pipeline off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "AddSub5" Ports [2, 1] Position [595, 479, 640, 526] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "10" quantization "Truncate" overflow "Wrap" latency "0" explicit_period on period "0.01" use_carryin off use_carryout off en off dbl_ovrd off show_param off use_core on pipeline off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "AddSub6" Ports [2, 1] Position [755, 580, 795, 640] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "10" quantization "Truncate" overflow "Wrap" latency "0" explicit_period on period "0.01" use_carryin off use_carryout off en off dbl_ovrd off show_param off use_core on pipeline off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "CMult3" Ports [1, 1] Position [320, 403, 365, 447] NamePlacement "alternate" SourceBlock "xbsIndex_r3/CMult" SourceType "Xilinx Constant Multiplier" const "2" show_cparam on const_n_bits "16" const_bin_pt "4" show_output_param off precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "6" quantization "Round (unbiased: +/- Inf)" overflow "Wrap" latency "0" explicit_period on period "0.01" en off dbl_ovrd off show_param off mult_type "Parallel" oversample "2" mem_type "Distributed RAM" pipeline off use_rpm on placement_style "Rectangular Shape" gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay" Ports [1, 1] Position [245, 324, 280, 366] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period on period "0.01" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay1" Ports [1, 1] Position [765, 670, 800, 710] Orientation "left" NamePlacement "alternate" SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period on period "0.01" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay2" Ports [1, 1] Position [330, 322, 365, 368] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period on period "0.01" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Derivative Name "Derivative" Position [320, 215, 355, 255] } Block { BlockType Gain Name "Gain" Position [210, 213, 260, 257] Gain "1.95" } Block { BlockType Gain Name "Gain1" Position [210, 147, 260, 193] Gain "0.01" } Block { BlockType Gain Name "Gain2" Position [210, 89, 260, 131] Gain "4.37" } Block { BlockType Reference Name "Gateway In1" Ports [1, 1] Position [145, 454, 180, 476] SourceBlock "xbsIndex_r3/Gateway In" SourceType "Xilinx Gateway In" arith_type "Signed (2's comp)" n_bits "16" bin_pt "4" quantization "Truncate" overflow "Wrap" period "0.01" timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out" Ports [1, 1] Position [840, 518, 875, 542] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Integrator Name "Integrator1" Ports [1, 1] Position [975, 512, 1000, 548] } Block { BlockType Integrator Name "Integrator2" Ports [1, 1] Position [320, 150, 355, 190] } Block { BlockType Integrator Name "Integrator3" Ports [1, 1] Position [635, 140, 670, 180] } Block { BlockType Integrator Name "Integrator4" Ports [1, 1] Position [715, 140, 750, 180] } Block { BlockType Integrator Name "Integrator5" Ports [1, 1] Position [1025, 513, 1050, 547] } Block { BlockType Reference Name "Kd" Ports [1, 1] Position [585, 368, 640, 422] SourceBlock "xbsIndex_r3/CMult" SourceType "Xilinx Constant Multiplier" const "1.95/0.01" show_cparam on const_n_bits "16" const_bin_pt "4" show_output_param off precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "6" quantization "Round (unbiased: +/- Inf)" overflow "Wrap" latency "0" explicit_period on period "0.01" en off dbl_ovrd off show_param off mult_type "Parallel" oversample "2" mem_type "Distributed RAM" pipeline off use_rpm on placement_style "Rectangular Shape" gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Ki" Ports [1, 1] Position [465, 439, 550, 491] SourceBlock "xbsIndex_r3/CMult" SourceType "Xilinx Constant Multiplier" const "0.01*0.01" show_cparam on const_n_bits "16" const_bin_pt "16" show_output_param off precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "6" quantization "Round (unbiased: +/- Inf)" overflow "Wrap" latency "0" explicit_period on period "0.01" en off dbl_ovrd off show_param off mult_type "Parallel" oversample "2" mem_type "Distributed RAM" pipeline off use_rpm on placement_style "Rectangular Shape" gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Kp" Ports [1, 1] Position [465, 575, 525, 635] SourceBlock "xbsIndex_r3/CMult" SourceType "Xilinx Constant Multiplier" const "4.37" show_cparam on const_n_bits "16" const_bin_pt "10" show_output_param off precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "6" quantization "Round (unbiased: +/- Inf)" overflow "Wrap" latency "0" explicit_period on period "0.01" en off dbl_ovrd off show_param off mult_type "Parallel" oversample "2" mem_type "Distributed RAM" pipeline off use_rpm on placement_style "Rectangular Shape" gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Mux Name "Mux" Ports [2, 1] Position [1155, 151, 1160, 189] ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType Mux Name "Mux1" Ports [2, 1] Position [1150, 326, 1155, 364] ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType Mux Name "Mux2" Ports [2, 1] Position [1150, 241, 1155, 279] ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType Mux Name "Mux3" Ports [2, 1] Position [1150, 483, 1155, 547] ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType Scope Name "Scope" Ports [1] Position [1185, 94, 1215, 126] Location [188, 365, 512, 604] Open on NumInputPorts "1" List { ListType AxesTitles axes1 "%" } List { ListType SelectedSignals axes1 "" } SaveName "ScopeData3" DataFormat "StructureWithTime" } Block { BlockType Scope Name "Scope1" Ports [1] Position [1185, 154, 1215, 186] Location [5, 60, 1021, 733] Open off NumInputPorts "1" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" } List { ListType SelectedSignals axes1 "" } SaveName "ScopeData1" DataFormat "StructureWithTime" } Block { BlockType Scope Name "Scope2" Ports [1] Position [1185, 244, 1215, 276] Location [1, 54, 1025, 735] Open off NumInputPorts "1" List { ListType AxesTitles axes1 "%" } List { ListType SelectedSignals axes1 "" } YMin "-3" YMax "3" SaveName "ScopeData2" DataFormat "StructureWithTime" LimitDataPoints off } Block { BlockType Scope Name "Scope3" Ports [1] Position [1185, 329, 1215, 361] Location [188, 365, 512, 604] Open on NumInputPorts "1" List { ListType AxesTitles axes1 "%" } List { ListType SelectedSignals axes1 "" } SaveName "ScopeData5" DataFormat "StructureWithTime" } Block { BlockType Scope Name "Scope5" Ports [1] Position [1185, 499, 1215, 531] Location [1, 56, 1025, 737] Open off NumInputPorts "1" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" } List { ListType SelectedSignals axes1 "" } DataFormat "StructureWithTime" } Block { BlockType Scope Name "Scope8" Ports [1] Position [1185, 404, 1215, 436] Location [188, 365, 512, 604] Open off NumInputPorts "1" List { ListType AxesTitles axes1 "%" } List { ListType SelectedSignals axes1 "" } TimeRange "100" SaveName "ScopeData4" DataFormat "StructureWithTime" } Block { BlockType SignalGenerator Name "Signal\nGenerator" Position [15, 344, 50, 386] WaveForm "square" Frequency "0.06" } Block { BlockType Sum Name "Sum" Ports [2, 1] Position [95, 455, 115, 475] ShowName off IconShape "round" Inputs "|+-" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType Sum Name "Sum1" Ports [2, 1] Position [75, 160, 95, 180] ShowName off IconShape "round" Inputs "|+-" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType Sum Name "Sum2" Ports [3, 1] Position [480, 124, 495, 196] ShowName off Inputs "|+++" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType ZeroOrderHold Name "Zero-Order\nHold" Position [915, 511, 950, 549] SampleTime "0.01" } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Delay2" DstPort 1 } Branch { Points [0, 80] Branch { DstBlock "CMult3" DstPort 1 } Branch { Points [0, 105; 75, 0; 0, 85] DstBlock "AddSub3" DstPort 2 } } } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "CMult3" SrcPort 1 Points [45, 0] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Sum" SrcPort 1 DstBlock "Gateway In1" DstPort 1 } Line { SrcBlock "Signal\nGenerator" SrcPort 1 Points [5, 0] Branch { Points [0, 0; 0, -65] Branch { DstBlock "Sum1" DstPort 1 } Branch { Points [790, 0] Branch { Points [0, 200] DstBlock "Mux3" DstPort 1 } Branch { Points [0, -120] DstBlock "Mux" DstPort 2 } } } Branch { Labels [1, 0] Points [0, 100] DstBlock "Sum" DstPort 1 } } Line { SrcBlock "Sum1" SrcPort 1 Points [30, 0] Branch { Points [0, -60] DstBlock "Gain2" DstPort 1 } Branch { DstBlock "Gain1" DstPort 1 } Branch { Points [0, 65] DstBlock "Gain" DstPort 1 } } Line { SrcBlock "Gain1" SrcPort 1 DstBlock "Integrator2" DstPort 1 } Line { SrcBlock "Gain" SrcPort 1 DstBlock "Derivative" DstPort 1 } Line { SrcBlock "Derivative" SrcPort 1 Points [55, 0; 0, -45] DstBlock "Sum2" DstPort 3 } Line { SrcBlock "Sum2" SrcPort 1 Points [105, 0] Branch { DstBlock "Integrator3" DstPort 1 } Branch { Points [0, -50; 505, 0] Branch { DstBlock "Scope" DstPort 1 } Branch { Points [0, 225] DstBlock "Mux1" DstPort 1 } } } Line { SrcBlock "Integrator3" SrcPort 1 DstBlock "Integrator4" DstPort 1 } Line { SrcBlock "Integrator4" SrcPort 1 Points [65, 0] Branch { Points [0, 115; -735, 0] DstBlock "Sum1" DstPort 2 } Branch { Points [275, 0] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 90] DstBlock "Mux2" DstPort 1 } } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Scope1" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Scope2" DstPort 1 } Line { SrcBlock "Gateway In1" SrcPort 1 Points [30, 0] Branch { Points [215, 0] Branch { DstBlock "Ki" DstPort 1 } Branch { Points [0, -60] DstBlock "AddSub2" DstPort 2 } } Branch { Points [0, -120] DstBlock "Delay" DstPort 1 } Branch { Points [0, 125] DstBlock "AddSub3" DstPort 1 } } Line { SrcBlock "Gateway Out" SrcPort 1 Points [0, 0; 20, 0] Branch { Points [-15, 0; 0, -110; 225, 0] Branch { DstBlock "Scope8" DstPort 1 } Branch { Points [0, -65] DstBlock "Mux1" DstPort 2 } } Branch { DstBlock "Zero-Order\nHold" DstPort 1 } } Line { SrcBlock "Ki" SrcPort 1 Points [5, 0; 0, 50] DstBlock "AddSub5" DstPort 2 } Line { SrcBlock "AddSub3" SrcPort 1 DstBlock "Kp" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 Points [10, 0; 0, 20] DstBlock "AddSub2" DstPort 1 } Line { SrcBlock "Kd" SrcPort 1 Points [10, 0; 0, 75; -75, 0] DstBlock "AddSub5" DstPort 1 } Line { SrcBlock "AddSub2" SrcPort 1 DstBlock "Kd" DstPort 1 } Line { SrcBlock "Kp" SrcPort 1 DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "AddSub5" SrcPort 1 Points [5, 0; 0, 75] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "AddSub4" SrcPort 1 DstBlock "AddSub6" DstPort 1 } Line { SrcBlock "Zero-Order\nHold" SrcPort 1 DstBlock "Integrator1" DstPort 1 } Line { SrcBlock "AddSub6" SrcPort 1 Points [25, 0] Branch { Points [0, 80] DstBlock "Delay1" DstPort 1 } Branch { DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [-20, 0] DstBlock "AddSub6" DstPort 2 } Line { SrcBlock "Gain2" SrcPort 1 Points [150, 0; 0, 40] DstBlock "Sum2" DstPort 1 } Line { SrcBlock "Integrator1" SrcPort 1 DstBlock "Integrator5" DstPort 1 } Line { SrcBlock "Integrator5" SrcPort 1 Points [10, 0; 15, 0] Branch { Points [0, 185; -975, 0] DstBlock "Sum" DstPort 2 } Branch { Points [15, 0] Branch { DstBlock "Mux3" DstPort 2 } Branch { Points [0, -260] DstBlock "Mux2" DstPort 2 } } } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Scope5" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Scope3" DstPort 1 } Line { SrcBlock "Integrator2" SrcPort 1 DstBlock "Sum2" DstPort 2 } Annotation { Name "\n\n\n\n\n" Position [984, 634] } Annotation { Name "en" Position [221, 331] } Annotation { Name "en-1" Position [290, 333] } Annotation { Name "en-2" Position [369, 331] } Annotation { Name "Un" Position [811, 591] } Annotation { Name "Un-1" Position [730, 669] } } } MatData { NumRecords 1 DataRecord { Tag DataTag0 Data " %)30 . .!( 8 ( @ % " "\" $ ! 0 % 0 !@ $ , &EL:6YX9F%M:6QY '!A0!S '0 90!M #@ & & \" 0 !0 @ " " ! & $ ! # !! &, 8P!O '( 9 !I &X 9P @ '0 ;P @ $( ; !O " "&, :P @ $T 80!S &L

&9A;6EL" ">0 !P87)T 6YT:" "&5S:7-?=&]O; 9&ER96-T;W)Y '1E7-C;&M?<&5R:6]D " " 8V]R95]G96YE !C #(

!P &D 9 !? ', 9P!? &8 =0!" "L &P 7P P # ,0 #@ #@ & \" 0 !0 @ ! P $" " ! 8 !O &8 9@ X X !@ @ $ 4 ( 0 " " , ! 0 & ,0 P # . 8 8 ( ! % " "\" $ 8 0 $ , $$ 8P!C &\\ <@!D &D ;@!G \" = !O \" 0" "@!L &\\ 8P!K \" 30!A ', :P!S X X !@ @ $ 4 ( 0 " " , ! 0 & ;P!F &8 . , 8 ( ! % " "\" $ ! 0 $ ( , X P !@ @ $ 4 (" " ! 0 " } }