Model { Name "phase_detector" Version 5.0 SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ExecutionOrder off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Fri Apr 30 11:32:24 2010" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "Administrator" ModifiedDateFormat "%" LastModifiedDate "Sun May 02 10:07:46 2010" ModelVersionFormat "1.%" ConfigurationManager "None" SimParamPage "Solver" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeMexFile "ext_comm" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on RTWExpressionDepthLimit 5 SimulationMode "normal" Solver "ode4" SolverMode "Auto" StartTime "0.0" StopTime "10" MaxOrder 5 MaxStep "auto" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "0.00001" RelTol "1e-6" AbsTol "auto" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" LoadExternalInput off ExternalInput "[t, u]" LoadInitialState off InitialState "xInitial" SaveTime on TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput on OutputSaveName "yout" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" Decimation "1" LimitDataPoints on MaxDataPoints "1000" SignalLoggingName "sigsOut" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" CheckForMatrixSingularity "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SfunCompatibilityCheckMsg "none" RTWInlineParameters off BlockReductionOpt on BooleanDataType on ConditionallyExecuteInputs on ParameterPooling on OptimizeBlockIOStorage on ZeroCross on AssertionControl "UseLocalSettings" ProdHWDeviceType "Microprocessor" ProdHWWordLengths "8,16,32,32" RTWSystemTargetFile "grt.tlc" RTWTemplateMakefile "grt_default_tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off RTWRetainRTWFile off TLCProfiler off TLCDebug off TLCCoverage off TLCAssertion off BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Constant Value "1" VectorParams1D on ShowAdditionalParam off OutDataTypeMode "Inherit from 'Constant value'" OutDataType "sfix(16)" ConRadixGroup "Use specified scaling" OutScaling "2^0" } Block { BlockType Integrator ExternalReset "none" InitialConditionSource "internal" InitialCondition "0" LimitOutput off UpperSaturationLimit "inf" LowerSaturationLimit "-inf" ShowSaturationPort off ShowStatePort off AbsoluteTolerance "auto" ZeroCross on } Block { BlockType MATLABFcn MATLABFcn "sin" OutputDimensions "-1" OutputSignalType "auto" Output1D on } Block { BlockType Mux Inputs "4" DisplayOption "none" } Block { BlockType Outport Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Saturate UpperLimit "0.5" LowerLimit "-0.5" LinearizeAsGain on ZeroCross on } Block { BlockType StateSpace A "1" B "1" C "1" D "1" X0 "0" AbsoluteTolerance "auto" Realization "auto" } Block { BlockType Step Time "1" Before "0" After "1" SampleTime "-1" VectorParams1D on ZeroCross on } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Sum IconShape "rectangular" Inputs "++" ShowAdditionalParam off InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } Block { BlockType ToWorkspace VariableName "simulink_output" MaxDataPoints "1000" Decimation "1" SampleTime "0" } Block { BlockType TransferFcn Numerator "[1]" Denominator "[1 2 1]" AbsoluteTolerance "auto" Realization "auto" } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "phase_detector" Location [256, 150, 1273, 543] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType Reference Name "Analog\nFilter Design" Ports [1, 1] Position [755, 202, 820, 258] SourceBlock "dsparch4/Analog\nFilter Design" SourceType "Analog Filter Design" method "Butterworth" filttype "Lowpass" N "8" Wlo "30" Whi "80" Rp "2" Rs "40" } Block { BlockType Constant Name "Constant" Position [35, 30, 65, 60] } Block { BlockType Integrator Name "Integrator" Ports [1, 1] Position [140, 30, 170, 60] } Block { BlockType Integrator Name "Integrator1" Ports [1, 1] Position [340, 215, 370, 245] } Block { BlockType Integrator Name "Integrator2" Ports [1, 1] Position [1045, 215, 1075, 245] InitialCondition "14.3239" } Block { BlockType Mux Name "Mux" Ports [3, 1] Position [125, 116, 130, 154] ShowName off Inputs "3" DisplayOption "bar" } Block { BlockType Mux Name "Mux1" Ports [3, 1] Position [540, 271, 545, 309] ShowName off Inputs "3" DisplayOption "bar" } Block { BlockType Mux Name "Mux2" Ports [2, 1] Position [630, 211, 635, 249] ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType MATLABFcn Name "Pembangkit Snus 1" Position [175, 120, 235, 150] MATLABFcn "gel_sinus" } Block { BlockType MATLABFcn Name "Pembangkit Snus 2" Position [580, 275, 640, 305] MATLABFcn "gel_sinus" } Block { BlockType MATLABFcn Name "Peng_XOR" Position [675, 215, 735, 245] MATLABFcn "peng_xor" } Block { BlockType Saturate Name "Saturation" Position [395, 215, 425, 245] UpperLimit "pi/2" LowerLimit "-pi/2" } Block { BlockType Sum Name "Sum" Ports [2, 1] Position [125, 270, 145, 290] ShowName off IconShape "round" Inputs "|++" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType Sum Name "Sum1" Ports [2, 1] Position [185, 220, 205, 240] ShowName off IconShape "round" Inputs "|-+" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType Sum Name "Sum2" Ports [2, 1] Position [495, 170, 515, 190] ShowName off IconShape "round" Inputs "|+-" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType Sum Name "Sum3" Ports [2, 1] Position [925, 220, 945, 240] ShowName off IconShape "round" Inputs "|+-" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType TransferFcn Name "Transfer Fcn1" Position [255, 212, 315, 248] Numerator "[2*pi]" Denominator "[1000]" } Block { BlockType TransferFcn Name "Transfer Fcn2" Position [535, 162, 595, 198] Numerator "[180]" Denominator "[pi]" } Block { BlockType TransferFcn Name "Transfer Fcn3" Position [840, 212, 900, 248] Numerator "[180]" Denominator "[pi]" } Block { BlockType TransferFcn Name "Transfer Fcn4" Position [965, 212, 1010, 248] Denominator "[0.4]" } Block { BlockType TransferFcn Name "Transfer Fcn5" Position [1115, 212, 1160, 248] Numerator "[45]" Denominator "[14.3239]" } Block { BlockType SubSystem Name "Variasi Frekuensi" Ports [0, 1] Position [15, 299, 115, 341] FontSize 10 TreatAsAtomicUnit off System { Name "Variasi Frekuensi" Location [433, 403, 931, 703] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Step Name "Step" Position [120, 35, 150, 65] Time "4" After "-20" SampleTime "0" } Block { BlockType Step Name "Step1" Position [120, 90, 150, 120] Time "5" After "-20" SampleTime "0" } Block { BlockType Step Name "Step2" Position [120, 160, 150, 190] Time "7" After "20" SampleTime "0" } Block { BlockType Step Name "Step3" Position [120, 215, 150, 245] Time "8" After "20" SampleTime "0" } Block { BlockType Sum Name "Sum" Ports [2, 1] Position [295, 100, 315, 120] ShowName off IconShape "round" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType Sum Name "Sum1" Ports [2, 1] Position [195, 70, 215, 90] ShowName off IconShape "round" Inputs "+-" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType Sum Name "Sum2" Ports [2, 1] Position [200, 190, 220, 210] ShowName off IconShape "round" Inputs "+-" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType Outport Name "Out1" Position [360, 103, 390, 117] } Line { SrcBlock "Sum" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "Step" SrcPort 1 Points [50, 0] DstBlock "Sum1" DstPort 1 } Line { SrcBlock "Step1" SrcPort 1 DstBlock "Sum1" DstPort 2 } Line { SrcBlock "Sum1" SrcPort 1 Points [85, 0] DstBlock "Sum" DstPort 1 } Line { SrcBlock "Step2" SrcPort 1 DstBlock "Sum2" DstPort 1 } Line { SrcBlock "Step3" SrcPort 1 Points [55, 0] DstBlock "Sum2" DstPort 2 } Line { SrcBlock "Sum2" SrcPort 1 Points [80, 0] DstBlock "Sum" DstPort 2 } } } Block { BlockType ToWorkspace Name "Waktu" Position [235, 30, 295, 60] VariableName "time" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Constant Name "frekuensi" Position [10, 110, 70, 140] Value "1000" } Block { BlockType Constant Name "frekuensi1" Position [40, 215, 70, 245] Value "1000" } Block { BlockType ToWorkspace Name "gelombang 1" Position [670, 120, 730, 150] VariableName "sinus_1" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "gelombang 2" Position [675, 272, 740, 308] VariableName "sinus_2" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "glombang 3" Position [1195, 215, 1255, 245] ShowName off VariableName "hasil_xor" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "perubahan frekuensi" Position [250, 305, 310, 335] VariableName "frek" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Constant Name "phase" Position [40, 165, 70, 195] Value "pi/4" } Block { BlockType ToWorkspace Name "selisih fasa" Position [670, 165, 730, 195] VariableName "phase" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Integrator" DstPort 1 } Line { SrcBlock "Integrator" SrcPort 1 Points [25, 0] Branch { DstBlock "Waktu" DstPort 1 } Branch { Points [0, 50; 240, 0; 0, 100] Branch { Points [-330, 0] DstBlock "Mux" DstPort 3 } Branch { Points [0, 105] DstBlock "Mux1" DstPort 3 } } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Pembangkit Snus 1" DstPort 1 } Line { SrcBlock "frekuensi" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "phase" SrcPort 1 Points [15, 0] Branch { Points [0, -45] DstBlock "Mux" DstPort 2 } Branch { DstBlock "Sum2" DstPort 1 } } Line { SrcBlock "Pembangkit Snus 1" SrcPort 1 Points [370, 0] Branch { DstBlock "gelombang 1" DstPort 1 } Branch { Points [0, 85] DstBlock "Mux2" DstPort 1 } } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Pembangkit Snus 2" DstPort 1 } Line { SrcBlock "Pembangkit Snus 2" SrcPort 1 Points [20, 0] Branch { DstBlock "gelombang 2" DstPort 1 } Branch { Points [-10, 0; 0, -30; -40, 0] DstBlock "Mux2" DstPort 2 } } Line { SrcBlock "frekuensi1" SrcPort 1 Points [25, 0] Branch { DstBlock "Sum1" DstPort 1 } Branch { Points [0, 50] DstBlock "Sum" DstPort 1 } } Line { SrcBlock "Sum" SrcPort 1 Points [45, 0] Branch { DstBlock "Mux1" DstPort 1 } Branch { DstBlock "Sum1" DstPort 2 } Branch { Points [0, 40] DstBlock "perubahan frekuensi" DstPort 1 } } Line { SrcBlock "Transfer Fcn1" SrcPort 1 DstBlock "Integrator1" DstPort 1 } Line { SrcBlock "Integrator1" SrcPort 1 DstBlock "Saturation" DstPort 1 } Line { SrcBlock "Saturation" SrcPort 1 Points [75, 0; 0, 60] Branch { DstBlock "Mux1" DstPort 2 } Branch { DstBlock "Sum2" DstPort 2 } } Line { SrcBlock "Sum1" SrcPort 1 DstBlock "Transfer Fcn1" DstPort 1 } Line { SrcBlock "Sum2" SrcPort 1 DstBlock "Transfer Fcn2" DstPort 1 } Line { SrcBlock "Transfer Fcn2" SrcPort 1 DstBlock "selisih fasa" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Peng_XOR" DstPort 1 } Line { SrcBlock "Peng_XOR" SrcPort 1 DstBlock "Analog\nFilter Design" DstPort 1 } Line { SrcBlock "Analog\nFilter Design" SrcPort 1 DstBlock "Transfer Fcn3" DstPort 1 } Line { SrcBlock "Transfer Fcn3" SrcPort 1 DstBlock "Sum3" DstPort 1 } Line { SrcBlock "Sum3" SrcPort 1 DstBlock "Transfer Fcn4" DstPort 1 } Line { SrcBlock "Transfer Fcn4" SrcPort 1 DstBlock "Integrator2" DstPort 1 } Line { SrcBlock "Integrator2" SrcPort 1 Points [15, 0] Branch { Points [0, 75; -160, 0] DstBlock "Sum3" DstPort 2 } Branch { DstBlock "Transfer Fcn5" DstPort 1 } } Line { SrcBlock "Transfer Fcn5" SrcPort 1 DstBlock "glombang 3" DstPort 1 } Line { SrcBlock "Variasi Frekuensi" SrcPort 1 Points [15, 0] DstBlock "Sum" DstPort 2 } } } Generator 1" SrcPort 1 Points [15, 0; 90, 0] Branch { Points [280, 0] Branch { DstBlock "gelombang 1" DstPort 1 } Branch { Points [0, 85] DstBlock "Mux2" DstPort 1 } } Branch { Points [0, -175] DstBlock "Analog Filter " DstPort 1 } } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Pulse Generator 2" DstPort 1 } Line { SrcBlock "Pulse Generator 2" SrcPort 1 Points [0, 0; 20, 0] Branch { DstBlock "gelombang 2" DstPort 1 } Branch { Points [-10, 0; 0, -30; -40, 0; 0, -20] Branch { DstBlock "Mux2" DstPort 2 } Branch { Points [-220, 0; 0, -195] DstBlock "Analog Filter1" DstPort 1 } } } Line { SrcBlock "Gain" SrcPort 1 DstBlock "Integrator1" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Peng_XOR" DstPort 1 } Line { SrcBlock "Peng_XOR" SrcPort 1 DstBlock "Analog Filter" DstPort 1 } Line { SrcBlock "Analog Filter" SrcPort 1 DstBlock "Logarithmic Amplifier" DstPort 1 } Line { SrcBlock "rad to degree " SrcPort 1 DstBlock "glombang 3" DstPort 1 } Line { SrcBlock "Ref. Freq [Hz]" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "phase" SrcPort 1 Points [20, 0; 0, -40] DstBlock "Mux" DstPort 3 } Line { SrcBlock "Sum" SrcPort 1 Points [0, 0; 60, 0] Branch { DstBlock "Mux1" DstPort 2 } Branch { Points [0, -55] DstBlock "Frequency Variation" DstPort 1 } Branch { DstBlock "Sum1" DstPort 1 } } Line { SrcBlock "frekuensi1 [RPM]" SrcPort 1 Points [105, 0] Branch { Points [75, 0] DstBlock "Sum1" DstPort 2 } Branch { DstBlock "Sum" DstPort 2 } } Line { SrcBlock "Sum1" SrcPort 1 DstBlock "Gain" DstPort 1 } Line { SrcBlock "Integrator1" SrcPort 1 Points [40, 0] Branch { Points [0, -40] DstBlock "Mux1" DstPort 3 } Branch { DstBlock "rad to degree" DstPort 1 } } Line { SrcBlock "Analog Filter " SrcPort 1 Points [75, 0] DstBlock "Sum2" DstPort 1 } Line { SrcBlock "Analog Filter1" SrcPort 1 Points [75, 0] DstBlock "Sum2" DstPort 2 } Line { SrcBlock "Sum2" SrcPort 1 Points [35, 0] Branch { Points [0, 60] DstBlock "gelombang 3" DstPort 1 } Branch { DstBlock "Komparator" DstPort 1 } } Line { SrcBlock "Komparator" SrcPort 1 Points [75, 0; 0, 50] DstBlock "Product" DstPort 1 } Line { SrcBlock "rad to degree" SrcPort 1 DstBlock "glombang 1" DstPort 1 } Line { SrcBlock "Product" SrcPort 1 DstBlock "rad to degree" DstPort 1 } Line { SrcBlock "Frequency Variations" SrcPort 1 DstBlock "Manual Switch" DstPort 1 } Line { SrcBlock "Manual Switch" SrcPort 1 Points [20, 0] DstBlock "Sum" DstPort 1 } Line { SrcBlock "phase1" SrcPort 1 Points [10, 0; 0, -35] DstBlock "Manual Switch" DstPort 2 } Line { SrcBlock "rad to degree" SrcPort 1 DstBlock "phase difference" DstPort 1 } Line { SrcBlock "Logarithmic Amplifier" SrcPort 1 Points [55, 0] Branch { DstBlock "rad to degree " DstPort 1 } Branch { Points [0, -160] DstBlock "Product" DstPort 2 } } } }