Model {
  Name			  "simple1_sg"
  Version		  5.0
  SaveDefaultBlockParams  on
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  ShowStorageClass	  off
  ExecutionOrder	  off
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeVarName	  "covCumulativeData"
  CovCumulativeReport	  off
  DataTypeOverride	  "UseLocalSettings"
  MinMaxOverflowLogging	  "UseLocalSettings"
  MinMaxOverflowArchiveMode "Overwrite"
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  Created		  "Wed May 11 12:03:08 2005"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "WinXp"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Thu Jul 28 16:49:26 2005"
  ModelVersionFormat	  "1.%<AutoIncrement:30>"
  ConfigurationManager	  "None"
  SimParamPage		  "Solver"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  ExtModeMexFile	  "ext_comm"
  ExtModeBatchMode	  off
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  BufferReuse		  on
  RTWExpressionDepthLimit 5
  SimulationMode	  "normal"
  Solver		  "ode45"
  SolverMode		  "Auto"
  StartTime		  "0.0"
  StopTime		  "30"
  MaxOrder		  5
  MaxStep		  "auto"
  MinStep		  "auto"
  MaxNumMinSteps	  "-1"
  InitialStep		  "auto"
  FixedStep		  "auto"
  RelTol		  "1e-3"
  AbsTol		  "auto"
  OutputOption		  "RefineOutputTimes"
  OutputTimes		  "[]"
  Refine		  "1"
  LoadExternalInput	  off
  ExternalInput		  "[t, u]"
  LoadInitialState	  off
  InitialState		  "xInitial"
  SaveTime		  on
  TimeSaveName		  "tout"
  SaveState		  off
  StateSaveName		  "xout"
  SaveOutput		  on
  OutputSaveName	  "yout"
  SaveFinalState	  off
  FinalStateName	  "xFinal"
  SaveFormat		  "Array"
  Decimation		  "1"
  LimitDataPoints	  on
  MaxDataPoints		  "1000"
  SignalLoggingName	  "sigsOut"
  ConsistencyChecking	  "none"
  ArrayBoundsChecking	  "none"
  AlgebraicLoopMsg	  "warning"
  BlockPriorityViolationMsg "warning"
  MinStepSizeMsg	  "warning"
  InheritedTsInSrcMsg	  "warning"
  DiscreteInheritContinuousMsg "warning"
  MultiTaskRateTransMsg	  "error"
  SingleTaskRateTransMsg  "none"
  CheckForMatrixSingularity "none"
  IntegerOverflowMsg	  "warning"
  Int32ToFloatConvMsg	  "warning"
  ParameterDowncastMsg	  "error"
  ParameterOverflowMsg	  "error"
  ParameterPrecisionLossMsg "warning"
  UnderSpecifiedDataTypeMsg "none"
  UnnecessaryDatatypeConvMsg "none"
  VectorMatrixConversionMsg "none"
  InvalidFcnCallConnMsg	  "error"
  SignalLabelMismatchMsg  "none"
  UnconnectedInputMsg	  "warning"
  UnconnectedOutputMsg	  "warning"
  UnconnectedLineMsg	  "warning"
  SfunCompatibilityCheckMsg "none"
  RTWInlineParameters	  off
  BlockReductionOpt	  on
  BooleanDataType	  on
  ConditionallyExecuteInputs on
  ParameterPooling	  on
  OptimizeBlockIOStorage  on
  ZeroCross		  on
  AssertionControl	  "UseLocalSettings"
  ProdHWDeviceType	  "Microprocessor"
  ProdHWWordLengths	  "8,16,32,32"
  RTWSystemTargetFile	  "grt.tlc"
  RTWTemplateMakefile	  "grt_default_tmf"
  RTWMakeCommand	  "make_rtw"
  RTWGenerateCodeOnly	  off
  RTWRetainRTWFile	  off
  TLCProfiler		  off
  TLCDebug		  off
  TLCCoverage		  off
  TLCAssertion		  off
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      DiscretePulseGenerator
      PulseType		      "Sample based"
      Amplitude		      "1"
      Period		      "2"
      PulseWidth	      "1"
      PhaseDelay	      "0"
      SampleTime	      "1"
      VectorParams1D	      on
    }
    Block {
      BlockType		      Integrator
      ExternalReset	      "none"
      InitialConditionSource  "internal"
      InitialCondition	      "0"
      LimitOutput	      off
      UpperSaturationLimit    "inf"
      LowerSaturationLimit    "-inf"
      ShowSaturationPort      off
      ShowStatePort	      off
      AbsoluteTolerance	      "auto"
      ZeroCross		      on
    }
    Block {
      BlockType		      Scope
      Floating		      off
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
      Grid		      "on"
      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
      SaveToWorkspace	      off
      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "0"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      PortCounts	      "[]"
      SFunctionModules	      "''"
    }
    Block {
      BlockType		      Step
      Time		      "1"
      Before		      "0"
      After		      "1"
      SampleTime	      "-1"
      VectorParams1D	      on
      ZeroCross		      on
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      RTWSystemCode	      "Auto"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      ShowAdditionalParam     off
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
    }
    Block {
      BlockType		      Terminator
    }
    Block {
      BlockType		      ZeroOrderHold
      SampleTime	      "1"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "simple1_sg"
    Location		    [2, 84, 1014, 697]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    ZoomFactor		    "80"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      " System Generator"
      Tag		      "genX"
      Ports		      []
      Position		      [852, 158, 903, 208]
      ShowName		      off
      AttributesFormatString  "System\\nGenerator"
      UserDataPersistent      on
      UserData		      "DataTag0"
      SourceBlock	      "xbsIndex_r3/ System Generator"
      SourceType	      "Xilinx System Generator"
      xilinxfamily	      "Virtex2"
      part		      "xc2v1000"
      speed		      "-4"
      package		      "bg575"
      synthesis_tool	      "XST"
      directory		      "./netlist"
      testbench		      off
      simulink_period	      "1/100"
      sysclk_period	      "100"
      incr_netlist	      off
      trim_vbits	      "Everywhere in SubSystem"
      dbl_ovrd		      "According to Block Masks"
      core_generation	      "According to Block Masks"
      run_coregen	      off
      deprecated_control      off
      eval_field	      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "AddSub1"
      Ports		      [2, 1]
      Position		      [545, 271, 590, 329]
      SourceBlock	      "xbsIndex_r3/AddSub"
      SourceType	      "Xilinx Adder/Subtractor"
      mode		      "Subtraction"
      precision		      "Full"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "16"
      bin_pt		      "4"
      quantization	      "Truncate"
      overflow		      "Wrap"
      latency		      "0"
      explicit_period	      on
      period		      "0.01"
      use_carryin	      off
      use_carryout	      off
      en		      off
      dbl_ovrd		      off
      show_param	      off
      use_core		      on
      pipeline		      off
      use_rpm		      on
      gen_core		      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Reference
      Name		      "AddSub2"
      Ports		      [2, 1]
      Position		      [735, 213, 765, 262]
      SourceBlock	      "xbsIndex_r3/AddSub"
      SourceType	      "Xilinx Adder/Subtractor"
      mode		      "Addition"
      precision		      "Full"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "16"
      bin_pt		      "4"
      quantization	      "Truncate"
      overflow		      "Wrap"
      latency		      "0"
      explicit_period	      on
      period		      "0.01"
      use_carryin	      off
      use_carryout	      off
      en		      off
      dbl_ovrd		      off
      show_param	      off
      use_core		      on
      pipeline		      off
      use_rpm		      on
      gen_core		      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Reference
      Name		      "AddSub3"
      Ports		      [2, 1]
      Position		      [550, 364, 595, 411]
      SourceBlock	      "xbsIndex_r3/AddSub"
      SourceType	      "Xilinx Adder/Subtractor"
      mode		      "Addition"
      precision		      "User Defined"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "16"
      bin_pt		      "8"
      quantization	      "Truncate"
      overflow		      "Wrap"
      latency		      "0"
      explicit_period	      on
      period		      "0.01"
      use_carryin	      off
      use_carryout	      off
      en		      off
      dbl_ovrd		      off
      show_param	      off
      use_core		      on
      pipeline		      off
      use_rpm		      on
      gen_core		      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Reference
      Name		      "AddSub4"
      Ports		      [2, 1]
      Position		      [810, 290, 850, 350]
      SourceBlock	      "xbsIndex_r3/AddSub"
      SourceType	      "Xilinx Adder/Subtractor"
      mode		      "Addition"
      precision		      "User Defined"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "24"
      bin_pt		      "16"
      quantization	      "Truncate"
      overflow		      "Wrap"
      latency		      "0"
      explicit_period	      on
      period		      "0.01"
      use_carryin	      off
      use_carryout	      off
      en		      off
      dbl_ovrd		      off
      show_param	      off
      use_core		      on
      pipeline		      off
      use_rpm		      off
      gen_core		      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Reference
      Name		      "Delay"
      Ports		      [1, 1]
      Position		      [455, 294, 490, 336]
      SourceBlock	      "xbsIndex_r3/Delay"
      SourceType	      "Xilinx Delay Block"
      latency		      "1"
      reg_retiming	      off
      explicit_period	      on
      period		      "0.01"
      en		      off
      accept_only_valid	      off
      init_zero		      on
      dbl_ovrd		      off
      show_param	      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Reference
      Name		      "Delay1"
      Ports		      [1, 1]
      Position		      [555, 445, 590, 485]
      Orientation	      "left"
      SourceBlock	      "xbsIndex_r3/Delay"
      SourceType	      "Xilinx Delay Block"
      latency		      "1"
      reg_retiming	      off
      explicit_period	      on
      period		      "0.01"
      en		      off
      accept_only_valid	      off
      init_zero		      on
      dbl_ovrd		      off
      show_param	      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Reference
      Name		      "In"
      Ports		      [1, 1]
      Position		      [350, 304, 385, 326]
      SourceBlock	      "xbsIndex_r3/Gateway In"
      SourceType	      "Xilinx Gateway In"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "16"
      bin_pt		      "8"
      quantization	      "Truncate"
      overflow		      "Wrap"
      period		      "0.01"
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      needs_fixed_name	      off
      dbl_ovrd		      off
      show_param	      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Step
      Name		      "Input Step"
      Position		      [775, 715, 805, 745]
      Time		      "2"
      SampleTime	      "1"
    }
    Block {
      BlockType		      Integrator
      Name		      "Integrator1"
      Ports		      [1, 1]
      Position		      [1025, 300, 1055, 340]
    }
    Block {
      BlockType		      Integrator
      Name		      "Integrator2"
      Ports		      [1, 1]
      Position		      [1090, 300, 1120, 340]
    }
    Block {
      BlockType		      Reference
      Name		      "Kd"
      Ports		      [1, 1]
      Position		      [635, 273, 690, 327]
      SourceBlock	      "xbsIndex_r3/CMult"
      SourceType	      "Xilinx Constant Multiplier"
      const		      "1.95/0.01"
      show_cparam	      on
      const_n_bits	      "16"
      const_bin_pt	      "4"
      show_output_param	      off
      precision		      "Full"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "8"
      bin_pt		      "6"
      quantization	      "Round  (unbiased: +/- Inf)"
      overflow		      "Wrap"
      latency		      "0"
      explicit_period	      on
      period		      "0.01"
      en		      off
      dbl_ovrd		      off
      show_param	      off
      mult_type		      "Parallel"
      oversample	      "2"
      mem_type		      "Distributed RAM"
      pipeline		      off
      use_rpm		      on
      placement_style	      "Rectangular Shape"
      gen_core		      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Reference
      Name		      "Ki"
      Ports		      [1, 1]
      Position		      [670, 364, 755, 416]
      SourceBlock	      "xbsIndex_r3/CMult"
      SourceType	      "Xilinx Constant Multiplier"
      const		      "0.01*0.01"
      show_cparam	      on
      const_n_bits	      "16"
      const_bin_pt	      "16"
      show_output_param	      off
      precision		      "Full"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "8"
      bin_pt		      "6"
      quantization	      "Round  (unbiased: +/- Inf)"
      overflow		      "Wrap"
      latency		      "0"
      explicit_period	      on
      period		      "0.01"
      en		      off
      dbl_ovrd		      off
      show_param	      off
      mult_type		      "Parallel"
      oversample	      "2"
      mem_type		      "Distributed RAM"
      pipeline		      off
      use_rpm		      on
      placement_style	      "Rectangular Shape"
      gen_core		      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Reference
      Name		      "Kp"
      Ports		      [1, 1]
      Position		      [590, 155, 650, 215]
      SourceBlock	      "xbsIndex_r3/CMult"
      SourceType	      "Xilinx Constant Multiplier"
      const		      "4.37"
      show_cparam	      on
      const_n_bits	      "16"
      const_bin_pt	      "10"
      show_output_param	      off
      precision		      "Full"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "8"
      bin_pt		      "6"
      quantization	      "Round  (unbiased: +/- Inf)"
      overflow		      "Wrap"
      latency		      "0"
      explicit_period	      on
      period		      "0.01"
      en		      off
      dbl_ovrd		      off
      show_param	      off
      mult_type		      "Parallel"
      oversample	      "2"
      mem_type		      "Distributed RAM"
      pipeline		      off
      use_rpm		      on
      placement_style	      "Rectangular Shape"
      gen_core		      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Reference
      Name		      "Out"
      Ports		      [1, 1]
      Position		      [890, 308, 925, 332]
      SourceBlock	      "xbsIndex_r3/Gateway Out"
      SourceType	      "Xilinx Gateway Out"
      hdl_port		      on
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      needs_fixed_name	      off
      show_param	      off
      xl_area		      "[0, 0, 0, 0, 0, 0, 0]"
      xl_use_area	      off
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      Ports		      [1]
      Position		      [1185, 309, 1215, 341]
      Location		      [191, 74, 979, 618]
      Open		      off
      NumInputPorts	      "1"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
      }
      List {
	ListType		SelectedSignals
	axes1			""
      }
      TimeRange		      "30"
      SaveName		      "ScopeData1"
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope1"
      Ports		      [1]
      Position		      [950, 204, 980, 236]
      Location		      [191, 74, 979, 618]
      Open		      off
      NumInputPorts	      "1"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
      }
      List {
	ListType		SelectedSignals
	axes1			""
      }
      TimeRange		      "30"
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope2"
      Ports		      [1]
      Position		      [365, 159, 395, 191]
      Location		      [191, 74, 979, 618]
      Open		      on
      NumInputPorts	      "1"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
      }
      List {
	ListType		SelectedSignals
	axes1			""
      }
      TimeRange		      "30"
      SaveName		      "ScopeData2"
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope3"
      Ports		      [1]
      Position		      [265, 59, 295, 91]
      Location		      [191, 74, 979, 618]
      Open		      on
      NumInputPorts	      "1"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
      }
      List {
	ListType		SelectedSignals
	axes1			""
      }
      TimeRange		      "30"
      SaveName		      "ScopeData3"
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      Step
      Name		      "Step"
      Position		      [125, 250, 155, 280]
      Time		      "2"
      After		      "2"
      SampleTime	      "1"
    }
    Block {
      BlockType		      Step
      Name		      "Step1"
      Position		      [125, 200, 155, 230]
      Time		      "2"
      SampleTime	      "1"
    }
    Block {
      BlockType		      Step
      Name		      "Step2"
      Position		      [125, 300, 155, 330]
      Time		      "3"
      After		      "3"
      SampleTime	      "1"
    }
    Block {
      BlockType		      Step
      Name		      "Step3"
      Position		      [125, 350, 155, 380]
      Time		      "4"
      After		      "-2"
      SampleTime	      "1"
    }
    Block {
      BlockType		      Step
      Name		      "Step4"
      Position		      [125, 395, 155, 425]
      Time		      "5"
      After		      "2"
      SampleTime	      "1"
    }
    Block {
      BlockType		      Sum
      Name		      "Sum"
      Ports		      [2, 1]
      Position		      [295, 310, 315, 330]
      ShowName		      off
      IconShape		      "round"
      Inputs		      "|+-"
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
    }
    Block {
      BlockType		      Sum
      Name		      "Sum1"
      Ports		      [5, 1]
      Position		      [235, 240, 250, 405]
      ShowName		      off
      Inputs		      "|++-++"
      SaturateOnIntegerOverflow	off
    }
    Block {
      BlockType		      ZeroOrderHold
      Name		      "Zero-Order\nHold"
      Position		      [955, 301, 990, 339]
      SampleTime	      "0.01"
    }
    Line {
      SrcBlock		      "In"
      SrcPort		      1
      Points		      [0, 0; 45, 0]
      Branch {
	DstBlock		"Delay"
	DstPort			1
      }
      Branch {
	Points			[0, -130; 85, 0]
	Branch {
	  DstBlock		  "Kp"
	  DstPort		  1
	}
	Branch {
	  Points		  [0, 100]
	  DstBlock		  "AddSub1"
	  DstPort		  1
	}
      }
      Branch {
	Points			[0, 60]
	DstBlock		"AddSub3"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Delay"
      SrcPort		      1
      DstBlock		      "AddSub1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "AddSub1"
      SrcPort		      1
      DstBlock		      "Kd"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Kp"
      SrcPort		      1
      Points		      [30, 0; 0, 40]
      DstBlock		      "AddSub2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Kd"
      SrcPort		      1
      Points		      [10, 0; 0, -50]
      DstBlock		      "AddSub2"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Delay1"
      SrcPort		      1
      Points		      [-20, 0; 0, -65]
      DstBlock		      "AddSub3"
      DstPort		      2
    }
    Line {
      SrcBlock		      "AddSub3"
      SrcPort		      1
      Points		      [0, 0; 5, 0]
      Branch {
	DstBlock		"Ki"
	DstPort			1
      }
      Branch {
	DstBlock		"Delay1"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "AddSub2"
      SrcPort		      1
      Points		      [10, 0; 0, 65]
      DstBlock		      "AddSub4"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Ki"
      SrcPort		      1
      Points		      [20, 0; 0, -55]
      DstBlock		      "AddSub4"
      DstPort		      2
    }
    Line {
      SrcBlock		      "AddSub4"
      SrcPort		      1
      DstBlock		      "Out"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Step"
      SrcPort		      1
      Points		      [40, 0; 0, 25]
      DstBlock		      "Sum1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Step1"
      SrcPort		      1
      Points		      [60, 0]
      DstBlock		      "Sum1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Step2"
      SrcPort		      1
      Points		      [0, 10]
      DstBlock		      "Sum1"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Step3"
      SrcPort		      1
      DstBlock		      "Sum1"
      DstPort		      4
    }
    Line {
      SrcBlock		      "Step4"
      SrcPort		      1
      Points		      [60, 0]
      DstBlock		      "Sum1"
      DstPort		      5
    }
    Line {
      SrcBlock		      "Integrator1"
      SrcPort		      1
      DstBlock		      "Integrator2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Zero-Order\nHold"
      SrcPort		      1
      DstBlock		      "Integrator1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Integrator2"
      SrcPort		      1
      Points		      [20, 0]
      Branch {
	Points			[25, 0]
	DstBlock		"Scope"
	DstPort			1
      }
      Branch {
	Points			[0, 280; -840, 0]
	DstBlock		"Sum"
	DstPort			2
      }
    }
    Line {
      SrcBlock		      "Out"
      SrcPort		      1
      Points		      [5, 0]
      Branch {
	DstBlock		"Zero-Order\nHold"
	DstPort			1
      }
      Branch {
	DstBlock		"Scope1"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Sum"
      SrcPort		      1
      Points		      [5, 0; 0, -5; 5, 0]
      Branch {
	DstBlock		"In"
	DstPort			1
      }
      Branch {
	Points			[0, -50; 20, 0]
	DstBlock		"Scope2"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Sum1"
      SrcPort		      1
      Points		      [10, 0; 0, -5]
      Branch {
	DstBlock		"Sum"
	DstPort			1
      }
      Branch {
	Points			[15, 0; 0, -115; -30, 0]
	DstBlock		"Scope3"
	DstPort			1
      }
    }
    Annotation {
      Name		      "e(k)"
      Position		      [403, 303]
    }
    Annotation {
      Name		      "e(k-1)"
      Position		      [511, 304]
    }
    Annotation {
      Name		      "S(k)"
      Position		      [618, 379]
    }
    Annotation {
      Name		      "S(k-1)"
      Position		      [530, 478]
    }
    Annotation {
      Name		      "u(k)"
      Position		      [865, 301]
    }
  }
}
MatData {
  NumRecords		  1
  DataRecord {
    Tag			    DataTag0
    Data		    "  %)30     .    \" D   8    (     @         %    "
"\"     $    !     0         %  0 !@    $    &    <V%V960    .    P @   8    ("
"     @         %    \"     $    !     0         %  0 #     $    8    <VAA<F5D"
"        8V]M<&EL871I;VX #@   .@#   &    \"     (         !0    @    !     0  "
"  $         !0 $ !,    !    A0   &-O;7!I;&%T:6]N          !C;VUP:6QA=&EO;E]L="
"70     <VEM=6QI;FM?<&5R:6]D     &EN8W)?;F5T;&ES=         !T<FEM7W9B:71S      "
"      9&)L7V]V<F0              &1E<')E8V%T961?8V]N=')O;      .    0     8    "
"(    !          %    \"     $    '     0         $    #@   '0 80!R &< 90!T #$"
"    .    0 $   8    (     @         %    \"     $    !     0         %  0 !P "
"   $    .    :V5Y<P   '9A;'5E<P    X   !X    !@    @    !          4    (    "
" 0    $    !          X   !(    !@    @    $          4    (     0    L    ! "
"         0    6    2 !$ $P ( !. &4 = !L &D <P!T    #@   '     &    \"     $  "
"       !0    @    !     0    $         #@   $     &    \"     0         !0   "
" @    !    !P    $         !     X   !T &$ <@!G &4 =  Q    #@   $     &    \""
"     0         !0    @    !    !0    $         !     H    Q \"\\ ,0 P #      "
"    #@   #@    &    \"     0         !0    @    !     P    $         !     8 "
"  !O &8 9@    X   !@    !@    @    $          4    (     0   !<    !         "
" 0    N    10!V &4 <@!Y '< : !E '( 90 @ &D ;@ @ %, =0!B %, >0!S '0 90!M    #@"
"   &     &    \"     0         !0    @    !    &     $         !    #    !! &"
", 8P!O '( 9 !I &X 9P @ '0 ;P @ $( ; !O &, :P @ $T 80!S &L <P .    .     8    "
"(    !          %    \"     $    #     0         $    !@   &\\ 9@!F    #@   '"
"@$   &    \"     (         !0    @    !     0    $         !0 $  @    !    \""
"    '1A<F=E=#$ #@   # $   &    \"     (         !0    @    !     0    $      "
"   !0 $ !     !    P    'AI;&EN>&9A;6EL>0    !P87)T                <W!E960   "
"           '!A8VMA9V4           !S>6YT:&5S:7-?=&]O;   9&ER96-T;W)Y         '1"
"E<W1B96YC:         !S>7-C;&M?<&5R:6]D    8V]R95]G96YE<F%T:6]N ')U;E]C;W)E9V5N"
"      !E=F%L7V9I96QD        8VQO8VM?;&]C          X   !     !@    @    $     "
"     4    (     0    <    !          0    .    5@!I '( = !E '@ ,@    X   !   "
"  !@    @    $          4    (     0    @    !          0    0    > !C #( =@ "
"Q #  ,  P  X    P    !@    @    $          4    (     0    (    !          0 "
"!  M #0 #@   $     &    \"     0         !0    @    !    !0    $         !   "
"  H   !B &< -0 W #4         #@   #@    &    \"     0         !0    @    !    "
" P    $         !     8   !8 %, 5     X   !(    !@    @    $          4    ( "
"    0    D    !          0    2    +@ O &X 90!T &P :0!S '0         #@   #@   "
" &    \"     0         !0    @    !     P    $         !     8   !O &8 9@    "
"X    X    !@    @    $          4    (     0    ,    !          0    &    ,0 "
"P #     .    8     8    (    !          %    \"     $    8     0         $   "
" ,    $$ 8P!C &\\ <@!D &D ;@!G \"  = !O \"  0@!L &\\ 8P!K \"  30!A ', :P!S  X"
"    X    !@    @    $          4    (     0    ,    !          0    &    ;P!F"
" &8    .    ,     8    (    !          %    \"     $    !     0         $  ( "
",     X    P    !@    @    $          4    (               !          0      "
"   "
  }
}