library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;

--******************************************************************************
--**** ENTITY IEReg
--**** Deskripsi: Entity ini menguraikan register yang digunakan untuk menjaga
--****            enabled interrupts.
--******************************************************************************
ENTITY IEReg IS
    PORT(Interrupt                          : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
         clk,enable                         : IN STD_LOGIC;
         EIOut                              : OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END ENTITY IEReg;

ARCHITECTURE IEReg_behav OF IEReg IS
BEGIN
    name : PROCESS(clk) IS
    VARIABLE regValue : std_logic_vector(5 downto 0) := "000000";
    BEGIN
        IF(clk='1') THEN
            IF(enable='1') THEN
                regValue := Interrupt;
            END IF;

            EIOut <= regValue;

        END IF;
    END PROCESS name;
END ARCHITECTURE IEReg_behav;
