# XST (Creating Lso File) : 
pid_sg_full_001_clk_wrapper.lso
# xst flow : RunXST
pid_sg_full_001_clk_wrapper.syr
pid_sg_full_001_clk_wrapper.prj
pid_sg_full_001_clk_wrapper.sprj
pid_sg_full_001_clk_wrapper.ana
pid_sg_full_001_clk_wrapper.stx
pid_sg_full_001_clk_wrapper.cmd_log
pid_sg_full_001_clk_wrapper.ngc
pid_sg_full_001_clk_wrapper.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\matlab6p5\work\xpid_sg_full_001/_ngo
pid_sg_full_001_clk_wrapper.ngd
pid_sg_full_001_clk_wrapper_ngdbuild.nav
pid_sg_full_001_clk_wrapper.bld
.untf
pid_sg_full_001_clk_wrapper.cmd_log
# Implementation : Map
pid_sg_full_001_clk_wrapper_map.ncd
pid_sg_full_001_clk_wrapper.ngm
pid_sg_full_001_clk_wrapper.pcf
pid_sg_full_001_clk_wrapper.nc1
pid_sg_full_001_clk_wrapper.mrp
pid_sg_full_001_clk_wrapper_map.mrp
pid_sg_full_001_clk_wrapper.mdf
__projnav/map.log
pid_sg_full_001_clk_wrapper.cmd_log
MAP_NO_GUIDE_FILE_CPF "pid_sg_full_001_clk_wrapper"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
pid_sg_full_001_clk_wrapper.twr
pid_sg_full_001_clk_wrapper.twx
pid_sg_full_001_clk_wrapper.tsi
pid_sg_full_001_clk_wrapper.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
pid_sg_full_001_clk_wrapper.ncd
pid_sg_full_001_clk_wrapper.par
pid_sg_full_001_clk_wrapper.pad
pid_sg_full_001_clk_wrapper_pad.txt
pid_sg_full_001_clk_wrapper_pad.csv
pid_sg_full_001_clk_wrapper.pad_txt
pid_sg_full_001_clk_wrapper.dly
reportgen.log
pid_sg_full_001_clk_wrapper.xpi
pid_sg_full_001_clk_wrapper.grf
pid_sg_full_001_clk_wrapper.itr
pid_sg_full_001_clk_wrapper_last_par.ncd
__projnav/par.log
pid_sg_full_001_clk_wrapper.placed_ncd_tracker
pid_sg_full_001_clk_wrapper.routed_ncd_tracker
pid_sg_full_001_clk_wrapper.cmd_log
PAR_NO_GUIDE_FILE_CPF "pid_sg_full_001_clk_wrapper"
# Generate Programming File
__projnav/pid_sg_full_001_clk_wrapper_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
pid_sg_full_001_clk_wrapper.ut
# Generate Programming File
pid_sg_full_001_clk_wrapper.bgn
pid_sg_full_001_clk_wrapper.rbt
pid_sg_full_001_clk_wrapper.ll
pid_sg_full_001_clk_wrapper.msk
pid_sg_full_001_clk_wrapper.drc
pid_sg_full_001_clk_wrapper.nky
pid_sg_full_001_clk_wrapper.bit
pid_sg_full_001_clk_wrapper.bin
pid_sg_full_001_clk_wrapper.isc
pid_sg_full_001_clk_wrapper.cmd_log
# Implementation : Generate Post-Translate Simulation Model
pid_sg_full_001_clk_wrapper_translate.vhd
pid_sg_full_001_clk_wrapper_translate.vhd
pid_sg_full_001_clk_wrapper_translate.nlf
pid_sg_full_001_clk_wrapper.xlate_nlf
pid_sg_full_001_clk_wrapper.vhdsim_xlate
pid_sg_full_001_clk_wrapper.cmd_log
# Implmentation : Post-Map Static Timing
__projnav/pretrc.log
pid_sg_full_001_clk_wrapper_preroute.twr
pid_sg_full_001_clk_wrapper_preroute.twx
pid_sg_full_001_clk_wrapper.twx_map
pid_sg_full_001_clk_wrapper.tsi
pid_sg_full_001_clk_wrapper.tw1
pid_sg_full_001_clk_wrapper.cmd_log
# Implementation : Generate Primetime Netlist
pid_sg_full_001_clk_wrapper_sta.v
pid_sg_full_001_clk_wrapper_sta.nlf
pid_sg_full_001_clk_wrapper.par_sta_v
pid_sg_full_001_clk_wrapper.par_sta_nlf
# Implementation : Generate Post-Map Simulation Model
pid_sg_full_001_clk_wrapper_map.vhd
pid_sg_full_001_clk_wrapper_map.sdf
pid_sg_full_001_clk_wrapper_map.sdf
pid_sg_full_001_clk_wrapper_map.vhd
pid_sg_full_001_clk_wrapper_map.nlf
pid_sg_full_001_clk_wrapper.map_nlf
pid_sg_full_001_clk_wrapper.vhdsim_map
pid_sg_full_001_clk_wrapper.cmd_log
__projnav/netgen_map_tcl.rsp
# Generate Power Data
pid_sg_full_001_clk_wrapper.pwr
pid_sg_full_001_clk_wrapper_xpwr.xml
# Implementation : Generate Post-Par Simulation Model
pid_sg_full_001_clk_wrapper_timesim.vhd
pid_sg_full_001_clk_wrapper_timesim.sdf
pid_sg_full_001_clk_wrapper_timesim.sdf
pid_sg_full_001_clk_wrapper_timesim.vhd
pid_sg_full_001_clk_wrapper_timesim.nlf
pid_sg_full_001_clk_wrapper.par_nlf
pid_sg_full_001_clk_wrapper.vhdsim_par
pid_sg_full_001_clk_wrapper.cmd_log
__projnav/netgen_par_tcl.rsp
# Implementation : Generate IBIS Model (FPGA Flow)
pid_sg_full_001_clk_wrapper.ibs
pid_sg_full_001_clk_wrapper.cmd_log
# Implementation : Multi Pass Place & Route
__projnav/mppr.log
mppr_result.par
c:\matlab6p5\work\xpid_sg_full_001/mppr_result.dir
pid_sg_full_001_clk_wrapper.par
pid_sg_full_001_clk_wrapper.ncd
pid_sg_full_001_clk_wrapper.pad
pid_sg_full_001_clk_wrapper.dly
pid_sg_full_001_clk_wrapper.xpi
pid_sg_full_001_clk_wrapper.mppr
pid_sg_full_001_clk_wrapper.cmd_log
PAR_NO_GUIDE_FILE_CPF "pid_sg_full_001_clk_wrapper"
# Implmentation : Back-annotate Pin Locations
__projnav/ncdTOlck_tcl.rsp
pid_sg_full_001_clk_wrapper_last_ngd.ngd
pid_sg_full_001_clk_wrapper_last_ngd_report.bld
pid_sg_full_001_clk_wrapper.lck
pid_sg_full_001_clk_wrapper.lpc
pid_sg_full_001_clk_wrapper.cmd_log
# Generate Programming File
__projnav/pid_sg_full_001_clk_wrapper_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
pid_sg_full_001_clk_wrapper.ut
# Generate Programming File
pid_sg_full_001_clk_wrapper.bgn
pid_sg_full_001_clk_wrapper.rbt
pid_sg_full_001_clk_wrapper.ll
pid_sg_full_001_clk_wrapper.msk
pid_sg_full_001_clk_wrapper.drc
pid_sg_full_001_clk_wrapper.nky
pid_sg_full_001_clk_wrapper.bit
pid_sg_full_001_clk_wrapper.bin
pid_sg_full_001_clk_wrapper.isc
pid_sg_full_001_clk_wrapper.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
pid_sg_full_001_clk_wrapper.twr
pid_sg_full_001_clk_wrapper.twx
pid_sg_full_001_clk_wrapper.tsi
pid_sg_full_001_clk_wrapper.cmd_log
# Implementation : Generate Primetime Netlist
pid_sg_full_001_clk_wrapper_sta.v
pid_sg_full_001_clk_wrapper_sta.nlf
pid_sg_full_001_clk_wrapper.par_sta_v
pid_sg_full_001_clk_wrapper.par_sta_nlf
# Generate Power Data
pid_sg_full_001_clk_wrapper.pwr
pid_sg_full_001_clk_wrapper_xpwr.xml
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\matlab6p5\work\xpid_sg_full_001/_ngo
pid_sg_full_001_clk_wrapper.ngd
pid_sg_full_001_clk_wrapper_ngdbuild.nav
pid_sg_full_001_clk_wrapper.bld
.untf
pid_sg_full_001_clk_wrapper.cmd_log
# Implementation : Map
pid_sg_full_001_clk_wrapper_map.ncd
pid_sg_full_001_clk_wrapper.ngm
pid_sg_full_001_clk_wrapper.pcf
pid_sg_full_001_clk_wrapper.nc1
pid_sg_full_001_clk_wrapper.mrp
pid_sg_full_001_clk_wrapper_map.mrp
pid_sg_full_001_clk_wrapper.mdf
__projnav/map.log
pid_sg_full_001_clk_wrapper.cmd_log
MAP_NO_GUIDE_FILE_CPF "pid_sg_full_001_clk_wrapper"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
pid_sg_full_001_clk_wrapper.twr
pid_sg_full_001_clk_wrapper.twx
pid_sg_full_001_clk_wrapper.tsi
pid_sg_full_001_clk_wrapper.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
pid_sg_full_001_clk_wrapper.ncd
pid_sg_full_001_clk_wrapper.par
pid_sg_full_001_clk_wrapper.pad
pid_sg_full_001_clk_wrapper_pad.txt
pid_sg_full_001_clk_wrapper_pad.csv
pid_sg_full_001_clk_wrapper.pad_txt
pid_sg_full_001_clk_wrapper.dly
reportgen.log
pid_sg_full_001_clk_wrapper.xpi
pid_sg_full_001_clk_wrapper.grf
pid_sg_full_001_clk_wrapper.itr
pid_sg_full_001_clk_wrapper_last_par.ncd
__projnav/par.log
pid_sg_full_001_clk_wrapper.placed_ncd_tracker
pid_sg_full_001_clk_wrapper.routed_ncd_tracker
pid_sg_full_001_clk_wrapper.cmd_log
PAR_NO_GUIDE_FILE_CPF "pid_sg_full_001_clk_wrapper"
# Generate Programming File
__projnav/pid_sg_full_001_clk_wrapper_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
pid_sg_full_001_clk_wrapper.ut
# Generate Programming File
pid_sg_full_001_clk_wrapper.bgn
pid_sg_full_001_clk_wrapper.rbt
pid_sg_full_001_clk_wrapper.ll
pid_sg_full_001_clk_wrapper.msk
pid_sg_full_001_clk_wrapper.drc
pid_sg_full_001_clk_wrapper.nky
pid_sg_full_001_clk_wrapper.bit
pid_sg_full_001_clk_wrapper.bin
pid_sg_full_001_clk_wrapper.isc
pid_sg_full_001_clk_wrapper.cmd_log
# Implmentation : Floorplan Design
__projnav/xlateFloorPlanner.rsp
# Implementation : View/Edit Routed Design (FPGA Editor)
pid_sg_full_001_clk_wrapper_map_fpga_editor.log
pid_sg_full_001_clk_wrapper_fpga_editor.out
pid_sg_full_001_clk_wrapper_fpga_editor.log
__projnav/pfea_tcl.rsp
# Implmentation : View/Edit Placed Design (Floorplanner)
__projnav/parFloorPlanner.rsp
pid_sg_full_001_clk_wrapper.mfp
# Implmentation : Analyze Post-Place & Route Static Timing (Timing Analyzer)
# Implmentation : View/Edit Placed Design (Floorplanner)
__projnav/parFloorPlanner.rsp
pid_sg_full_001_clk_wrapper.mfp
# Implementation : View/Edit Routed Design (FPGA Editor)
pid_sg_full_001_clk_wrapper_map_fpga_editor.log
pid_sg_full_001_clk_wrapper_fpga_editor.out
pid_sg_full_001_clk_wrapper_fpga_editor.log
__projnav/pfea_tcl.rsp
# Implmentation : View/Edit Placed Design (Floorplanner)
__projnav/parFloorPlanner.rsp
pid_sg_full_001_clk_wrapper.mfp
