library ieee;
use ieee.std_logic_1164.all;

entity regCU is
   port(T, Clk, Rst : in std_logic;
        Q : out std_logic);
end regCU;

architecture regCU_behav of regCU is
begin
  process(Clk, Rst)
    variable Qtmp : std_logic;
  begin
    if (Rst = '1') then
       Qtmp := '0';
    elsif Clk = '1' and Clk'event then
       if T = '1' then
          Qtmp := not Qtmp;
       end if;
    end if;
    Q <= Qtmp;
  end process;
end regCU_behav;
