Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.51 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.51 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: top_spartan21.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top_spartan21.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top_spartan21
Output Format                      : NGC
Target Device                      : xc2s50-6-pq208

---- Source Options
Top Module Name                    : top_spartan21
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top_spartan21.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator greatequal for signal <$n0003> created at line 20.
    Found 19-bit up counter for signal <clock_cnt>.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <top_spartan21>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf.
Unit <top_spartan21> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 3
 18-bit up counter                 : 1
 32-bit up counter                 : 1
 19-bit up counter                 : 1
# Registers                        : 6
 1-bit register                    : 5
 2-bit register                    : 1
# Comparators                      : 1
 32-bit comparator greatequal      : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan21> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_spartan21, actual ratio is 42.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top_spartan21.ngr
Top Level Output File Name         : top_spartan21
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 30

Macro Statistics :
# Registers                        : 9
#      1-bit register              : 5
#      18-bit register             : 3
#      2-bit register              : 1
# Adders/Subtractors               : 3
#      18-bit adder                : 3
# Comparators                      : 1
#      32-bit comparator greatequal: 1

Cell Usage :
# BELS                             : 1409
#      BUF                         : 105
#      GND                         : 8
#      LUT1                        : 71
#      LUT1_L                      : 8
#      LUT2                        : 6
#      LUT3                        : 8
#      LUT3_D                      : 23
#      LUT3_L                      : 4
#      LUT4                        : 450
#      LUT4_D                      : 2
#      LUT4_L                      : 8
#      MUXCY                       : 361
#      VCC                         : 3
#      XORCY                       : 352
# FlipFlops/Latches                : 116
#      FD                          : 19
#      FDC                         : 21
#      FDE                         : 73
#      FDP                         : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 29
#      IBUF                        : 17
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     336  out of    768    43%  
 Number of Slice Flip Flops:           116  out of   1536     7%  
 Number of 4 input LUTs:               580  out of   1536    37%  
 Number of bonded IOBs:                 29  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_10_clock_div10ms:Q            | NONE                   | 40    |
clock                              | BUFGP                  | 70    |
XLXI_2_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.275ns
   Maximum combinational path delay: 35.811ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clock'
Delay:               8.776ns (Levels of Logic = 3)
  Source:            XLXI_10_clock_cnt_5 (FF)
  Destination:       XLXI_10_count_30 (FF)
  Source Clock:      clock rising
  Destination Clock: clock rising

  Data Path: XLXI_10_clock_cnt_5 to XLXI_10_count_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   1.085   1.206  XLXI_10_clock_cnt_5 (XLXI_10_clock_cnt_5)
     LUT4_L:I0->LO         1   0.549   0.100  XLXI_10__n000260 (CHOICE190)
     LUT4:I0->O            3   0.549   1.332  XLXI_10__n000285_SW0 (N12972)
     LUT4:I0->O           16   0.549   2.520  XLXI_10__n000285_2 (XLXI_10__n000285_2)
     FDE:CE                    0.886          XLXI_10_count_9
    ----------------------------------------
    Total                      8.776ns (3.618ns logic, 5.158ns route)
                                       (41.2% logic, 58.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_10_clock_div10ms:Q'
Delay:               9.302ns (Levels of Logic = 28)
  Source:            XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u20 (FF)
  Destination:       XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u219 (FF)
  Source Clock:      XLXI_10_clock_div10ms:Q rising
  Destination Clock: XLXI_10_clock_div10ms:Q rising

  Data Path: XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u20 to XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u219
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   1.085   1.035  XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u20 (XLXI_4_spartan2_top_q_x_0<0>)
     begin scope: 'XLXI_4_spartan2_top_addsub3_core_instance4'
     LUT4:I1->O            1   0.549   0.000  BU3 (N2)
     MUXCY:S->O            1   0.659   0.000  BU4 (N5)
     MUXCY:CI->O           1   0.042   0.000  BU8 (N10)
     MUXCY:CI->O           1   0.042   0.000  BU12 (N15)
     MUXCY:CI->O           1   0.042   0.000  BU16 (N20)
     MUXCY:CI->O           1   0.042   0.000  BU20 (N25)
     MUXCY:CI->O           1   0.042   0.000  BU24 (N30)
     MUXCY:CI->O           1   0.042   0.000  BU28 (N35)
     MUXCY:CI->O           1   0.042   0.000  BU32 (N40)
     MUXCY:CI->O           1   0.042   0.000  BU36 (N45)
     MUXCY:CI->O           1   0.042   0.000  BU40 (N50)
     MUXCY:CI->O           1   0.042   0.000  BU44 (N55)
     MUXCY:CI->O           1   0.042   0.000  BU48 (N60)
     MUXCY:CI->O           1   0.042   0.000  BU52 (N65)
     MUXCY:CI->O           1   0.042   0.000  BU56 (N70)
     MUXCY:CI->O           1   0.042   0.000  BU60 (N75)
     MUXCY:CI->O           1   0.042   0.000  BU64 (N80)
     MUXCY:CI->O           1   0.042   0.000  BU68 (N85)
     MUXCY:CI->O           1   0.042   0.000  BU72 (N90)
     MUXCY:CI->O           1   0.042   0.000  BU76 (N95)
     MUXCY:CI->O           1   0.042   0.000  BU80 (N100)
     MUXCY:CI->O           1   0.042   0.000  BU84 (N105)
     MUXCY:CI->O           1   0.042   0.000  BU88 (N110)
     MUXCY:CI->O           1   0.042   0.000  BU92 (N115)
     MUXCY:CI->O           0   0.042   0.000  BU96 (N120)
     XORCY:CI->O          30   0.420   3.330  BU100 (s<24>)
     end scope: 'XLXI_4_spartan2_top_addsub3_core_instance4'
     LUT3_D:I2->LO         1   0.549   0.000  XLXI_4_spartan2_top_addsub3_conv_s<8>1 (N13018)
     FDE:D                     0.709          XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u28
    ----------------------------------------
    Total                      9.302ns (4.937ns logic, 4.365ns route)
                                       (53.1% logic, 46.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_2_clock_cnt_17:Q'
Delay:               4.008ns (Levels of Logic = 1)
  Source:            XLXI_3_clk_int_0 (FF)
  Destination:       XLXI_3_clk_int_0 (FF)
  Source Clock:      XLXI_2_clock_cnt_17:Q rising
  Destination Clock: XLXI_2_clock_cnt_17:Q rising

  Data Path: XLXI_3_clk_int_0 to XLXI_3_clk_int_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              6   1.085   1.665  XLXI_3_clk_int_0 (XLXI_3_clk_int_0)
     LUT1:I0->O            1   0.549   0.000  XLXI_3_Madd__old_clk_int_1__n00031 (XLXI_3__old_clk_int_1<0>)
     FDC:D                     0.709          XLXI_3_clk_int_0
    ----------------------------------------
    Total                      4.008ns (2.343ns logic, 1.665ns route)
                                       (58.5% logic, 41.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_10_clock_div10ms:Q'
Offset:              10.838ns (Levels of Logic = 29)
  Source:            in_x_0<0> (PAD)
  Destination:       XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u219 (FF)
  Destination Clock: XLXI_10_clock_div10ms:Q rising

  Data Path: in_x_0<0> to XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u219
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            20   0.776   2.880  in_x_0_0_IBUF (in_x_0_0_IBUF)
     begin scope: 'XLXI_4_spartan2_top_addsub3_core_instance4'
     LUT4:I0->O            1   0.549   0.000  BU3 (N2)
     MUXCY:S->O            1   0.659   0.000  BU4 (N5)
     MUXCY:CI->O           1   0.042   0.000  BU8 (N10)
     MUXCY:CI->O           1   0.042   0.000  BU12 (N15)
     MUXCY:CI->O           1   0.042   0.000  BU16 (N20)
     MUXCY:CI->O           1   0.042   0.000  BU20 (N25)
     MUXCY:CI->O           1   0.042   0.000  BU24 (N30)
     MUXCY:CI->O           1   0.042   0.000  BU28 (N35)
     MUXCY:CI->O           1   0.042   0.000  BU32 (N40)
     MUXCY:CI->O           1   0.042   0.000  BU36 (N45)
     MUXCY:CI->O           1   0.042   0.000  BU40 (N50)
     MUXCY:CI->O           1   0.042   0.000  BU44 (N55)
     MUXCY:CI->O           1   0.042   0.000  BU48 (N60)
     MUXCY:CI->O           1   0.042   0.000  BU52 (N65)
     MUXCY:CI->O           1   0.042   0.000  BU56 (N70)
     MUXCY:CI->O           1   0.042   0.000  BU60 (N75)
     MUXCY:CI->O           1   0.042   0.000  BU64 (N80)
     MUXCY:CI->O           1   0.042   0.000  BU68 (N85)
     MUXCY:CI->O           1   0.042   0.000  BU72 (N90)
     MUXCY:CI->O           1   0.042   0.000  BU76 (N95)
     MUXCY:CI->O           1   0.042   0.000  BU80 (N100)
     MUXCY:CI->O           1   0.042   0.000  BU84 (N105)
     MUXCY:CI->O           1   0.042   0.000  BU88 (N110)
     MUXCY:CI->O           1   0.042   0.000  BU92 (N115)
     MUXCY:CI->O           0   0.042   0.000  BU96 (N120)
     XORCY:CI->O          30   0.420   3.330  BU100 (s<24>)
     end scope: 'XLXI_4_spartan2_top_addsub3_core_instance4'
     LUT3_D:I2->LO         1   0.549   0.000  XLXI_4_spartan2_top_addsub3_conv_s<8>1 (N13018)
     FDE:D                     0.709          XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u28
    ----------------------------------------
    Total                     10.838ns (4.628ns logic, 6.210ns route)
                                       (42.7% logic, 57.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_2_clock_cnt_17:Q'
Offset:              10.829ns (Levels of Logic = 3)
  Source:            XLXI_3_anode1 (FF)
  Destination:       cathode<7> (PAD)
  Source Clock:      XLXI_2_clock_cnt_17:Q rising

  Data Path: XLXI_3_anode1 to cathode<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              9   1.085   1.908  XLXI_3_anode1 (XLXI_3_anode1)
     LUT4:I0->O            1   0.549   1.035  XLXI_3_digit<1>_SW0 (N12344)
     LUT3:I1->O            1   0.549   1.035  XLXI_3_digit<1> (cathode_1_OBUF)
     OBUF:I->O                 4.668          cathode_1_OBUF (cathode<1>)
    ----------------------------------------
    Total                     10.829ns (6.851ns logic, 3.978ns route)
                                       (63.3% logic, 36.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_10_clock_div10ms:Q'
Offset:              34.275ns (Levels of Logic = 70)
  Source:            XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u20 (FF)
  Destination:       cathode<7> (PAD)
  Source Clock:      XLXI_10_clock_div10ms:Q rising

  Data Path: XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u20 to cathode<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   1.085   1.035  XLXI_4_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u20 (XLXI_4_spartan2_top_q_x_0<0>)
     begin scope: 'XLXI_4_spartan2_top_addsub3_core_instance4'
     LUT4:I1->O            1   0.549   0.000  BU3 (N2)
     MUXCY:S->O            1   0.659   0.000  BU4 (N5)
     MUXCY:CI->O           1   0.042   0.000  BU8 (N10)
     MUXCY:CI->O           1   0.042   0.000  BU12 (N15)
     MUXCY:CI->O           1   0.042   0.000  BU16 (N20)
     MUXCY:CI->O           1   0.042   0.000  BU20 (N25)
     MUXCY:CI->O           1   0.042   0.000  BU24 (N30)
     MUXCY:CI->O           1   0.042   0.000  BU28 (N35)
     MUXCY:CI->O           1   0.042   0.000  BU32 (N40)
     MUXCY:CI->O           1   0.042   0.000  BU36 (N45)
     MUXCY:CI->O           1   0.042   0.000  BU40 (N50)
     MUXCY:CI->O           1   0.042   0.000  BU44 (N55)
     MUXCY:CI->O           1   0.042   0.000  BU48 (N60)
     MUXCY:CI->O           1   0.042   0.000  BU52 (N65)
     MUXCY:CI->O           1   0.042   0.000  BU56 (N70)
     MUXCY:CI->O           1   0.042   0.000  BU60 (N75)
     MUXCY:CI->O           1   0.042   0.000  BU64 (N80)
     MUXCY:CI->O           1   0.042   0.000  BU68 (N85)
     MUXCY:CI->O           1   0.042   0.000  BU72 (N90)
     MUXCY:CI->O           1   0.042   0.000  BU76 (N95)
     MUXCY:CI->O           1   0.042   0.000  BU80 (N100)
     MUXCY:CI->O           1   0.042   0.000  BU84 (N105)
     MUXCY:CI->O           1   0.042   0.000  BU88 (N110)
     MUXCY:CI->O           1   0.042   0.000  BU92 (N115)
     MUXCY:CI->O           0   0.042   0.000  BU96 (N120)
     XORCY:CI->O          30   0.420   3.330  BU100 (s<24>)
     end scope: 'XLXI_4_spartan2_top_addsub3_core_instance4'
     LUT3_D:I2->O          7   0.549   1.755  XLXI_4_spartan2_top_addsub3_conv_s<0>1 (XLXI_4_spartan2_top_s_x_1<0>)
     begin scope: 'XLXI_4_spartan2_top_ki_core_instance2'
     LUT4:I0->O            1   0.549   1.035  BU54 (N2235)
     LUT4:I0->O            1   0.549   0.000  BU115 (N5708)
     MUXCY:S->O            1   0.659   0.000  BU116 (N5711)
     MUXCY:CI->O           1   0.042   0.000  BU120 (N5716)
     MUXCY:CI->O           1   0.042   0.000  BU124 (N5721)
     MUXCY:CI->O           1   0.042   0.000  BU128 (N5726)
     MUXCY:CI->O           1   0.042   0.000  BU132 (N5731)
     MUXCY:CI->O           1   0.042   0.000  BU136 (N5736)
     XORCY:CI->O           1   0.420   1.035  BU141 (N1205)
     LUT4:I0->O            1   0.549   0.000  BU275 (N7254)
     MUXCY:S->O            1   0.659   0.000  BU276 (N7257)
     MUXCY:CI->O           1   0.042   0.000  BU280 (N7262)
     MUXCY:CI->O           1   0.042   0.000  BU284 (N7267)
     MUXCY:CI->O           1   0.042   0.000  BU288 (N7272)
     MUXCY:CI->O           1   0.042   0.000  BU292 (N7277)
     MUXCY:CI->O           1   0.042   0.000  BU296 (N7282)
     MUXCY:CI->O           1   0.042   0.000  BU300 (N7287)
     MUXCY:CI->O           1   0.042   0.000  BU304 (N7292)
     MUXCY:CI->O           1   0.042   0.000  BU308 (N7297)
     XORCY:CI->O           1   0.420   1.035  BU313 (N1254)
     LUT4:I0->O            1   0.549   0.000  BU456 (N8021)
     MUXCY:S->O            1   0.659   0.000  BU457 (N8024)
     MUXCY:CI->O           1   0.042   0.000  BU461 (N8029)
     MUXCY:CI->O           1   0.042   0.000  BU465 (N8034)
     MUXCY:CI->O           1   0.042   0.000  BU469 (N8039)
     MUXCY:CI->O           1   0.042   0.000  BU473 (N8044)
     MUXCY:CI->O           1   0.042   0.000  BU477 (N8049)
     MUXCY:CI->O           1   0.042   0.000  BU481 (N8054)
     XORCY:CI->O          14   0.420   2.340  BU486 (N254)
     BUF:I->O              1   0.549   1.035  BU520 (o<26>)
     end scope: 'XLXI_4_spartan2_top_ki_core_instance2'
     begin scope: 'XLXI_4_spartan2_top_addsub4_core_instance6'
     LUT4:I1->O            1   0.549   0.000  BU107 (N132)
     MUXCY:S->O            1   0.659   0.000  BU108 (N135)
     MUXCY:CI->O           1   0.042   0.000  BU112 (N140)
     MUXCY:CI->O           1   0.042   0.000  BU116 (N145)
     MUXCY:CI->O           1   0.042   0.000  BU120 (N150)
     MUXCY:CI->O           1   0.042   0.000  BU124 (N155)
     XORCY:CI->O           1   0.420   1.035  BU129 (s<31>)
     end scope: 'XLXI_4_spartan2_top_addsub4_core_instance6'
     LUT4:I2->O            1   0.549   1.035  XLXI_3_digit<7>_SW0 (N12421)
     LUT3:I1->O            1   0.549   1.035  XLXI_3_digit<7> (cathode_7_OBUF)
     OBUF:I->O                 4.668          cathode_7_OBUF (cathode<7>)
    ----------------------------------------
    Total                     34.275ns (18.570ns logic, 15.705ns route)
                                       (54.2% logic, 45.8% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               35.811ns (Levels of Logic = 71)
  Source:            in_x_0<0> (PAD)
  Destination:       cathode<7> (PAD)

  Data Path: in_x_0<0> to cathode<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            20   0.776   2.880  in_x_0_0_IBUF (in_x_0_0_IBUF)
     begin scope: 'XLXI_4_spartan2_top_addsub3_core_instance4'
     LUT4:I0->O            1   0.549   0.000  BU3 (N2)
     MUXCY:S->O            1   0.659   0.000  BU4 (N5)
     MUXCY:CI->O           1   0.042   0.000  BU8 (N10)
     MUXCY:CI->O           1   0.042   0.000  BU12 (N15)
     MUXCY:CI->O           1   0.042   0.000  BU16 (N20)
     MUXCY:CI->O           1   0.042   0.000  BU20 (N25)
     MUXCY:CI->O           1   0.042   0.000  BU24 (N30)
     MUXCY:CI->O           1   0.042   0.000  BU28 (N35)
     MUXCY:CI->O           1   0.042   0.000  BU32 (N40)
     MUXCY:CI->O           1   0.042   0.000  BU36 (N45)
     MUXCY:CI->O           1   0.042   0.000  BU40 (N50)
     MUXCY:CI->O           1   0.042   0.000  BU44 (N55)
     MUXCY:CI->O           1   0.042   0.000  BU48 (N60)
     MUXCY:CI->O           1   0.042   0.000  BU52 (N65)
     MUXCY:CI->O           1   0.042   0.000  BU56 (N70)
     MUXCY:CI->O           1   0.042   0.000  BU60 (N75)
     MUXCY:CI->O           1   0.042   0.000  BU64 (N80)
     MUXCY:CI->O           1   0.042   0.000  BU68 (N85)
     MUXCY:CI->O           1   0.042   0.000  BU72 (N90)
     MUXCY:CI->O           1   0.042   0.000  BU76 (N95)
     MUXCY:CI->O           1   0.042   0.000  BU80 (N100)
     MUXCY:CI->O           1   0.042   0.000  BU84 (N105)
     MUXCY:CI->O           1   0.042   0.000  BU88 (N110)
     MUXCY:CI->O           1   0.042   0.000  BU92 (N115)
     MUXCY:CI->O           0   0.042   0.000  BU96 (N120)
     XORCY:CI->O          30   0.420   3.330  BU100 (s<24>)
     end scope: 'XLXI_4_spartan2_top_addsub3_core_instance4'
     LUT3_D:I2->O          7   0.549   1.755  XLXI_4_spartan2_top_addsub3_conv_s<0>1 (XLXI_4_spartan2_top_s_x_1<0>)
     begin scope: 'XLXI_4_spartan2_top_ki_core_instance2'
     LUT4:I0->O            1   0.549   1.035  BU54 (N2235)
     LUT4:I0->O            1   0.549   0.000  BU115 (N5708)
     MUXCY:S->O            1   0.659   0.000  BU116 (N5711)
     MUXCY:CI->O           1   0.042   0.000  BU120 (N5716)
     MUXCY:CI->O           1   0.042   0.000  BU124 (N5721)
     MUXCY:CI->O           1   0.042   0.000  BU128 (N5726)
     MUXCY:CI->O           1   0.042   0.000  BU132 (N5731)
     MUXCY:CI->O           1   0.042   0.000  BU136 (N5736)
     XORCY:CI->O           1   0.420   1.035  BU141 (N1205)
     LUT4:I0->O            1   0.549   0.000  BU275 (N7254)
     MUXCY:S->O            1   0.659   0.000  BU276 (N7257)
     MUXCY:CI->O           1   0.042   0.000  BU280 (N7262)
     MUXCY:CI->O           1   0.042   0.000  BU284 (N7267)
     MUXCY:CI->O           1   0.042   0.000  BU288 (N7272)
     MUXCY:CI->O           1   0.042   0.000  BU292 (N7277)
     MUXCY:CI->O           1   0.042   0.000  BU296 (N7282)
     MUXCY:CI->O           1   0.042   0.000  BU300 (N7287)
     MUXCY:CI->O           1   0.042   0.000  BU304 (N7292)
     MUXCY:CI->O           1   0.042   0.000  BU308 (N7297)
     XORCY:CI->O           1   0.420   1.035  BU313 (N1254)
     LUT4:I0->O            1   0.549   0.000  BU456 (N8021)
     MUXCY:S->O            1   0.659   0.000  BU457 (N8024)
     MUXCY:CI->O           1   0.042   0.000  BU461 (N8029)
     MUXCY:CI->O           1   0.042   0.000  BU465 (N8034)
     MUXCY:CI->O           1   0.042   0.000  BU469 (N8039)
     MUXCY:CI->O           1   0.042   0.000  BU473 (N8044)
     MUXCY:CI->O           1   0.042   0.000  BU477 (N8049)
     MUXCY:CI->O           1   0.042   0.000  BU481 (N8054)
     XORCY:CI->O          14   0.420   2.340  BU486 (N254)
     BUF:I->O              1   0.549   1.035  BU520 (o<26>)
     end scope: 'XLXI_4_spartan2_top_ki_core_instance2'
     begin scope: 'XLXI_4_spartan2_top_addsub4_core_instance6'
     LUT4:I1->O            1   0.549   0.000  BU107 (N132)
     MUXCY:S->O            1   0.659   0.000  BU108 (N135)
     MUXCY:CI->O           1   0.042   0.000  BU112 (N140)
     MUXCY:CI->O           1   0.042   0.000  BU116 (N145)
     MUXCY:CI->O           1   0.042   0.000  BU120 (N150)
     MUXCY:CI->O           1   0.042   0.000  BU124 (N155)
     XORCY:CI->O           1   0.420   1.035  BU129 (s<31>)
     end scope: 'XLXI_4_spartan2_top_addsub4_core_instance6'
     LUT4:I2->O            1   0.549   1.035  XLXI_3_digit<7>_SW0 (N12421)
     LUT3:I1->O            1   0.549   1.035  XLXI_3_digit<7> (cathode_7_OBUF)
     OBUF:I->O                 4.668          cathode_7_OBUF (cathode<7>)
    ----------------------------------------
    Total                     35.811ns (18.261ns logic, 17.550ns route)
                                       (51.0% logic, 49.0% route)

=========================================================================
CPU : 16.30 / 17.31 s | Elapsed : 16.00 / 17.00 s
 
--> 

Total memory usage is 73484 kilobytes


