Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <spartan2_addsub1> (Architecture <behavior>) compiled.
Entity <spartan2_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <spartan2> (Architecture <structural>) compiled.
Entity <spartan2_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Entity <spartan2_clk_wrapper> (Architecture <structural>) compiled.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_86c498140491d6df.edn" "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.edn" "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_adf215fec985a9ef.edn" "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.edn" "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_fe654cf32dc31d3a.edn" "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_5cb3e9894aa707ba.edn" "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_22d1b55eb2467aac.edn" "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <spartan2_clk_wrapper> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block spartan2_clk_wrapper, actual ratio is 33.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     259  out of    768    33%  
 Number of Slice Flip Flops:            40  out of   1536     2%  
 Number of 4 input LUTs:               461  out of   1536    30%  
 Number of bonded IOBs:                 40  out of    144    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 40    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 31.107ns
   Maximum combinational path delay: 32.643ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xspartan2/_ngo -i -p
xc2s50-pq208-6 spartan2_clk_wrapper.ngc spartan2_clk_wrapper.ngd 

Reading NGO file "D:/isnique/work/xspartan2/spartan2_clk_wrapper.ngc" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_86c498140491d6df.edn"
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.n
go"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xspartan2/_ngo/adder_subtracter_spartan2_6_0_86c498140491d6df.n
go"...
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_9b2656d23c19deaf.edn"
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xspartan2/_ngo/adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.edn"
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.n
go"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xspartan2/_ngo/adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.n
go"...
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_fe654cf32dc31d3a.edn"
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xspartan2/_ngo/multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_5cb3e9894aa707ba.edn"
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xspartan2/_ngo/multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"...
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_22d1b55eb2467aac.edn"
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xspartan2/_ngo/multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_adf215fec985a9ef.edn"
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fec985a9ef.n
go"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xspartan2/_ngo/adder_subtracter_spartan2_6_0_adf215fec985a9ef.n
go"...
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fec985a9ef.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(0)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(1)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(2)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(3)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(4)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(5)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(6)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(7)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(32)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(33)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(34)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(35)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(36)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(37)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(38)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(39)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(40)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(41)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(42)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(43)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(44)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(45)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(46)'
   has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 39788 kilobytes

Writing NGD file "spartan2_clk_wrapper.ngd" ...

Writing NGDBUILD log file "spartan2_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        24 out of  1,536    1%
  Number of 4 input LUTs:           361 out of  1,536   23%
Logic Distribution:
    Number of occupied Slices:                         187 out of    768   24%
    Number of Slices containing only related logic:    187 out of    187  100%
    Number of Slices containing unrelated logic:         0 out of    187    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          364 out of  1,536   23%
      Number used as logic:                       361
      Number used as a route-thru:                  3
   Number of bonded IOBs:            40 out of    140   28%
      IOB Flip Flops:                              16
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,719
Additional JTAG gate count for IOBs:  1,968
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "spartan2_clk_wrapper_map.mrp" for details.
Completed process "Map".

Mapping Module spartan2_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o spartan2_clk_wrapper_map.ncd spartan2_clk_wrapper.ngd spartan2_clk_wrapper.pcf
Mapping Module spartan2_clk_wrapper: DONE



Started process "Place & Route".





Constraints file: spartan2_clk_wrapper.pcf

Loading device database for application Par from file
"spartan2_clk_wrapper_map.ncd".
   "spartan2_clk_wrapper" is an NCD, version 2.38, device xc2s50, package pq208,
speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            40 out of 140    28%
      Number of LOCed External IOBs    0 out of 40      0%

   Number of SLICEs                  187 out of 768    24%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:989959) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
......
.
Phase 5.8 (Checksum:9d598a) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file spartan2_clk_wrapper.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 1040 unrouted;       REAL time: 2 secs 

Phase 2: 1007 unrouted;       REAL time: 6 secs 

Phase 3: 223 unrouted;       REAL time: 6 secs 

Phase 4: 223 unrouted; (0)      REAL time: 6 secs 

Phase 5: 223 unrouted; (0)      REAL time: 6 secs 

Phase 6: 223 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   28   |  0.080     |  0.465      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_8917ce66 = PERIOD TIMEGRP "clk_891 | 100.000ns  | 7.640ns    | 14   
  7ce66"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  57 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file spartan2_clk_wrapper.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Wed Aug 03 10:25:04 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module spartan2_clk_wrapper . . .
PAR command line: par -w -intstyle ise -ol std -t 1 spartan2_clk_wrapper_map.ncd spartan2_clk_wrapper.ncd spartan2_clk_wrapper.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library
work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <spartan2_addsub1> (Architecture <behavior>) compiled.
Entity <spartan2_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <spartan2> (Architecture <structural>) compiled.
Entity <spartan2_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in
Library work.
Entity <spartan2_clk_wrapper> (Architecture <structural>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library
work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <spartan2_addsub1> (Architecture <behavior>) compiled.
Entity <spartan2_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <spartan2> (Architecture <structural>) compiled.
Entity <spartan2_clock_driver> (Architecture <structural>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.


Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 15.72 / 17.13 s | Elapsed : 16.00 / 17.00 s
 
--> 

Total memory usage is 71352 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <spartan2_addsub1> (Architecture <behavior>).
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <synth_addsub> (Architecture <behavior>).
	arith_type = 1
	a_width = 17
	b_width = 17
	s_width = 17
	mode = 1
	use_cin = 0
	use_bin = 0
	latency = 0
Entity <synth_addsub> analyzed. Unit <synth_addsub> generated.


Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <synth_addsub>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
WARNING:Xst:647 - Input <cin<0>> is never used.
WARNING:Xst:646 - Signal <cin_sub<0>> is assigned but never used.
    Found 17-bit adder for signal <$n0036> created at line 1131.
    Summary:
	inferred   1 Adder/Subtracter(s).
Unit <synth_addsub> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:646 - Signal <temp_cout> is assigned but never used.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 17-bit adder                      : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <spartan2_addsub1> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
WARNING:Xst:1665 - Line 6: Can not define group with TNM_NET on INST or PIN. Constraint ignored.
Last warning will be issued only once.
XCF parsing done.
ERROR:Xst:1396 - Processing TIMESPEC TS_clk_8917ce66: No TNM or User group name clk_8917ce66 is defined.
ERROR:Xst:1489 - Constraint annotation failed.
CPU : 3.19 / 4.48 s | Elapsed : 3.00 / 5.00 s
 
--> 

Total memory usage is 55992 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <spartan2_addsub1> (Architecture <behavior>) compiled.
Entity <spartan2_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <spartan2> (Architecture <structural>) compiled.
Entity <spartan2_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <spartan2_clk_wrapper> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block spartan2_clk_wrapper, actual ratio is 33.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     259  out of    768    33%  
 Number of Slice Flip Flops:            40  out of   1536     2%  
 Number of 4 input LUTs:               461  out of   1536    30%  
 Number of bonded IOBs:                 40  out of    144    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 40    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 31.107ns
   Maximum combinational path delay: 32.643ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xspartan2/_ngo -i -p
xc2s50-pq208-6 spartan2_clk_wrapper.ngc spartan2_clk_wrapper.ngd 

Reading NGO file "D:/isnique/work/xspartan2/spartan2_clk_wrapper.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fec985a9ef.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(0)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(1)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(2)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(3)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(4)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(5)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(6)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(7)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(32)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(33)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(34)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(35)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(36)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(37)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(38)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(39)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(40)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(41)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(42)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(43)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(44)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(45)'
   has no load
WARNING:NgdBuild:454 - logical net 'spartan2_top_addsub4_core_instance6/S(46)'
   has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 39728 kilobytes

Writing NGD file "spartan2_clk_wrapper.ngd" ...

Writing NGDBUILD log file "spartan2_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        24 out of  1,536    1%
  Number of 4 input LUTs:           361 out of  1,536   23%
Logic Distribution:
    Number of occupied Slices:                         187 out of    768   24%
    Number of Slices containing only related logic:    187 out of    187  100%
    Number of Slices containing unrelated logic:         0 out of    187    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          364 out of  1,536   23%
      Number used as logic:                       361
      Number used as a route-thru:                  3
   Number of bonded IOBs:            40 out of    140   28%
      IOB Flip Flops:                              16
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,719
Additional JTAG gate count for IOBs:  1,968
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "spartan2_clk_wrapper_map.mrp" for details.
Completed process "Map".

Mapping Module spartan2_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o spartan2_clk_wrapper_map.ncd spartan2_clk_wrapper.ngd spartan2_clk_wrapper.pcf
Mapping Module spartan2_clk_wrapper: DONE



Started process "Place & Route".





Constraints file: spartan2_clk_wrapper.pcf

Loading device database for application Par from file
"spartan2_clk_wrapper_map.ncd".
   "spartan2_clk_wrapper" is an NCD, version 2.38, device xc2s50, package pq208,
speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            40 out of 140    28%
      Number of LOCed External IOBs    0 out of 40      0%

   Number of SLICEs                  187 out of 768    24%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:989959) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
......
.
Phase 5.8 (Checksum:9d598a) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file spartan2_clk_wrapper.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 1040 unrouted;       REAL time: 2 secs 

Phase 2: 1007 unrouted;       REAL time: 5 secs 

Phase 3: 223 unrouted;       REAL time: 6 secs 

Phase 4: 223 unrouted; (0)      REAL time: 6 secs 

Phase 5: 223 unrouted; (0)      REAL time: 6 secs 

Phase 6: 223 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   28   |  0.080     |  0.465      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_8917ce66 = PERIOD TIMEGRP "clk_891 | 100.000ns  | 7.640ns    | 14   
  7ce66"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  57 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file spartan2_clk_wrapper.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Wed Aug 03 10:35:52 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module spartan2_clk_wrapper . . .
PAR command line: par -w -intstyle ise -ol std -t 1 spartan2_clk_wrapper_map.ncd spartan2_clk_wrapper.ncd spartan2_clk_wrapper.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "choosen_out.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_div.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "seg7_driver.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library
work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <spartan2_addsub1> (Architecture <behavior>) compiled.
Entity <spartan2_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <spartan2> (Architecture <structural>) compiled.
Entity <spartan2_clock_driver> (Architecture <structural>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.


Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 15.61 / 16.94 s | Elapsed : 15.00 / 17.00 s
 
--> 

Total memory usage is 71352 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_schematic.prj> succeeded.
 
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/top_schematic.vhf in Library work.
Entity <top_schematic> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_schematic> (Architecture <BEHAVIORAL>).
WARNING:Xst:766 - D:/isnique/work/xspartan2/top_schematic.vhf line 71: Generating a Black Box for component <clk_div>.
Entity <top_schematic> analyzed. Unit <top_schematic> generated.

Analyzing module <choosen_out>.
ERROR:Xst:1932 - Port <choice_yy> in instance of module <choosen_out> is missing in the module definition.
--> 

Total memory usage is 48776 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/top_schematic.vhf in Library work.
Architecture behavioral of Entity top_schematic is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_schematic> (Architecture <behavioral>).
WARNING:Xst:766 - D:/isnique/work/xspartan2/top_schematic.vhf line 71: Generating a Black Box for component <clk_div>.
Entity <top_schematic> analyzed. Unit <top_schematic> generated.

Analyzing module <choosen_out>.
ERROR:Xst:1932 - Port <choice_yy> in instance of module <choosen_out> is missing in the module definition.
--> 

Total memory usage is 48776 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/top_schematic.vhf in Library work.
Architecture behavioral of Entity top_schematic is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_schematic> (Architecture <behavioral>).
WARNING:Xst:766 - D:/isnique/work/xspartan2/top_schematic.vhf line 71: Generating a Black Box for component <clk_div>.
Entity <top_schematic> analyzed. Unit <top_schematic> generated.

Analyzing module <choosen_out>.
ERROR:Xst:1932 - Port <choice_yy> in instance of module <choosen_out> is missing in the module definition.
--> 

Total memory usage is 48776 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "choosen_out.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_schematic.prj> succeeded.
 
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/top_schematic.vhf in Library work.
Architecture behavioral of Entity top_schematic is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_schematic> (Architecture <behavioral>).
Entity <top_schematic> analyzed. Unit <top_schematic> generated.

Analyzing module <choosen_out>.
ERROR:Xst:1932 - Port <choice_yy> in instance of module <choosen_out> is missing in the module definition.
--> 

Total memory usage is 48776 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_schematic.prj> succeeded.
 
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/top_schematic.vhf in Library work.
ERROR:HDLParsers:856 - D:/isnique/work/xspartan2/top_schematic.vhf Line 89. No default value for unconnected port <ce>.
ERROR:HDLParsers:856 - D:/isnique/work/xspartan2/top_schematic.vhf Line 89. No default value for unconnected port <clk>.
ERROR:HDLParsers:856 - D:/isnique/work/xspartan2/top_schematic.vhf Line 89. No default value for unconnected port <in_x_0>.
--> 

Total memory usage is 47752 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_schematic.prj> succeeded.
 
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/top_schematic.vhf in Library work.
ERROR:HDLParsers:856 - D:/isnique/work/xspartan2/top_schematic.vhf Line 89. No default value for unconnected port <ce>.
ERROR:HDLParsers:856 - D:/isnique/work/xspartan2/top_schematic.vhf Line 89. No default value for unconnected port <clk>.
ERROR:HDLParsers:856 - D:/isnique/work/xspartan2/top_schematic.vhf Line 89. No default value for unconnected port <in_x_0>.
--> 

Total memory usage is 47752 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
No errors in compilation
Analysis of file <choosen_out.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <choosen_out> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.94 / 4.25 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "choosen_out.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <clk_div.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 18-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_div> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.34 / 3.63 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <seg7_driver.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.52 / 3.80 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "choosen_out.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_schematic.prj> succeeded.
 
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/top_schematic.vhf in Library work.
ERROR:HDLParsers:856 - D:/isnique/work/xspartan2/top_schematic.vhf Line 89. No default value for unconnected port <ce>.
ERROR:HDLParsers:856 - D:/isnique/work/xspartan2/top_schematic.vhf Line 89. No default value for unconnected port <clk>.
ERROR:HDLParsers:856 - D:/isnique/work/xspartan2/top_schematic.vhf Line 89. No default value for unconnected port <in_x_0>.
--> 

Total memory usage is 47752 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <clk_div.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 18-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_div> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.47 / 3.75 s | Elapsed : 2.00 / 3.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <seg7_driver.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.58 / 3.89 s | Elapsed : 2.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "choosen_out.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------

Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Instantiation Template".

Compiling source file "choosen_out.v"
tdtfi(verilog) completed successfully.
Completed process "View VHDL Instantiation Template".




Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
No errors in compilation
Analysis of file <choosen_out.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <choosen_out> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.31 / 3.59 s | Elapsed : 2.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
No errors in compilation
Analysis of file <choosen_out.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <choosen_out> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.33 / 3.64 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "choosen_out.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
No errors in compilation
Analysis of file <choosen_out.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <choosen_out> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.22 / 3.52 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
No errors in compilation
Analysis of file <choosen_out.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <choosen_out> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.39 / 3.83 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
No errors in compilation
Analysis of file <choosen_out.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <choosen_out> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.75 / 4.58 s | Elapsed : 3.00 / 5.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
No errors in compilation
Analysis of file <choosen_out.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <choosen_out> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.39 / 3.72 s | Elapsed : 2.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
No errors in compilation
Analysis of file <choosen_out.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <choosen_out> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.34 / 3.64 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <clk_div.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 18-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_div> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.42 / 3.70 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <seg7_driver.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.61 / 4.31 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.


Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 14.86 / 16.16 s | Elapsed : 15.00 / 16.00 s
 
--> 

Total memory usage is 71352 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Compile HDL Simulation Libraries".

Process "Compile HDL Simulation Libraries" did not complete.



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Compile HDL Simulation Libraries".

Process "Compile HDL Simulation Libraries" did not complete.



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Compile HDL Simulation Libraries".

Process "Compile HDL Simulation Libraries" did not complete.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
No errors in compilation
Analysis of file <choosen_out.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <choosen_out> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.45 / 3.89 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Instantiation Template".

Compiling source file "clk_div.v"
tdtfi(verilog) completed successfully.
Completed process "View VHDL Instantiation Template".




Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <clk_div.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 18-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_div> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.63 / 3.97 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
No errors in compilation
Analysis of file <choosen_out.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <choosen_out> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.67 / 4.08 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <clk_div.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 18-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_div> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.56 / 3.94 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <seg7_driver.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 2.73 / 4.11 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 53944 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/top_spartan2.vhf in Library work.
Entity <top_spartan2> (Architecture <BEHAVIORAL>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_spartan2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan2> (Architecture <BEHAVIORAL>).
Entity <top_spartan2> analyzed. Unit <top_spartan2> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan2>.
    Related source file is D:/isnique/work/xspartan2/top_spartan2.vhf.
Unit <top_spartan2> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block top_spartan2, actual ratio is 36.
FlipFlop XLXI_2_anode0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode2 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     280  out of    768    36%  
 Number of Slice Flip Flops:            69  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_4_clock_cnt_17:Q              | NONE                   | 11    |
XLXN_14(XLXI_3_choice_yy1:O)       | NONE(*)(XLXI_1_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u214)| 40    |
clk                                | BUFGP                  | 18    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.365ns
   Maximum combinational path delay: 35.901ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xspartan2/_ngo -i -p
xc2s50-pq208-6 top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "D:/isnique/work/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fec985a9ef.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 39728 kilobytes

Writing NGD file "top_spartan2.ngd" ...

Writing NGDBUILD log file "top_spartan2.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/top_spartan2.vhf in Library work.
Entity <top_spartan2> (Architecture <behavioral>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_spartan2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan2> (Architecture <behavioral>).
Entity <top_spartan2> analyzed. Unit <top_spartan2> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan2>.
    Related source file is D:/isnique/work/xspartan2/top_spartan2.vhf.
Unit <top_spartan2> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block top_spartan2, actual ratio is 36.
FlipFlop XLXI_2_anode0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode2 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     280  out of    768    36%  
 Number of Slice Flip Flops:            69  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_4_clock_cnt_17:Q              | NONE                   | 11    |
XLXN_14(XLXI_3_choice_yy1:O)       | NONE(*)(XLXI_1_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u214)| 40    |
clk                                | BUFGP                  | 18    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.365ns
   Maximum combinational path delay: 35.901ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xspartan2/_ngo -uc
top_spartan2.ucf -p xc2s50-pq208-6 top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "D:/isnique/work/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fec985a9ef.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 39728 kilobytes

Writing NGD file "top_spartan2.ngd" ...

Writing NGDBUILD log file "top_spartan2.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file D:/isnique/work/xspartan2/top_spartan2.vhf in Library work.
Architecture behavioral of Entity top_spartan2 is up to date.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_spartan2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan2> (Architecture <behavioral>).
Entity <top_spartan2> analyzed. Unit <top_spartan2> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is D:/isnique/work/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan2>.
    Related source file is D:/isnique/work/xspartan2/top_spartan2.vhf.
Unit <top_spartan2> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block top_spartan2, actual ratio is 36.
FlipFlop XLXI_2_anode0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode2 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     280  out of    768    36%  
 Number of Slice Flip Flops:            69  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_4_clock_cnt_17:Q              | NONE                   | 11    |
XLXN_14(XLXI_3_choice_yy1:O)       | NONE(*)(XLXI_1_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u215)| 40    |
clk                                | BUFGP                  | 18    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.365ns
   Maximum combinational path delay: 35.901ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xspartan2/_ngo -i -p
xc2s50-pq208-6 top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "D:/isnique/work/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fec985a9ef.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 39728 kilobytes

Writing NGD file "top_spartan2.ngd" ...

Writing NGDBUILD log file "top_spartan2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        48 out of  1,536    3%
  Number of 4 input LUTs:           384 out of  1,536   25%
Logic Distribution:
    Number of occupied Slices:                         209 out of    768   27%
    Number of Slices containing only related logic:    209 out of    209  100%
    Number of Slices containing unrelated logic:         0 out of    209    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          404 out of  1,536   26%
      Number used as logic:                       384
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              21
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  4,191
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  63 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan2_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan2_map.ncd top_spartan2.ngd top_spartan2.pcf
Mapping Module top_spartan2: DONE



Started process "Place & Route".





Constraints file: top_spartan2.pcf

Loading device database for application Par from file "top_spartan2_map.ncd".
   "top_spartan2" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs    0 out of 30      0%

   Number of SLICEs                  209 out of 768    27%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:9899ce) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
........
.
Phase 5.8 (Checksum:9d66b9) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file top_spartan2.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 1160 unrouted;       REAL time: 3 secs 

Phase 2: 1110 unrouted;       REAL time: 6 secs 

Phase 3: 258 unrouted;       REAL time: 6 secs 

Phase 4: 258 unrouted; (0)      REAL time: 7 secs 

Phase 5: 258 unrouted; (0)      REAL time: 7 secs 

Phase 6: 258 unrouted; (0)      REAL time: 7 secs 

Phase 7: 0 unrouted; (0)      REAL time: 7 secs 

Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |    9   |  0.000     |  0.465      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_14          |   Local  |   28   |  1.982     |  4.723      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt(17)    |   Local  |   10   |  1.803     |  4.674      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_8917ce66 = PERIOD TIMEGRP "clk_891 | 100.000ns  | 4.859ns    | 9    
  7ce66"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  58 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file top_spartan2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 07 13:33:16 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan2_map.ncd top_spartan2.ncd top_spartan2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xspartan2/_ngo -uc
top_spartan2.ucf -p xc2s50-pq208-6 top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "D:/isnique/work/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fec985a9ef.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 41776 kilobytes

Writing NGD file "top_spartan2.ngd" ...

Writing NGDBUILD log file "top_spartan2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        48 out of  1,536    3%
  Number of 4 input LUTs:           384 out of  1,536   25%
Logic Distribution:
    Number of occupied Slices:                         209 out of    768   27%
    Number of Slices containing only related logic:    209 out of    209  100%
    Number of Slices containing unrelated logic:         0 out of    209    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          404 out of  1,536   26%
      Number used as logic:                       384
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              21
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  4,191
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  63 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan2_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan2_map.ncd top_spartan2.ngd top_spartan2.pcf
Mapping Module top_spartan2: DONE



Started process "Place & Route".





Constraints file: top_spartan2.pcf

Loading device database for application Par from file "top_spartan2_map.ncd".
   "top_spartan2" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   30 out of 30    100%

   Number of SLICEs                  209 out of 768    27%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:9899ce) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
...
.
Phase 5.8 (Checksum:9d5ffc) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_spartan2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 1160 unrouted;       REAL time: 2 secs 

Phase 2: 1114 unrouted;       REAL time: 5 secs 

Phase 3: 283 unrouted;       REAL time: 6 secs 

Phase 4: 283 unrouted; (0)      REAL time: 6 secs 

Phase 5: 283 unrouted; (0)      REAL time: 6 secs 

Phase 6: 283 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |    9   |  0.000     |  0.450      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_14          |   Local  |   28   |  0.491     |  4.638      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt(17)    |   Local  |   10   |  0.802     |  3.092      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_8917ce66 = PERIOD TIMEGRP "clk_891 | 100.000ns  | 4.859ns    | 9    
  7ce66"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  58 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file top_spartan2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 07 13:43:57 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan2_map.ncd top_spartan2.ncd top_spartan2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xspartan2/_ngo -uc
top_spartan2.ucf -p xc2s50-pq208-6 top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "D:/isnique/work/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fec985a9ef.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 41776 kilobytes

Writing NGD file "top_spartan2.ngd" ...

Writing NGDBUILD log file "top_spartan2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        48 out of  1,536    3%
  Number of 4 input LUTs:           384 out of  1,536   25%
Logic Distribution:
    Number of occupied Slices:                         209 out of    768   27%
    Number of Slices containing only related logic:    209 out of    209  100%
    Number of Slices containing unrelated logic:         0 out of    209    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          404 out of  1,536   26%
      Number used as logic:                       384
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              21
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  4,191
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan2_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan2_map.ncd top_spartan2.ngd top_spartan2.pcf
Mapping Module top_spartan2: DONE



Started process "Place & Route".





Constraints file: top_spartan2.pcf

Loading device database for application Par from file "top_spartan2_map.ncd".
   "top_spartan2" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   29 out of 30     96%

   Number of SLICEs                  209 out of 768    27%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:9899ce) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
....
.
Phase 5.8 (Checksum:9d8edc) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file top_spartan2.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 1160 unrouted;       REAL time: 3 secs 

Phase 2: 1125 unrouted;       REAL time: 6 secs 

Phase 3: 262 unrouted;       REAL time: 7 secs 

Phase 4: 262 unrouted; (0)      REAL time: 7 secs 

Phase 5: 262 unrouted; (0)      REAL time: 7 secs 

Phase 6: 262 unrouted; (0)      REAL time: 7 secs 

Phase 7: 0 unrouted; (0)      REAL time: 7 secs 

Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |    9   |  0.000     |  0.449      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_14          |   Local  |   28   |  2.598     |  3.429      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt(17)    |   Local  |   10   |  0.631     |  2.904      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_8917ce66 = PERIOD TIMEGRP "clk_891 | 100.000ns  | 4.859ns    | 9    
  7ce66"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  58 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file top_spartan2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 07 14:40:11 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan2_map.ncd top_spartan2.ncd top_spartan2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xspartan2/_ngo -uc
top_spartan2.ucf -p xc2s50-pq208-6 top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "D:/isnique/work/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"d:\isnique\work\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fec985a9ef.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 41776 kilobytes

Writing NGD file "top_spartan2.ngd" ...

Writing NGDBUILD log file "top_spartan2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        48 out of  1,536    3%
  Number of 4 input LUTs:           384 out of  1,536   25%
Logic Distribution:
    Number of occupied Slices:                         209 out of    768   27%
    Number of Slices containing only related logic:    209 out of    209  100%
    Number of Slices containing unrelated logic:         0 out of    209    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          404 out of  1,536   26%
      Number used as logic:                       384
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              21
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  4,191
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  63 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan2_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan2_map.ncd top_spartan2.ngd top_spartan2.pcf
Mapping Module top_spartan2: DONE



Started process "Place & Route".





Constraints file: top_spartan2.pcf

Loading device database for application Par from file "top_spartan2_map.ncd".
   "top_spartan2" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   30 out of 30    100%

   Number of SLICEs                  209 out of 768    27%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:9899ce) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
...
.
Phase 5.8 (Checksum:9d5ffc) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file top_spartan2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 1160 unrouted;       REAL time: 2 secs 

Phase 2: 1114 unrouted;       REAL time: 6 secs 

Phase 3: 269 unrouted;       REAL time: 6 secs 

Phase 4: 269 unrouted; (0)      REAL time: 6 secs 

Phase 5: 269 unrouted; (0)      REAL time: 6 secs 

Phase 6: 269 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 7 secs 

Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |    9   |  0.000     |  0.450      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_14          |   Local  |   28   |  0.491     |  4.638      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt(17)    |   Local  |   10   |  0.802     |  3.092      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_8917ce66 = PERIOD TIMEGRP "clk_891 | 100.000ns  | 4.859ns    | 9    
  7ce66"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  58 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file top_spartan2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 07 14:50:05 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan2_map.ncd top_spartan2.ncd top_spartan2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Instantiation Template".

WARNING:HDLParsers:3215 - Unit work/CONV_PKG is now defined in a different file:
   was D:/isnique/work/xspartan2/spartan2_pkgs.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd
WARNING:HDLParsers:3215 - Unit work/CONV_PKG is now defined in a different file:
   was D:/isnique/work/xspartan2/spartan2_pkgs.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd
WARNING:HDLParsers:3215 - Unit work/CLOCK_PKG is now defined in a different
   file: was D:/isnique/work/xspartan2/spartan2_pkgs.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd
WARNING:HDLParsers:3215 - Unit work/SRL17E is now defined in a different file:
   was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SRL17E/STRUCTURAL is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG is now defined in a different
   file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG/STRUCTURAL is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_REG is now defined in a different
   file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_REG/BEHAV is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SINGLE_REG_W_INIT is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SINGLE_REG_W_INIT/STRUCTURAL is now defined
   in a different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_W_INIT is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_W_INIT/STRUCTURAL is now defined
   in a different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLKPROBE is now defined in a different
   file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLKPROBE/BEHAVIOR is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKDRIVER is now defined in a different
   file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKDRIVER/BEHAVIOR is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKGENERATOR is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKGENERATOR/STRUCTURAL is now defined
   in a different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSL2SLV is now defined in a different file:
   was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSL2SLV/BEHAVIOR is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSLV2SL is now defined in a different file:
   was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSLV2SL/BEHAVIOR is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_ADDSUB is now defined in a different
   file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_ADDSUB/BEHAVIOR is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SPARTAN2_ADDSUB1 is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SPARTAN2_ADDSUB1/BEHAVIOR is now defined in
   a different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SPARTAN2_KD is now defined in a different
   file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SPARTAN2_KD/BEHAVIOR is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLDELAY is now defined in a different file:
   was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLDELAY/BEHAVIOR is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SPARTAN2 is now defined in a different file:
   was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SPARTAN2/STRUCTURAL is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SPARTAN2_CLOCK_DRIVER is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SPARTAN2_CLOCK_DRIVER/STRUCTURAL is now
   defined in a different file: was
   D:/isnique/work/xspartan2/spartan2_files.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd
WARNING:HDLParsers:3215 - Unit work/SPARTAN2_CLK_WRAPPER is now defined in a
   different file: was D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd, now
   is c:/matlab6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd
WARNING:HDLParsers:3215 - Unit work/SPARTAN2_CLK_WRAPPER/STRUCTURAL is now
   defined in a different file: was
   D:/isnique/work/xspartan2/spartan2_clk_wrapper.vhd, now is
   c:/matlab6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd
Compiling vhdl file c:/matlab6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in
Library work.
Compiling vhdl file c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd in
Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <spartan2_addsub1> (Architecture <behavior>) compiled.
Entity <spartan2_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <spartan2> (Architecture <structural>) compiled.
Entity <spartan2_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file c:/matlab6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd
in Library work.
Entity <spartan2_clk_wrapper> (Architecture <structural>) compiled.
tdtfi(vhdl) completed successfully.
Completed process "View VHDL Instantiation Template".




Project Navigator Auto-Make Log File
-------------------------------------

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deleting top_spartan2.hex
deleting top_spartan2.svf
deleting top_spartan2.stapl
deleting impact.cmd
deleting _impact.log
deleting _impact.cmd
deleting top_spartan2.prm
deleting top_spartan2.isc
deleting top_spartan2.svf
deleting xilinx.sys
deleting top_spartan2.mcs
deleting top_spartan2.exo
deleting top_spartan2.hex
deleting top_spartan2.tek
deleting top_spartan2.dst
deleting top_spartan2.dst_compressed
deleting top_spartan2.mpm
deleting _impact.cmd
deleting _impact.log
deleting top_spartan2.prm
deleting top_spartan2.isc
deleting top_spartan2.svf
deleting xilinx.sys
deleting top_spartan2.mcs
deleting top_spartan2.exo
deleting top_spartan2.hex
deleting top_spartan2.tek
deleting top_spartan2.dst
deleting top_spartan2.dst_compressed
deleting top_spartan2.mpm
deleting _impact.cmd
deleting _impact.log
deleting __projnav/tb.rsp
deleting spartan2_clk_wrapper.vhi
deleting __projnav/vhd2vhi.err
deleting __projnav/spartan2_clk_wrapper.gfl
Finished cleaning up project


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Compile HDL Simulation Libraries".

Process "Compile HDL Simulation Libraries" did not complete.



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Compile HDL Simulation Libraries".

Process "Compile HDL Simulation Libraries" did not complete.



Project Navigator Auto-Make Log File
-------------------------------------


Started process "HDL Converter".


ERROR: No input file specified for the "HDL Converter" process.
Please select an input file (ABEL or AHDL) from the property menu.
(Right click on the "HDL Converter" process name and select 'Properties')
Process "HDL Converter" did not complete due to error(s) reported by internal script.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file c:/matlab6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in
Library work.
Compiling vhdl file c:/matlab6p5/work/isniamy/xspartan2/spartan2_files.vhd in
Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <spartan2_addsub1> (Architecture <behavior>) compiled.
Entity <spartan2_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <spartan2> (Architecture <structural>) compiled.
Entity <spartan2_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file c:/matlab6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd
in Library work.
Entity <spartan2_clk_wrapper> (Architecture <structural>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Completed process "Check Syntax".


