source {C:/xilinx_62i/data/projnav/scripts/VsimStopServer.tcl}
initIPC 1200
-- Auto Generated by Project Navigator to simulate
-- HDL Bencher Annotated Test Bench
--
vlib work
onbreak {resume}
onerror {quit -code 99 -force}
onElabError {resume}
vcom -93 -explicit  spartan2_pkgs.vhd
vcom -93 -explicit  spartan2_files.vhd
vcom -93 -explicit  spartan2_clk_wrapper.vhd
vlog  seg7_driver.v
vlog  choosen_out.v
vlog  clk_div.v
vcom -93 -explicit  top_spartan2.vhf
vcom -93 -explicit  top_spartan2_tb.ant
vlog  "C:/xilinx_62i/verilog/src/glbl.v"
vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver  -lib work top_spartan2_tb glbl
run -all
quit -force
