Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xtambah/tambah_pkgs.vhd in Library work.
Compiling vhdl file C:/MATLAB6p5/work/xtambah/tambah_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <tambah_addsub> (Architecture <behavior>) compiled.
Entity <tambah> (Architecture <structural>) compiled.
Entity <tambah_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file C:/MATLAB6p5/work/xtambah/tambah_clk_wrapper.vhd in Library work.
Entity <tambah_clk_wrapper> (Architecture <structural>) compiled.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tambah_tbw.ado 
listening on address 127.0.0.1 port 1200
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity tambah_addsub
# -- Compiling architecture behavior of tambah_addsub
# -- Loading entity synth_addsub
# WARNING[1]: tambah_files.vhd(1448): No default binding for component: "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53". (No entity named "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# -- Compiling entity tambah
# -- Compiling architecture structural of tambah
# -- Loading entity tambah_addsub
# -- Loading entity xlsl2slv
# -- Compiling entity tambah_clock_driver
# -- Compiling architecture structural of tambah_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity tambah_clk_wrapper
# -- Compiling architecture structural of tambah_clk_wrapper
# -- Loading entity tambah_clock_driver
# -- Loading entity tambah
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tambah_tbw
# -- Compiling architecture testbench_arch of tambah_tbw
# -- Loading entity tambah_clk_wrapper
# -- Compiling configuration tambah_clk_wrapper_cfg
# -- Loading entity tambah_tbw
# -- Loading architecture testbench_arch of tambah_tbw
# vsim -lib work -t 1ps tambah_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tambah_tbw(testbench_arch)
# Loading work.tambah_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.tambah_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.tambah(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.tambah_addsub(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 1357 statements or 3 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 810 ns  Iteration: 0  Process: /tambah_tbw/line__84 File: tambah_tbw.ant
# Break at tambah_tbw.ant line 132
# Stopped at tambah_tbw.ant line 132 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tambah_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity tambah_addsub
# -- Compiling architecture behavior of tambah_addsub
# -- Loading entity synth_addsub
# WARNING[1]: tambah_files.vhd(1448): No default binding for component: "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53". (No entity named "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# -- Compiling entity tambah
# -- Compiling architecture structural of tambah
# -- Loading entity tambah_addsub
# -- Loading entity xlsl2slv
# -- Compiling entity tambah_clock_driver
# -- Compiling architecture structural of tambah_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity tambah_clk_wrapper
# -- Compiling architecture structural of tambah_clk_wrapper
# -- Loading entity tambah_clock_driver
# -- Loading entity tambah
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tambah_tbw
# -- Compiling architecture testbench_arch of tambah_tbw
# -- Loading entity tambah_clk_wrapper
# -- Compiling configuration tambah_clk_wrapper_cfg
# -- Loading entity tambah_tbw
# -- Loading architecture testbench_arch of tambah_tbw
# vsim -lib work -t 1ps tambah_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tambah_tbw(testbench_arch)
# Loading work.tambah_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.tambah_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.tambah(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.tambah_addsub(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 1353 statements or 3 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 810 ns  Iteration: 0  Process: /tambah_tbw/line__84 File: tambah_tbw.ant
# Break at tambah_tbw.ant line 128
# Stopped at tambah_tbw.ant line 128 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tambah_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity tambah_addsub
# -- Compiling architecture behavior of tambah_addsub
# -- Loading entity synth_addsub
# WARNING[1]: tambah_files.vhd(1448): No default binding for component: "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53". (No entity named "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# -- Compiling entity tambah
# -- Compiling architecture structural of tambah
# -- Loading entity tambah_addsub
# -- Loading entity xlsl2slv
# -- Compiling entity tambah_clock_driver
# -- Compiling architecture structural of tambah_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity tambah_clk_wrapper
# -- Compiling architecture structural of tambah_clk_wrapper
# -- Loading entity tambah_clock_driver
# -- Loading entity tambah
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tambah_tbw
# -- Compiling architecture testbench_arch of tambah_tbw
# -- Loading entity tambah_clk_wrapper
# -- Compiling configuration tambah_clk_wrapper_cfg
# -- Loading entity tambah_tbw
# -- Loading architecture testbench_arch of tambah_tbw
# vsim -lib work -t 1ps tambah_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tambah_tbw(testbench_arch)
# Loading work.tambah_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.tambah_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.tambah(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.tambah_addsub(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 1353 statements or 3 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 810 ns  Iteration: 0  Process: /tambah_tbw/line__84 File: tambah_tbw.ant
# Break at tambah_tbw.ant line 128
# Stopped at tambah_tbw.ant line 128 


Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/TAMBAH_CLK_WRAPPER is now defined in a different file: was c:/matlab6p5/work/xtambah/tambah_clk_wrapper.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_clk_wrapper.vhd
WARNING:HDLParsers:3215 - Unit work/TAMBAH_CLK_WRAPPER/STRUCTURAL is now defined in a different file: was c:/matlab6p5/work/xtambah/tambah_clk_wrapper.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_clk_wrapper.vhd
WARNING:HDLParsers:3215 - Unit work/SRL17E is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SRL17E/STRUCTURAL is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG/STRUCTURAL is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_REG is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_REG/BEHAV is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SINGLE_REG_W_INIT is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SINGLE_REG_W_INIT/STRUCTURAL is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_W_INIT is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_W_INIT/STRUCTURAL is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLKPROBE is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLKPROBE/BEHAVIOR is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKDRIVER is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKDRIVER/BEHAVIOR is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKGENERATOR is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKGENERATOR/STRUCTURAL is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSL2SLV is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSL2SLV/BEHAVIOR is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSLV2SL is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSLV2SL/BEHAVIOR is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_ADDSUB is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_ADDSUB/BEHAVIOR is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/TAMBAH_ADDSUB is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/TAMBAH_ADDSUB/BEHAVIOR is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/TAMBAH is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/TAMBAH/STRUCTURAL is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/TAMBAH_CLOCK_DRIVER is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/TAMBAH_CLOCK_DRIVER/STRUCTURAL is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_files.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd
WARNING:HDLParsers:3215 - Unit work/CONV_PKG is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_pkgs.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_pkgs.vhd
WARNING:HDLParsers:3215 - Unit work/CONV_PKG is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_pkgs.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_pkgs.vhd
WARNING:HDLParsers:3215 - Unit work/CLOCK_PKG is now defined in a different file: was C:/MATLAB6p5/work/xtambah/tambah_pkgs.vhd, now is C:/MATLAB6p5/work/isniamy/xtambah/tambah_pkgs.vhd
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xtambah/tambah_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity tambah_addsub is up to date.
Architecture structural of Entity tambah is up to date.
Architecture structural of Entity tambah_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xtambah/tambah_clk_wrapper.vhd in Library work.
Architecture structural of Entity tambah_clk_wrapper is up to date.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do plus1_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity tambah_addsub
# -- Compiling architecture behavior of tambah_addsub
# -- Loading entity synth_addsub
# WARNING[1]: tambah_files.vhd(1448): No default binding for component: "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53". (No entity named "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# -- Compiling entity tambah
# -- Compiling architecture structural of tambah
# -- Loading entity tambah_addsub
# -- Loading entity xlsl2slv
# -- Compiling entity tambah_clock_driver
# -- Compiling architecture structural of tambah_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity tambah_clk_wrapper
# -- Compiling architecture structural of tambah_clk_wrapper
# -- Loading entity tambah_clock_driver
# -- Loading entity tambah
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity plus1_tbw
# -- Compiling architecture testbench_arch of plus1_tbw
# -- Loading entity tambah_clk_wrapper
# -- Compiling configuration tambah_clk_wrapper_cfg
# -- Loading entity plus1_tbw
# -- Loading architecture testbench_arch of plus1_tbw
# vsim -lib work -t 1ps plus1_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.plus1_tbw(testbench_arch)
# Loading work.tambah_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.tambah_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.tambah(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.tambah_addsub(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 1353 statements or 3 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 81 ms  Iteration: 0  Process: /plus1_tbw/line__84 File: plus1_tbw.ant
# Break at plus1_tbw.ant line 128
# Stopped at plus1_tbw.ant line 128 


Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xtambah/tambah_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity tambah_addsub is up to date.
Architecture structural of Entity tambah is up to date.
Architecture structural of Entity tambah_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xtambah/tambah_clk_wrapper.vhd in Library work.
Architecture structural of Entity tambah_clk_wrapper is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <tambah_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xtambah/tambah_clk_wrapper.vhd line 110: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <tambah_clk_wrapper> analyzed. Unit <tambah_clk_wrapper> generated.

Analyzing Entity <tambah_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd line 1796: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <tambah_clock_driver> analyzed. Unit <tambah_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <tambah> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd line 1642: Unconnected input port 'c_in' of component 'tambah_addsub' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd line 1642: Unconnected output port 'c_out' of component 'tambah_addsub'.
Entity <tambah> analyzed. Unit <tambah> generated.

Analyzing generic Entity <tambah_addsub> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53"
	a_width = 8
	a_bin_pt = 4
	a_arith = 1
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 8
	b_bin_pt = 4
	b_arith = 1
	s_width = 16
	s_bin_pt = 4
	s_arith = 1
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 9
	full_s_arith = 1
	mode = 1
	extra_registers = 0
	latency = 1
	quantization = 1
	overflow = 1
	c_a_width = 9
	c_b_width = 9
	c_a_type = 1
	c_b_type = 1
	c_add_mode = 0
	c_has_s = 0
	c_has_q = 1
	c_has_sclr = 1
	c_has_ce = 1
	c_latency = 1
	c_output_width = 9
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <tambah_addsub> analyzed. Unit <tambah_addsub> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


Reading constraint file .\tambah_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <tambah_addsub>.
    Related source file is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
Unit <tambah_addsub> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <tambah>.
    Related source file is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd.
Unit <tambah> synthesized.


Synthesizing Unit <tambah_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xtambah/tambah_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <tambah_clock_driver> synthesized.


Synthesizing Unit <tambah_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xtambah/tambah_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <tambah_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <tambah_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53.edn" "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53.ngo"...
Loading core <adder_subtracter_spartan2_6_0_565e6fc4f8af6f53> for timing and area information for instance <core_instance0>.

Optimizing unit <tambah_clk_wrapper> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\tambah_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block tambah_clk_wrapper, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                       5  out of    768     0%  
 Number of Slice Flip Flops:             9  out of   1536     0%  
 Number of 4 input LUTs:                 9  out of   1536     0%  
 Number of bonded IOBs:                 32  out of    144    22%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: 4.442ns
   Maximum output required time after clock: 6.788ns
   Maximum combinational path delay: No path found
WARNING:Xst:1415 - No path found for this constraint.

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\matlab6p5\work\isniamy\xtambah/_ngo
-i -p xc2s50-pq208-6 tambah_clk_wrapper.ngc tambah_clk_wrapper.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xtambah/tambah_clk_wrapper.ngc" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_565e6fc4f8af6f53.edn"
"c:\matlab6p5\work\isniamy\xtambah\_ngo\adder_subtracter_spartan2_6_0_565e6fc4f8
af6f53.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/isniamy/xtambah/_ngo/adder_subtracter_spartan2_6_0_565e6fc4f8
af6f53.ngo"...
Loading design module
"c:\matlab6p5\work\isniamy\xtambah\_ngo\adder_subtracter_spartan2_6_0_565e6fc4f8
af6f53.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 37820 kilobytes

Writing NGD file "tambah_clk_wrapper.ngd" ...

Writing NGDBUILD log file "tambah_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         9 out of  1,536    1%
  Number of 4 input LUTs:             8 out of  1,536    1%
Logic Distribution:
    Number of occupied Slices:                           5 out of    768    1%
    Number of Slices containing only related logic:      5 out of      5  100%
    Number of Slices containing unrelated logic:         0 out of      5    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         8 out of  1,536    1%
   Number of bonded IOBs:            32 out of    140   22%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            1
Total equivalent gate count for design:  171
Additional JTAG gate count for IOBs:  1,584
Peak Memory Usage:  57 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "tambah_clk_wrapper_map.mrp" for details.
Completed process "Map".

Mapping Module tambah_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o tambah_clk_wrapper_map.ncd tambah_clk_wrapper.ngd tambah_clk_wrapper.pcf
Mapping Module tambah_clk_wrapper: DONE



Started process "Place & Route".





Constraints file: tambah_clk_wrapper.pcf

Loading device database for application Par from file
"tambah_clk_wrapper_map.ncd".
   "tambah_clk_wrapper" is an NCD, version 2.38, device xc2s50, package pq208,
speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            32 out of 140    22%
      Number of LOCed External IOBs    0 out of 32      0%

   Number of SLICEs                    5 out of 768     1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:98970b) REAL time: 3 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.8
.
Phase 5.8 (Checksum:998b6b) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file tambah_clk_wrapper.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 35 unrouted;       REAL time: 3 secs 

Phase 2: 30 unrouted;       REAL time: 3 secs 

Phase 3: 0 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted; (0)      REAL time: 3 secs 

Phase 5: 0 unrouted; (0)      REAL time: 3 secs 

Phase 6: 0 unrouted; (0)      REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |    5   |  0.000     |  0.463      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_4f9a0896 = PERIOD TIMEGRP "clk_4f9 | N/A        | N/A        | N/A  
  a0896"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  48 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file tambah_clk_wrapper.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun May 15 12:13:43 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module tambah_clk_wrapper . . .
PAR command line: par -w -intstyle ise -ol std -t 1 tambah_clk_wrapper_map.ncd tambah_clk_wrapper.ncd tambah_clk_wrapper.pcf
PAR completed successfully


