
SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = false
CSET latency = 0
CSET operation = add
CSET output_options = non_registered
CSET output_width = 47
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 47
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 47
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_47d1c1f0a7991da9
GENERATE

SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET asynchronous_clear = false
CSET clk_cycles_per_input = 1
CSET clock_enable = false
CSET create_rpm = true
CSET memory_type = Distributed_Memory
CSET multiplier_type = Parallel
CSET nd = false
CSET output_hold_register = false
CSET output_options = Non_Registered
CSET output_width = 33
CSET pipelined = Minimum
CSET port_a_data = Signed
CSET port_a_width = 17
CSET port_b_constant = true
CSET port_b_constant_value = 3120
CSET port_b_data = Unsigned
CSET port_b_width = 12
CSET rdy = false
CSET register_input = false
CSET reloadable = false
CSET rfd = false
CSET style = Rectangular_Shape
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_fe654cf32dc31d3a
GENERATE
