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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/xilinx_62i/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml tambah_clk_wrapper
tambah_clk_wrapper.ncd -o tambah_clk_wrapper.twr tambah_clk_wrapper.pcf


Design file:              tambah_clk_wrapper.ncd
Physical constraint file: tambah_clk_wrapper.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.

================================================================================
Timing constraint: TS_clk_4f9a0896 = PERIOD TIMEGRP "clk_4f9a0896"  100 nS   HIGH 50.000000 % ;

 0 items analyzed, 0 timing errors detected.
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All constraints were met.


Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 0 paths, 0 nets, and 20 connections

Design statistics:
No global statistics to report.

Analysis completed Sun May 15 12:13:43 2005
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Peak Memory Usage: 40 MB
