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library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;

entity logic1 is
  port (
    gateway_in: in std_logic_vector(3 downto 0);
    gateway_in1: in std_logic_vector(3 downto 0);
    gateway_in2: in std_logic_vector(3 downto 0);
    gateway_in3: in std_logic_vector(3 downto 0);
    gateway_out: out std_logic_vector(3 downto 0);
    gateway_out1: out std_logic_vector(3 downto 0)
  );
end logic1;

architecture structural of logic1 is
  signal dout: std_logic_vector(3 downto 0);
  signal dout_x_0: std_logic_vector(3 downto 0);
  signal dout_x_1: std_logic_vector(3 downto 0);
  signal dout_x_10: std_logic_vector(0 downto 0);
  signal dout_x_2: std_logic_vector(3 downto 0);
  signal dout_x_3: std_logic_vector(3 downto 0);
  signal dout_x_4: std_logic_vector(3 downto 0);
  signal dout_x_5: std_logic_vector(0 downto 0);
  signal dout_x_6: std_logic_vector(0 downto 0);
  signal dout_x_7: std_logic_vector(0 downto 0);
  signal dout_x_8: std_logic_vector(0 downto 0);
  signal dout_x_9: std_logic_vector(0 downto 0);
  signal gateway_in1_x_0: std_logic_vector(3 downto 0);
  signal gateway_in2_x_0: std_logic_vector(3 downto 0);
  signal gateway_in3_x_0: std_logic_vector(3 downto 0);
  signal gateway_in_x_0: std_logic_vector(3 downto 0);

begin
  gateway_in_x_0 <= gateway_in;
  gateway_in1_x_0 <= gateway_in1;
  gateway_in2_x_0 <= gateway_in2;
  gateway_in3_x_0 <= gateway_in3;
  gateway_out <= dout_x_4;
  gateway_out1 <= dout_x_0;

  inverter: entity work.xlinv
    generic map (
      din_width => 4,
      din_arith => xlSigned,
      din_bin_pt => 0,
      dout_width => 4,
      dout_arith => xlSigned,
      dout_bin_pt => 0,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      latency => 0
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => gateway_in2_x_0,
      en => dout_x_5,
      dout => dout
    );
  inverter1: entity work.xlinv
    generic map (
      din_width => 4,
      din_arith => xlSigned,
      din_bin_pt => 0,
      dout_width => 4,
      dout_arith => xlSigned,
      dout_bin_pt => 0,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      latency => 0
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dout_x_1,
      en => dout_x_6,
      dout => dout_x_0
    );
  logical: entity work.xllogical3
    generic map (
      din0_width => 4,
      din0_arith => xlSigned,
      din0_bin_pt => 0,
      din1_width => 4,
      din1_arith => xlSigned,
      din1_bin_pt => 0,
      din2_width => 4,
      din2_arith => xlSigned,
      din2_bin_pt => 0,
      dout_width => 4,
      dout_arith => xlSigned,
      dout_bin_pt => 0,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      full_arith => xlSigned,
      full_bin_pt => 0,
      full_width => 4,
      gate_type => 1,
      latency => 0,
      num_inputs => 3
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din0 => gateway_in3_x_0,
      din1 => dout,
      din2 => dout_x_2,
      en => dout_x_10,
      dout => dout_x_1
    );
  logical1: entity work.xllogical2
    generic map (
      din0_width => 4,
      din0_arith => xlSigned,
      din0_bin_pt => 0,
      din1_width => 4,
      din1_arith => xlSigned,
      din1_bin_pt => 0,
      dout_width => 4,
      dout_arith => xlSigned,
      dout_bin_pt => 0,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      full_arith => xlSigned,
      full_bin_pt => 0,
      full_width => 4,
      gate_type => 2,
      latency => 0,
      num_inputs => 2
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din0 => gateway_in_x_0,
      din1 => gateway_in1_x_0,
      en => dout_x_7,
      dout => dout_x_2
    );
  logical2: entity work.xllogical2
    generic map (
      din0_width => 4,
      din0_arith => xlSigned,
      din0_bin_pt => 0,
      din1_width => 4,
      din1_arith => xlSigned,
      din1_bin_pt => 0,
      dout_width => 4,
      dout_arith => xlSigned,
      dout_bin_pt => 0,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      full_arith => xlSigned,
      full_bin_pt => 0,
      full_width => 4,
      gate_type => 1,
      latency => 0,
      num_inputs => 2
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din0 => gateway_in_x_0,
      din1 => gateway_in1_x_0,
      en => dout_x_8,
      dout => dout_x_3
    );
  logical3: entity work.xllogical2
    generic map (
      din0_width => 4,
      din0_arith => xlSigned,
      din0_bin_pt => 0,
      din1_width => 4,
      din1_arith => xlSigned,
      din1_bin_pt => 0,
      dout_width => 4,
      dout_arith => xlSigned,
      dout_bin_pt => 0,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      full_arith => xlSigned,
      full_bin_pt => 0,
      full_width => 4,
      gate_type => 1,
      latency => 0,
      num_inputs => 2
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din0 => dout_x_0,
      din1 => dout_x_3,
      en => dout_x_9,
      dout => dout_x_4
    );
  x: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_5
    );
  x_x_0: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_6
    );
  x_x_1: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_7
    );
  x_x_2: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_8
    );
  x_x_3: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_9
    );
  x_x_4: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_10
    );
end structural;
