# Xilinx CORE Generator 6.2i
# User = isnique&amy
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in C:\MATLAB6p5\work\xpid3sg\temp\coregen_tmp\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=C:\MATLAB6p5\work\xpid3sg\temp\coregen_tmp
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Spartan2
# outputoption=DesignFlow
# overwritefiles=True
# simvendor=ModelSim
# expandedprojectpath=C:\MATLAB6p5\work\xpid3sg\temp\coregen_tmp

SETPROJECT ./
Set current Project to C:\MATLAB6p5\work\xpid3sg\temp\coregen_tmp
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = false
CSET latency = 0
CSET operation = add
CSET output_options = non_registered
CSET output_width = 69
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 69
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 69
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_c14c50981235b92f
GENERATE
Preparing to elaborate core...
Elaborating the module...
Generating the core .EDN implementation netlist...
 
