library ieee;
use ieee.std_logic_1164.all;

entity bus_mux_16 is
   port(a,b : in std_logic_vector(15 downto 0);
        sel : IN STD_LOGIC;
        y : out std_logic_vector(15 downto 0));
end bus_mux_16;

architecture bus_mux_16_behav of bus_mux_16 is
begin
   y <= a when(sel = '0') else
        b when(sel = '1');
end bus_mux_16_behav;
