// C:\MATLAB6P5\WORK\ISNIAMY\XSPARTAN2
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Thu Aug 11 12:10:36 2005

`timescale 1ns/1ns

module spartan2_tb;
	reg ce;
	reg clk;
	reg [15:0] in_x_0;
	wire [23:0] out_x_0;

	spartan2_clk_wrapper UUT (
		.ce(ce),
		.clk(clk),
		.in_x_0(in_x_0),
		.out_x_0(out_x_0)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	clk = 1'b0;
	#10
	clk = 1'b1;
	#10
	ANNOTATE_out_x_0;
	#40
	clk = 1'b0;
	#40
	clk = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("c:\\matlab6p5\\work\\isniamy\\xspartan2\\spartan2_tb.ano");

	// --------------------
	ce = 1'b1;
	in_x_0 = 16'b0000001100000000; //300
	// --------------------
	#100 // Time=100 ns
	in_x_0 = 16'b0000010000000000; //400
	// --------------------
	#110 // Time=210 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_out_x_0;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,out_x_0,%b]",
			$time, out_x_0);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule
