delay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

ERROR:HDLCompilers:247 - clk_d10ms.v line 17 Reference to scalar wire 'clock_divms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 17 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

ERROR:HDLCompilers:247 - clk_d10ms.v line 17 Reference to scalar wire 'clock_divms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 17 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

ERROR:HDLCompilers:247 - clk_d10ms.v line 17 Reference to scalar wire 'clock_divms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 17 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

Analyzing module <clk_d10ms>.
ERROR:Xst:1932 - Port <clock_div10ms> in instance of module <clk_d10ms> is missing in the module definition.
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_divms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 18 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_divms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 18 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

ERROR:HDLCompilers:247 - clk_d10ms.v line 17 Reference to scalar wire 'clock_divms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 17 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

ERROR:HDLCompilers:247 - clk_d10ms.v line 17 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 17 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

ERROR:HDLCompilers:247 - clk_d10ms.v line 17 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 17 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

Analyzing module <clk_d10ms>.
ERROR:Xst:1932 - Port <clock_div10ms> in instance of module <clk_d10ms> is missing in the module definition.
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 18 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 48860 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 18 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
ERROR:HDLCompilers:26 - counter.v line 2 expecting ';', found 'input'
ERROR:HDLCompilers:208 - counter.v line 1 Port reference 'out' was not declared as input, inout or output
ERROR:HDLCompilers:208 - counter.v line 1 Port reference 'in' was not declared as input, inout or output
Module <counter> compiled
ERROR:HDLCompilers:26 - counter.v line 9 expecting 'endmodule', found 'EOF'
Analysis of file <counter.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
ERROR:HDLCompilers:26 - counter.v line 2 expecting ';', found 'input'
ERROR:HDLCompilers:208 - counter.v line 1 Port reference 'out' was not declared as input, inout or output
ERROR:HDLCompilers:208 - counter.v line 1 Port reference 'in' was not declared as input, inout or output
Module <counter> compiled
ERROR:HDLCompilers:26 - counter.v line 9 expecting 'endmodule', found 'EOF'
Analysis of file <counter.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
ERROR:HDLCompilers:26 - counter.v line 2 expecting ';', found 'input'
ERROR:HDLCompilers:208 - counter.v line 1 Port reference 'out' was not declared as input, inout or output
ERROR:HDLCompilers:208 - counter.v line 1 Port reference 'in' was not declared as input, inout or output
Module <counter> compiled
Analysis of file <counter.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
ERROR:HDLCompilers:28 - counter.v line 5 'count' has not been declared
ERROR:HDLCompilers:28 - counter.v line 5 'count' has not been declared
ERROR:HDLCompilers:26 - counter.v line 5 unexpected token: '1'
ERROR:HDLCompilers:26 - counter.v line 6 expecting ';', found ')'
Module <counter> compiled
ERROR:HDLCompilers:26 - counter.v line 7 expecting 'endmodule', found 'else'
Analysis of file <counter.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
Module <counter> compiled
ERROR:HDLCompilers:26 - counter.v line 7 expecting 'endmodule', found 'if'
Analysis of file <counter.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
Module <counter> compiled
ERROR:HDLCompilers:26 - counter.v line 7 expecting 'endmodule', found 'if'
Analysis of file <counter.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
ERROR:HDLCompilers:26 - counter.v line 9 unexpected token: 'else'
ERROR:HDLCompilers:26 - counter.v line 10 unexpected token: '0'
ERROR:HDLCompilers:26 - counter.v line 13 unexpected token: 'EOF'
ERROR:HDLCompilers:26 - counter.v line 13 expecting ';', found 'EOF'
ERROR:HDLCompilers:26 - counter.v line 13 unexpected token: 'EOF'
ERROR:HDLCompilers:26 - counter.v line 13 expecting 'end', found 'EOF'
Module <counter> compiled
ERROR:HDLCompilers:26 - counter.v line 13 expecting 'endmodule', found 'EOF'
Analysis of file <counter.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
Module <counter> compiled
No errors in compilation
Analysis of file <counter.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - counter.v line 9 Reference to scalar wire 'out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - counter.v line 9 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - counter.v line 11 Reference to scalar wire 'out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - counter.v line 11 Illegal left hand side of blocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
Module <counter> compiled
No errors in compilation
Analysis of file <counter.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - counter.v line 10 Reference to scalar wire 'out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - counter.v line 10 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - counter.v line 12 Reference to scalar wire 'out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - counter.v line 12 Illegal left hand side of blocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
ERROR:HDLCompilers:27 - counter.v line 6 Illegal redeclaration of 'out'
Module <counter> compiled
Analysis of file <counter.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
Module <counter> compiled
No errors in compilation
Analysis of file <counter.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <counter>.
Module <counter> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter>.
    Related source file is counter.v.
WARNING:Xst:647 - Input <in> is never used.
WARNING:Xst:1780 - Signal <out_> is never used or assigned.
    Found 32-bit comparator less for signal <$n0000> created at line 12.
    Found 32-bit adder for signal <$old_count_1>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <counter> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <counter> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block counter, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      27  out of    768     3%  
 Number of 4 input LUTs:                52  out of   1536     3%  
 Number of bonded IOBs:                  8  out of    144     5%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 counter.ngc
counter.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/counter.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "counter.ngd" ...

Writing NGDBUILD log file "counter.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:             7 out of    140    5%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  336
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "counter_map.mrp" for details.
Completed process "Map".

Mapping Module counter . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o counter_map.ncd counter.ngd counter.pcf
Mapping Module counter: DONE



Started process "Place & Route".





Constraints file: counter.pcf

Loading device database for application Par from file "counter_map.ncd".
   "counter" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs             7 out of 140     5%
      Number of LOCed External IOBs    0 out of 7       0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989686) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file counter.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file counter.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 21 14:55:40 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module counter . . .
PAR command line: par -w -intstyle ise -ol std -t 1 counter_map.ncd counter.ncd counter.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 18 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
ERROR:HDLCompilers:28 - clk_d10ms.v line 18 'clock_div10ms' has not been declared
ERROR:HDLCompilers:28 - clk_d10ms.v line 18 'clock_div10ms' has not been declared
Module <clk_d10ms> compiled
Analysis of file <clk_d10ms.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 18 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_div10ms_' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 18 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 18 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - clk_d10ms.v line 18 Illegal left hand side of nonblocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do count_1_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vlog 5.7g Compiler 2003.10 Oct 13 2003
# -- Compiling module counter
# 
# Top level modules:
# 	counter
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package textio
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Compiling entity count_1_tbw
# -- Compiling architecture testbench_arch of count_1_tbw
# ** Error: count_1_tbw.ant(19): near "in": expecting: IDENTIFIER
# ** Error: count_1_tbw.ant(24): near "in": expecting: IDENTIFIER
# ** Error: count_1_tbw.ant(29): near "port": expecting: ';'
# ** Error: count_1_tbw.ant(46): near "out": syntax error
# ** Error: count_1_tbw.ant(53): near "begin": syntax error
# ERROR: C:/Modeltech_xe_starter/win32xoem/vcom failed.
# Executing ONERROR command at macro ./count_1_tbw.ado line 11
ERROR: VSim failed to simulate annotated testbench

Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "counter.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 13: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:653 - Signal <clock_cnt<18>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <clock_cnt<17:0>> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 17.
    Found 32-bit adder for signal <$n0001> created at line 19.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of bonded IOBs:                  1  out of    144     0%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:             1 out of    140    1%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  48
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs             1 out of 140     1%
      Number of LOCed External IOBs    0 out of 1       0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989680) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 21 15:05:50 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - clk_d10ms.v line 18 Illegal left hand side of blocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
ERROR:Xst:880 - clk_d10ms.v line 18: Cannot mix blocking and non blocking assignments on signal <count>.
WARNING:Xst:905 - clk_d10ms.v line 13: The signals <count> are missing in the sensitivity list of always block.
 
Found 1 error(s). Aborting synthesis.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
ERROR:HDLCompilers:28 - clk_d10ms.v line 20 'reset' has not been declared
Module <clk_d10ms> compiled
Analysis of file <clk_d10ms.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 13: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:653 - Signal <clock_cnt<18>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <clock_cnt<17:0>> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 17.
    Found 32-bit adder for signal <$n0001> created at line 18.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of bonded IOBs:                  1  out of    144     0%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:             1 out of    140    1%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  48
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs             1 out of 140     1%
      Number of LOCed External IOBs    0 out of 1       0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989680) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 21 15:11:18 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 13: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:653 - Signal <clock_cnt<18>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <clock_cnt<17:0>> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 17.
    Found 32-bit adder for signal <$n0001> created at line 18.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of bonded IOBs:                  1  out of    144     0%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:             1 out of    140    1%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  48
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs             1 out of 140     1%
      Number of LOCed External IOBs    0 out of 1       0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989680) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 21 15:11:35 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Entity <top_spartan21> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 13: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:653 - Signal <clock_cnt<18>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <clock_cnt<17:0>> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 17.
    Found 32-bit adder for signal <$n0001> created at line 18.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <top_spartan21>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf.
Unit <top_spartan21> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan21> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_spartan21, actual ratio is 36.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     277  out of    768    36%  
 Number of Slice Flip Flops:            64  out of   1536     4%  
 Number of 4 input LUTs:               501  out of   1536    32%  
 Number of bonded IOBs:                 29  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XST_GND:G                          | NONE                   | 40    |
clock                              | BUFGP                  | 18    |
XLXI_2_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.275ns
   Maximum combinational path delay: 35.811ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 top_spartan21.ngc
top_spartan21.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXN_21' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 39812 kilobytes

Writing NGD file "top_spartan21.ngd" ...

Writing NGDBUILD log file "top_spartan21.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
ERROR:HDLCompilers:26 - clk_d10ms.v line 19 expecting 'end', found 'else'
ERROR:HDLCompilers:26 - clk_d10ms.v line 19 expecting 'end', found '('
ERROR:HDLCompilers:26 - clk_d10ms.v line 19 unexpected token: '>'
Module <clk_d10ms> compiled
ERROR:HDLCompilers:26 - clk_d10ms.v line 19 expecting 'endmodule', found '1500'
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Analysis of file <top_spartan21.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
ERROR:HDLCompilers:26 - clk_d10ms.v line 19 expecting 'end', found 'else'
ERROR:HDLCompilers:26 - clk_d10ms.v line 19 expecting 'end', found '('
ERROR:HDLCompilers:26 - clk_d10ms.v line 19 unexpected token: '>'
Module <clk_d10ms> compiled
ERROR:HDLCompilers:26 - clk_d10ms.v line 19 expecting 'endmodule', found '1500'
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Analysis of file <top_spartan21.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 13: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:653 - Signal <clock_cnt<18>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <clock_cnt<17:0>> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 17.
    Found 32-bit adder for signal <$n0001> created at line 18.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <top_spartan21>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf.
Unit <top_spartan21> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan21> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_spartan21, actual ratio is 36.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     277  out of    768    36%  
 Number of Slice Flip Flops:            64  out of   1536     4%  
 Number of 4 input LUTs:               501  out of   1536    32%  
 Number of bonded IOBs:                 29  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XST_GND:G                          | NONE                   | 40    |
clock                              | BUFGP                  | 18    |
XLXI_2_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.275ns
   Maximum combinational path delay: 35.811ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan21.ucf -p xc2s50-pq208-6
top_spartan21.ngc top_spartan21.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan21.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXN_21' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 39812 kilobytes

Writing NGD file "top_spartan21.ngd" ...

Writing NGDBUILD log file "top_spartan21.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
ERROR:HDLCompilers:120 - counter.v line 5 Illegal redeclaration of input 'in' as a reg
ERROR:HDLCompilers:26 - counter.v line 6 unexpected token: '{'
Module <counter> compiled
ERROR:HDLCompilers:26 - counter.v line 6 expecting 'endmodule', found '18'
Analysis of file <counter.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
ERROR:HDLCompilers:120 - counter.v line 5 Illegal redeclaration of input 'in' as a reg
Module <counter> compiled
Analysis of file <counter.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
Module <counter> compiled
No errors in compilation
Analysis of file <counter.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <counter>.
Module <counter> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter>.
    Related source file is counter.v.
WARNING:Xst:647 - Input <in> is never used.
WARNING:Xst:1780 - Signal <out_> is never used or assigned.
    Found 32-bit comparator less for signal <$n0000> created at line 13.
    Found 32-bit adder for signal <$old_count_1>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <counter> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <counter> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block counter, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      27  out of    768     3%  
 Number of 4 input LUTs:                52  out of   1536     3%  
 Number of bonded IOBs:                 19  out of    144    13%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 counter.ngc
counter.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/counter.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "counter.ngd" ...

Writing NGDBUILD log file "counter.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:            18 out of    140   12%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "counter_map.mrp" for details.
Completed process "Map".

Mapping Module counter . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o counter_map.ncd counter.ngd counter.pcf
Mapping Module counter: DONE



Started process "Place & Route".





Constraints file: counter.pcf

Loading device database for application Par from file "counter_map.ncd".
   "counter" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            18 out of 140    12%
      Number of LOCed External IOBs    0 out of 18      0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file counter.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file counter.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 21 15:29:17 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module counter . . .
PAR command line: par -w -intstyle ise -ol std -t 1 counter_map.ncd counter.ncd counter.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "counter.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
Module <counter> compiled
No errors in compilation
Analysis of file <counter.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - counter.v line 14 Reference to scalar wire 'out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - counter.v line 14 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - counter.v line 16 Reference to scalar wire 'out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - counter.v line 16 Illegal left hand side of blocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "counter.v"
Module <counter> compiled
No errors in compilation
Analysis of file <counter.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <counter>.
Module <counter> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter>.
    Related source file is counter.v.
WARNING:Xst:647 - Input <in> is never used.
WARNING:Xst:1780 - Signal <out_> is never used or assigned.
    Found 32-bit comparator less for signal <$n0000> created at line 13.
    Found 32-bit adder for signal <$old_count_1>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <counter> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <counter> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block counter, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      27  out of    768     3%  
 Number of 4 input LUTs:                52  out of   1536     3%  
 Number of bonded IOBs:                 19  out of    144    13%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 counter.ngc
counter.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/counter.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "counter.ngd" ...

Writing NGDBUILD log file "counter.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:            18 out of    140   12%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "counter_map.mrp" for details.
Completed process "Map".

Mapping Module counter . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o counter_map.ncd counter.ngd counter.pcf
Mapping Module counter: DONE



Started process "Place & Route".





Constraints file: counter.pcf

Loading device database for application Par from file "counter_map.ncd".
   "counter" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            18 out of 140    12%
      Number of LOCed External IOBs    0 out of 18      0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file counter.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file counter.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 21 16:15:34 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module counter . . .
PAR command line: par -w -intstyle ise -ol std -t 1 counter_map.ncd counter.ncd counter.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Entity <top_spartan21> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 13: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:653 - Signal <clock_cnt<18>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <clock_cnt<17:0>> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 17.
    Found 32-bit adder for signal <$n0001> created at line 18.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <top_spartan21>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf.
Unit <top_spartan21> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan21> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_spartan21, actual ratio is 36.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     277  out of    768    36%  
 Number of Slice Flip Flops:            64  out of   1536     4%  
 Number of 4 input LUTs:               501  out of   1536    32%  
 Number of bonded IOBs:                 29  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XST_GND:G                          | NONE                   | 40    |
clock                              | BUFGP                  | 18    |
XLXI_2_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.275ns
   Maximum combinational path delay: 35.811ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan21.ucf -p xc2s50-pq208-6
top_spartan21.ngc top_spartan21.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan21.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXN_21' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 39812 kilobytes

Writing NGD file "top_spartan21.ngd" ...

Writing NGDBUILD log file "top_spartan21.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        23 out of  1,536    1%
  Number of 4 input LUTs:           383 out of  1,536   24%
Logic Distribution:
    Number of occupied Slices:                         208 out of    768   27%
    Number of Slices containing only related logic:    208 out of    208  100%
    Number of Slices containing unrelated logic:         0 out of    208    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          403 out of  1,536   26%
      Number used as logic:                       383
      Number used as a route-thru:                 20
   Number of bonded IOBs:            29 out of    140   20%
      IOB Flip Flops:                               1
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,825
Additional JTAG gate count for IOBs:  1,440
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan21_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan21 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan21_map.ncd top_spartan21.ngd top_spartan21.pcf
Mapping Module top_spartan21: DONE



Started process "Place & Route".





Constraints file: top_spartan21.pcf

Loading device database for application Par from file "top_spartan21_map.ncd".
   "top_spartan21" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            29 out of 140    20%
      Number of LOCed External IOBs    0 out of 29      0%

   Number of SLICEs                  208 out of 768    27%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9899b8) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.........
Phase 5.8 (Checksum:9d3db5) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_spartan21.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1082 unrouted;       REAL time: 2 secs 

Phase 2: 1064 unrouted;       REAL time: 3 secs 

Phase 3: 262 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|       clock_BUFGP          |  Global  |    9   |  0.000     |  0.446      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_2_clock_cnt<17>    |   Local  |    5   |  0.063     |  2.983      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  52 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_spartan21.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 21 16:20:26 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan21 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan21_map.ncd top_spartan21.ncd top_spartan21.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf in Library work.
Entity <top_spartan2> (Architecture <behavioral>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_spartan2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan2> (Architecture <behavioral>).
Entity <top_spartan2> analyzed. Unit <top_spartan2> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf.
Unit <top_spartan2> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_spartan2, actual ratio is 37.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     278  out of    768    36%  
 Number of Slice Flip Flops:            66  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_4_clock_cnt_17:Q              | NONE                   | 8     |
XLXN_14(XLXI_3_choice_yy1:O)       | NONE(*)(XLXI_1_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u28)| 40    |
clk                                | BUFGP                  | 18    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.275ns
   Maximum combinational path delay: 35.811ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan2.ucf -p xc2s50-pq208-6
top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan2.ucf" ...
ERROR:NgdBuild:755 - Line 8 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 9 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 10 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 11 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 12 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 13 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 14 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 15 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 17 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 18 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 19 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(10)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 20 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(11)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 21 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(12)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 22 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(13)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 23 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(14)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 24 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(15)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 25 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 26 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 27 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 28 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 29 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 30 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 31 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(8)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 32 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(9)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
   "top_spartan2.ucf".

Writing NGDBUILD log file "top_spartan2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf in Library work.
Architecture behavioral of Entity top_spartan2 is up to date.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "choosen_out.v"
Module <choosen_out> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_spartan2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan2> (Architecture <behavioral>).
Entity <top_spartan2> analyzed. Unit <top_spartan2> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <choosen_out>.
Module <choosen_out> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <choosen_out>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice_nyy>.
    Found 1-bit register for signal <choice_y>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <choosen_out> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf.
Unit <top_spartan2> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block top_spartan2, actual ratio is 36.
FlipFlop XLXI_2_anode0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode2 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     280  out of    768    36%  
 Number of Slice Flip Flops:            69  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_4_clock_cnt_17:Q              | NONE                   | 11    |
XLXN_14(XLXI_3_choice_yy1:O)       | NONE(*)(XLXI_1_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u29)| 40    |
clk                                | BUFGP                  | 18    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.365ns
   Maximum combinational path delay: 35.901ns

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 top_spartan2.ngc
top_spartan2.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 39812 kilobytes

Writing NGD file "top_spartan2.ngd" ...

Writing NGDBUILD log file "top_spartan2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        48 out of  1,536    3%
  Number of 4 input LUTs:           384 out of  1,536   25%
Logic Distribution:
    Number of occupied Slices:                         209 out of    768   27%
    Number of Slices containing only related logic:    209 out of    209  100%
    Number of Slices containing unrelated logic:         0 out of    209    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          404 out of  1,536   26%
      Number used as logic:                       384
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              21
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  4,191
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan2_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan2_map.ncd top_spartan2.ngd top_spartan2.pcf
Mapping Module top_spartan2: DONE



Started process "Place & Route".





Constraints file: top_spartan2.pcf

Loading device database for application Par from file "top_spartan2_map.ncd".
   "top_spartan2" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs    0 out of 30      0%

   Number of SLICEs                  209 out of 768    27%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:9899ce) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
........
.
Phase 5.8 (Checksum:9d66b9) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file top_spartan2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1160 unrouted;       REAL time: 2 secs 

Phase 2: 1110 unrouted;       REAL time: 4 secs 

Phase 3: 258 unrouted;       REAL time: 4 secs 

Phase 4: 258 unrouted; (0)      REAL time: 4 secs 

Phase 5: 258 unrouted; (0)      REAL time: 4 secs 

Phase 6: 258 unrouted; (0)      REAL time: 4 secs 

Phase 7: 0 unrouted; (0)      REAL time: 4 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |    9   |  0.000     |  0.465      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_14          |   Local  |   28   |  1.982     |  4.723      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt(17)    |   Local  |   10   |  1.803     |  4.674      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_8917ce66 = PERIOD TIMEGRP "clk_891 | 100.000ns  | 4.859ns    | 9    
  7ce66"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  57 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file top_spartan2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Aug 21 17:09:29 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan2_map.ncd top_spartan2.ncd top_spartan2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan2.ucf -p xc2s50-pq208-6
top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 41860 kilobytes

Writing NGD file "top_spartan2.ngd" ...

Writing NGDBUILD log file "top_spartan2.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan21.ucf -p xc2s50-pq208-6
top_spartan21.ngc top_spartan21.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan21.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXN_21' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41860 kilobytes

Writing NGD file "top_spartan21.ngd" ...

Writing NGDBUILD log file "top_spartan21.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        23 out of  1,536    1%
  Number of 4 input LUTs:           383 out of  1,536   24%
Logic Distribution:
    Number of occupied Slices:                         208 out of    768   27%
    Number of Slices containing only related logic:    208 out of    208  100%
    Number of Slices containing unrelated logic:         0 out of    208    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          403 out of  1,536   26%
      Number used as logic:                       383
      Number used as a route-thru:                 20
   Number of bonded IOBs:            29 out of    140   20%
      IOB Flip Flops:                               1
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,825
Additional JTAG gate count for IOBs:  1,440
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan21_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan21 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan21_map.ncd top_spartan21.ngd top_spartan21.pcf
Mapping Module top_spartan21: DONE



Started process "Place & Route".





Constraints file: top_spartan21.pcf

Loading device database for application Par from file "top_spartan21_map.ncd".
   "top_spartan21" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            29 out of 140    20%
      Number of LOCed External IOBs   27 out of 29     93%

   Number of SLICEs                  208 out of 768    27%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9899b8) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9d1592) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_spartan21.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1082 unrouted;       REAL time: 0 secs 

Phase 2: 1064 unrouted;       REAL time: 3 secs 

Phase 3: 280 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|       clock_BUFGP          |  Global  |    9   |  0.000     |  0.465      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_2_clock_cnt<17>    |   Local  |    5   |  0.067     |  2.901      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  52 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_spartan21.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 14:16:20 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan21 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan21_map.ncd top_spartan21.ncd top_spartan21.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
ERROR:HDLCompilers:26 - clk_d10ms.v line 18 unexpected token: 'clock_div10ms'
ERROR:HDLCompilers:26 - clk_d10ms.v line 18 expecting 'end', found '!'
Module <clk_d10ms> compiled
ERROR:HDLCompilers:26 - clk_d10ms.v line 21 expecting 'endmodule', found 'end'
Analysis of file <clk_d10ms.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
ERROR:HDLCompilers:26 - clk_d10ms.v line 18 unexpected token: 'clock_div10ms'
ERROR:HDLCompilers:26 - clk_d10ms.v line 18 expecting 'end', found '!'
Module <clk_d10ms> compiled
ERROR:HDLCompilers:26 - clk_d10ms.v line 21 expecting 'endmodule', found 'end'
Analysis of file <clk_d10ms.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 13: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:653 - Signal <clock_cnt<18>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <clock_cnt<17:0>> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 17.
    Found 32-bit adder for signal <$n0001> created at line 19.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of bonded IOBs:                  1  out of    144     0%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 13: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:653 - Signal <clock_cnt<18>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <clock_cnt<17:0>> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 17.
    Found 32-bit adder for signal <$n0001> created at line 19.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of bonded IOBs:                  1  out of    144     0%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:             1 out of    140    1%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  48
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs             1 out of 140     1%
      Number of LOCed External IOBs    0 out of 1       0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989680) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 14:30:53 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Entity <top_spartan21> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 13: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:653 - Signal <clock_cnt<18>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <clock_cnt<17:0>> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 17.
    Found 32-bit adder for signal <$n0001> created at line 19.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <top_spartan21>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf.
Unit <top_spartan21> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan21> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_spartan21, actual ratio is 36.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     277  out of    768    36%  
 Number of Slice Flip Flops:            64  out of   1536     4%  
 Number of 4 input LUTs:               501  out of   1536    32%  
 Number of bonded IOBs:                 29  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XST_GND:G                          | NONE                   | 40    |
clock                              | BUFGP                  | 18    |
XLXI_2_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.275ns
   Maximum combinational path delay: 35.811ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan21.ucf -p xc2s50-pq208-6
top_spartan21.ngc top_spartan21.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan21.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXN_21' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41860 kilobytes

Writing NGD file "top_spartan21.ngd" ...

Writing NGDBUILD log file "top_spartan21.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        23 out of  1,536    1%
  Number of 4 input LUTs:           383 out of  1,536   24%
Logic Distribution:
    Number of occupied Slices:                         208 out of    768   27%
    Number of Slices containing only related logic:    208 out of    208  100%
    Number of Slices containing unrelated logic:         0 out of    208    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          403 out of  1,536   26%
      Number used as logic:                       383
      Number used as a route-thru:                 20
   Number of bonded IOBs:            29 out of    140   20%
      IOB Flip Flops:                               1
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,825
Additional JTAG gate count for IOBs:  1,440
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan21_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan21 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan21_map.ncd top_spartan21.ngd top_spartan21.pcf
Mapping Module top_spartan21: DONE



Started process "Place & Route".





Constraints file: top_spartan21.pcf

Loading device database for application Par from file "top_spartan21_map.ncd".
   "top_spartan21" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            29 out of 140    20%
      Number of LOCed External IOBs   27 out of 29     93%

   Number of SLICEs                  208 out of 768    27%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9899b8) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9d1592) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_spartan21.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1082 unrouted;       REAL time: 0 secs 

Phase 2: 1064 unrouted;       REAL time: 3 secs 

Phase 3: 280 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|       clock_BUFGP          |  Global  |    9   |  0.000     |  0.465      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_2_clock_cnt<17>    |   Local  |    5   |  0.067     |  2.901      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  52 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_spartan21.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 14:38:24 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan21 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan21_map.ncd top_spartan21.ncd top_spartan21.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
ERROR:HDLCompilers:26 - clk_d10ms.v line 18 unexpected token: 'clock_div10ms'
ERROR:HDLCompilers:26 - clk_d10ms.v line 18 expecting 'end', found '!'
Module <clk_d10ms> compiled
ERROR:HDLCompilers:26 - clk_d10ms.v line 21 expecting 'endmodule', found 'end'
Analysis of file <clk_d10ms.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - clk_d10ms.v line 18 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - clk_d10ms.v line 18 Illegal left hand side of blocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:246 - clk_d10ms.v line 24 Reference to vector reg 'clock_div10ms' is not a legal net lvalue
ERROR:HDLCompilers:53 - clk_d10ms.v line 24 Illegal left hand side of continuous assign
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:246 - clk_d10ms.v line 24 Reference to vector reg 'clock_div10ms' is not a legal net lvalue
ERROR:HDLCompilers:53 - clk_d10ms.v line 24 Illegal left hand side of continuous assign
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 14: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
WARNING:Xst:737 - Found 19-bit latch for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit adder for signal <count>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Latches                          : 1
 19-bit latch                      : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_15> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_14> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_13> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_12> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_11> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_10> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_9> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_8> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_7> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_6> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_5> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_4> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_3> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_2> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_1> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_17> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_18> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_16> (without init value) is constant in block <clk_d10ms>.

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:             1  out of   1536     0%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                 19  out of    144    13%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0000(Mcompar__n0000_inst_cy_51:O)| NONE(*)(clock_div10ms_0)| 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.657ns (Maximum Frequency: 273.411MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.068ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:            18 out of    140   12%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            18 out of 140    12%
      Number of LOCed External IOBs    0 out of 18      0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 14:48:20 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - clk_d10ms.v line 19 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - clk_d10ms.v line 19 Illegal left hand side of blocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 14: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
WARNING:Xst:737 - Found 19-bit latch for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit adder for signal <count>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Latches                          : 1
 19-bit latch                      : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_15> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_14> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_13> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_12> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_11> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_10> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_9> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_8> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_7> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_6> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_5> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_4> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_3> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_2> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_1> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_17> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_18> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_16> (without init value) is constant in block <clk_d10ms>.

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:             1  out of   1536     0%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                 19  out of    144    13%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0000(Mcompar__n0000_inst_cy_51:O)| NONE(*)(clock_div10ms_0)| 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.657ns (Maximum Frequency: 273.411MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.068ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:            18 out of    140   12%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            18 out of 140    12%
      Number of LOCed External IOBs    0 out of 18      0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 14:50:31 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 14: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
WARNING:Xst:737 - Found 19-bit latch for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit adder for signal <count>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Latches                          : 1
 19-bit latch                      : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_15> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_14> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_13> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_12> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_11> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_10> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_9> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_8> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_7> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_6> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_5> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_4> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_3> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_2> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_1> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_17> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_18> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_16> (without init value) is constant in block <clk_d10ms>.

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:             1  out of   1536     0%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                 19  out of    144    13%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0000(Mcompar__n0000_inst_cy_51:O)| NONE(*)(clock_div10ms_0)| 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.657ns (Maximum Frequency: 273.411MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.068ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:            18 out of    140   12%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            18 out of 140    12%
      Number of LOCed External IOBs    0 out of 18      0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 14:50:48 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
ERROR:HDLCompilers:27 - clk_d10ms.v line 11 Illegal redeclaration of 'clock_div10ms'
Module <clk_d10ms> compiled
Analysis of file <clk_d10ms.prj> failed.
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 14: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms1> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
WARNING:Xst:737 - Found 19-bit latch for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit adder for signal <count>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Latches                          : 1
 19-bit latch                      : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_15> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_14> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_13> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_12> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_11> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_10> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_9> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_8> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_7> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_6> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_5> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_4> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_3> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_2> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_1> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_17> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_18> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_16> (without init value) is constant in block <clk_d10ms>.

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:             1  out of   1536     0%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                 19  out of    144    13%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0000(Mcompar__n0000_inst_cy_51:O)| NONE(*)(clock_div10ms_0)| 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.657ns (Maximum Frequency: 273.411MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.068ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:            18 out of    140   12%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            18 out of 140    12%
      Number of LOCed External IOBs    0 out of 18      0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 14:52:36 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 14: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
WARNING:Xst:737 - Found 19-bit latch for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit adder for signal <count>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Latches                          : 1
 19-bit latch                      : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_15> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_14> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_13> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_12> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_11> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_10> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_9> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_8> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_7> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_6> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_5> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_4> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_3> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_2> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_1> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_17> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_18> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_16> (without init value) is constant in block <clk_d10ms>.

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:             1  out of   1536     0%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                 19  out of    144    13%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0000(Mcompar__n0000_inst_cy_51:O)| NONE(*)(clock_div10ms_0)| 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.657ns (Maximum Frequency: 273.411MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.068ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:            18 out of    140   12%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            18 out of 140    12%
      Number of LOCed External IOBs    0 out of 18      0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 14:53:33 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Instantiation Template".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.
Completed process "View VHDL Instantiation Template".




Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Instantiation Template".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.
Completed process "View VHDL Instantiation Template".




Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 14: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
WARNING:Xst:737 - Found 19-bit latch for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit adder for signal <count>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Latches                          : 1
 19-bit latch                      : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_15> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_14> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_13> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_12> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_11> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_10> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_9> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_8> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_7> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_6> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_5> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_4> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_3> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_2> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_1> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_17> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_18> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_16> (without init value) is constant in block <clk_d10ms>.

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:             1  out of   1536     0%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                 19  out of    144    13%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0000(Mcompar__n0000_inst_cy_51:O)| NONE(*)(clock_div10ms_0)| 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.657ns (Maximum Frequency: 273.411MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.068ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:            18 out of    140   12%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            18 out of 140    12%
      Number of LOCed External IOBs    0 out of 18      0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 15:00:42 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------

Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:155 - clk_d10ms.v line 23 Illegal function call to 'clock_cnt'
ERROR:HDLCompilers:185 - clk_d10ms.v line 23 Illegal right hand side of continuous assign
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 14: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:653 - Signal <clock_cnt<18>> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <clock_cnt<17:0>> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit adder for signal <$n0001> created at line 20.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of bonded IOBs:                  1  out of    144     0%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:             1 out of    140    1%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  48
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs             1 out of 140     1%
      Number of LOCed External IOBs    0 out of 1       0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989680) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 15:04:03 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Instantiation Template".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.
Completed process "View VHDL Instantiation Template".




Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 14: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:1306 - Output <clock_div10ms> is never assigned.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
WARNING:Xst:737 - Found 32-bit latch for signal <count>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit adder for signal <$n0001> created at line 20.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 



=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...
Loading design module "C:\MATLAB6p5\work\isniamy\xspartan2/clk_d10ms.ngc"...
WARNING:NgdBuild:578 - Design contains no instances.

Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:605 - logical root block 'clk_d10ms' with type 'clk_d10ms' is
   unexpanded. Symbol 'clk_d10ms' is not supported in target 'spartan2'.

NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:   0

Total memory usage is 36740 kilobytes


One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "clk_d10ms.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:247 - clk_d10ms.v line 19 Reference to scalar wire 'clock_div10ms' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - clk_d10ms.v line 19 Illegal left hand side of blocking assignment
--> 

Total memory usage is 46812 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 14: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
WARNING:Xst:737 - Found 19-bit latch for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit adder for signal <count>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Latches                          : 1
 19-bit latch                      : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_15> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_14> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_13> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_12> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_11> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_10> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_9> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_8> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_7> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_6> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_5> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_4> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_3> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_2> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_1> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_17> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_18> (without init value) is constant in block <clk_d10ms>.
WARNING:Xst:1710 - FF/Latch  <clock_div10ms_16> (without init value) is constant in block <clk_d10ms>.

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:             1  out of   1536     0%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                 19  out of    144    13%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0000(Mcompar__n0000_inst_cy_51:O)| NONE(*)(clock_div10ms_0)| 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.657ns (Maximum Frequency: 273.411MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.068ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:            18 out of    140   12%

Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            18 out of 140    12%
      Number of LOCed External IOBs    0 out of 18      0%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 0 unrouted;       REAL time: 0 secs 

Phase 2: 0 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 15:08:38 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Instantiation Template".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.
Completed process "View VHDL Instantiation Template".




Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
WARNING:Xst:905 - clk_d10ms.v line 14: The signals <count> are missing in the sensitivity list of always block.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:647 - Input <clock_sys> is never used.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
WARNING:Xst:737 - Found 1-bit latch for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit adder for signal <count>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Latches                          : 1
 1-bit latch                       : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:             1  out of   1536     0%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                  1  out of    144     0%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0000(Mcompar__n0000_inst_cy_51:O)| NONE(*)(clock_div10ms) | 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.657ns (Maximum Frequency: 273.411MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.068ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
ERROR:Pack:198 - NCD was not produced. All logic was removed from design.  This
   is usually due to having no input or output PAD connections in the design and
   no nets or symbols marked as 'SAVE'.  You can either add PADs or 'SAVE'
   attributes to the design, or run 'map -u' to disable logic trimming in the
   mapper.
Problem encountered generating the NCD.

Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: failed


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 18.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:            33  out of   1536     2%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                  1  out of    144     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock_sys                          | BUFGP                  | 33    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.344ns (Maximum Frequency: 157.629MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        33 out of  1,536    2%
  Number of 4 input LUTs:            19 out of  1,536    1%
Logic Distribution:
    Number of occupied Slices:                          27 out of    768    3%
    Number of Slices containing only related logic:     27 out of     27  100%
    Number of Slices containing unrelated logic:         0 out of     27    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           52 out of  1,536    3%
      Number used as logic:                        19
      Number used as a route-thru:                 33
   Number of bonded IOBs:             1 out of    140    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  624
Additional JTAG gate count for IOBs:  96
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             1 out of 140     1%
      Number of LOCed External IOBs    0 out of 1       0%

   Number of SLICEs                   27 out of 768     3%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896a3) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
........
Phase 5.8 (Checksum:98d5c7) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 123 unrouted;       REAL time: 0 secs 

Phase 2: 106 unrouted;       REAL time: 0 secs 

Phase 3: 5 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|   clock_sys_BUFGP          |  Global  |   17   |  0.014     |  0.465      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  45 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 15:15:40 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully




Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 15.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:            33  out of   1536     2%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                  1  out of    144     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock_sys                          | BUFGP                  | 33    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.344ns (Maximum Frequency: 157.629MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 15.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_d10ms, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:            33  out of   1536     2%  
 Number of 4 input LUTs:                53  out of   1536     3%  
 Number of bonded IOBs:                  1  out of    144     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock_sys                          | BUFGP                  | 33    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.344ns (Maximum Frequency: 157.629MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 clk_d10ms.ngc
clk_d10ms.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/clk_d10ms.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "clk_d10ms.ngd" ...

Writing NGDBUILD log file "clk_d10ms.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        33 out of  1,536    2%
  Number of 4 input LUTs:            19 out of  1,536    1%
Logic Distribution:
    Number of occupied Slices:                          27 out of    768    3%
    Number of Slices containing only related logic:     27 out of     27  100%
    Number of Slices containing unrelated logic:         0 out of     27    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           52 out of  1,536    3%
      Number used as logic:                        19
      Number used as a route-thru:                 33
   Number of bonded IOBs:             1 out of    140    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  624
Additional JTAG gate count for IOBs:  96
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clk_d10ms_map.mrp" for details.
Completed process "Map".

Mapping Module clk_d10ms . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o clk_d10ms_map.ncd clk_d10ms.ngd clk_d10ms.pcf
Mapping Module clk_d10ms: DONE



Started process "Place & Route".





Constraints file: clk_d10ms.pcf

Loading device database for application Par from file "clk_d10ms_map.ncd".
   "clk_d10ms" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             1 out of 140     1%
      Number of LOCed External IOBs    0 out of 1       0%

   Number of SLICEs                   27 out of 768     3%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896a3) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
........
Phase 5.8 (Checksum:98d5c7) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clk_d10ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 123 unrouted;       REAL time: 0 secs 

Phase 2: 106 unrouted;       REAL time: 0 secs 

Phase 3: 5 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|   clock_sys_BUFGP          |  Global  |   17   |  0.014     |  0.465      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  45 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clk_d10ms.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 15:21:16 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clk_d10ms . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clk_d10ms_map.ncd clk_d10ms.ncd clk_d10ms.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Instantiation Template".

Compiling source file "clk_d10ms.v"
tdtfi(verilog) completed successfully.
Completed process "View VHDL Instantiation Template".




Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "choosen_out.v"
Module <debounser> compiled
No errors in compilation
Analysis of file <debounser.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <debounser>.
Module <debounser> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <debounser>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice1>.
    Found 1-bit register for signal <choice2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <debounser> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <debounser> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block debounser, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                       2  out of    768     0%  
 Number of Slice Flip Flops:             2  out of   1536     0%  
 Number of 4 input LUTs:                 1  out of   1536     0%  
 Number of bonded IOBs:                  2  out of    144     1%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock                              | BUFGP                  | 2     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.025ns (Maximum Frequency: 330.579MHz)
   Minimum input arrival time before clock: 2.520ns
   Maximum output required time after clock: 8.543ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 debounser.ngc
debounser.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/debounser.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "debounser.ngd" ...

Writing NGDBUILD log file "debounser.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         1 out of  1,536    1%
  Number of 4 input LUTs:             1 out of  1,536    1%
Logic Distribution:
    Number of occupied Slices:                           2 out of    768    1%
    Number of Slices containing only related logic:      2 out of      2  100%
    Number of Slices containing unrelated logic:         0 out of      2    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         1 out of  1,536    1%
   Number of bonded IOBs:             2 out of    140    1%
      IOB Flip Flops:                               1
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  22
Additional JTAG gate count for IOBs:  144
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "debounser_map.mrp" for details.
Completed process "Map".

Mapping Module debounser . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o debounser_map.ncd debounser.ngd debounser.pcf
Mapping Module debounser: DONE



Started process "Place & Route".





Constraints file: debounser.pcf

Loading device database for application Par from file "debounser_map.ncd".
   "debounser" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             2 out of 140     1%
      Number of LOCed External IOBs    0 out of 2       0%

   Number of SLICEs                    2 out of 768     1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989697) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:989a99) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file debounser.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 7 unrouted;       REAL time: 0 secs 

Phase 2: 5 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|       clock_BUFGP          |  Global  |    2   |  0.094     |  0.446      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  46 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file debounser.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 15:27:18 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module debounser . . .
PAR command line: par -w -intstyle ise -ol std -t 1 debounser_map.ncd debounser.ncd debounser.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "choosen_out.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Instantiation Template".

Compiling source file "choosen_out.v"
tdtfi(verilog) completed successfully.
Completed process "View VHDL Instantiation Template".




Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf in Library work.
ERROR:HDLParsers:856 - C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf Line 86. No default value for unconnected port <choice>.
ERROR:HDLParsers:856 - C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf Line 86. No default value for unconnected port <clock>.
--> 

Total memory usage is 47836 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf in Library work.
Entity <top_spartan2> (Architecture <behavioral>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "choosen_out.v"
Module <debounser> compiled
No errors in compilation
Analysis of file <top_spartan2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan2> (Architecture <behavioral>).
Entity <top_spartan2> analyzed. Unit <top_spartan2> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <debounser>.
Module <debounser> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <debounser>.
    Related source file is choosen_out.v.
    Found 1-bit register for signal <choice1>.
    Found 1-bit register for signal <choice2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <debounser> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf.
Unit <top_spartan2> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_spartan2, actual ratio is 37.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     278  out of    768    36%  
 Number of Slice Flip Flops:            66  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 18    |
XLXN_14(XLXI_6_choice31:O)         | NONE(*)(XLXI_1_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u26)| 40    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 8     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.275ns
   Maximum combinational path delay: 35.811ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan2.ucf -p xc2s50-pq208-6
top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan2.ucf" ...
ERROR:NgdBuild:755 - Line 8 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 9 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 10 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 11 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 12 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 13 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 14 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 15 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 17 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 18 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 19 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(10)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 20 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(11)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 21 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(12)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 22 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(13)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 23 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(14)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 24 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(15)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 25 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 26 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 27 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 28 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 29 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 30 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 31 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(8)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 32 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(9)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
   "top_spartan2.ucf".

Writing NGDBUILD log file "top_spartan2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "debounser.v"
Module <debounser> compiled
No errors in compilation
Analysis of file <debounser.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <debounser>.
Module <debounser> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <debounser>.
    Related source file is debounser.v.
    Found 1-bit register for signal <choice1>.
    Found 1-bit register for signal <choice2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <debounser> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <debounser> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block debounser, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                       2  out of    768     0%  
 Number of Slice Flip Flops:             2  out of   1536     0%  
 Number of 4 input LUTs:                 1  out of   1536     0%  
 Number of bonded IOBs:                  2  out of    144     1%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock                              | BUFGP                  | 2     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.025ns (Maximum Frequency: 330.579MHz)
   Minimum input arrival time before clock: 2.520ns
   Maximum output required time after clock: 8.543ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 debounser.ngc
debounser.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/debounser.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36740 kilobytes

Writing NGD file "debounser.ngd" ...

Writing NGDBUILD log file "debounser.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         1 out of  1,536    1%
  Number of 4 input LUTs:             1 out of  1,536    1%
Logic Distribution:
    Number of occupied Slices:                           2 out of    768    1%
    Number of Slices containing only related logic:      2 out of      2  100%
    Number of Slices containing unrelated logic:         0 out of      2    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         1 out of  1,536    1%
   Number of bonded IOBs:             2 out of    140    1%
      IOB Flip Flops:                               1
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  22
Additional JTAG gate count for IOBs:  144
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "debounser_map.mrp" for details.
Completed process "Map".

Mapping Module debounser . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o debounser_map.ncd debounser.ngd debounser.pcf
Mapping Module debounser: DONE



Started process "Place & Route".





Constraints file: debounser.pcf

Loading device database for application Par from file "debounser_map.ncd".
   "debounser" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             2 out of 140     1%
      Number of LOCed External IOBs    0 out of 2       0%

   Number of SLICEs                    2 out of 768     1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989697) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:989a99) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file debounser.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 7 unrouted;       REAL time: 0 secs 

Phase 2: 5 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|       clock_BUFGP          |  Global  |    2   |  0.094     |  0.446      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  46 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file debounser.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 15:34:06 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module debounser . . .
PAR command line: par -w -intstyle ise -ol std -t 1 debounser_map.ncd debounser.ncd debounser.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf in Library work.
Architecture behavioral of Entity top_spartan2 is up to date.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "debounser.v"
Module <debounser> compiled
No errors in compilation
Analysis of file <top_spartan2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan2> (Architecture <behavioral>).
Entity <top_spartan2> analyzed. Unit <top_spartan2> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <debounser>.
Module <debounser> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <debounser>.
    Related source file is debounser.v.
    Found 1-bit register for signal <choice1>.
    Found 1-bit register for signal <choice2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <debounser> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf.
Unit <top_spartan2> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_spartan2, actual ratio is 37.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     278  out of    768    36%  
 Number of Slice Flip Flops:            66  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 18    |
XLXN_14(XLXI_6_choice31:O)         | NONE(*)(XLXI_1_spartan2_top_delay_synth_reg_srl_inst_last_srl17e_u27)| 40    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 8     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.275ns
   Maximum combinational path delay: 35.811ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan2.ucf -p xc2s50-pq208-6
top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan2.ucf" ...
ERROR:NgdBuild:755 - Line 8 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 9 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 10 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 11 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 12 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 13 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 14 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 15 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 17 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 18 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 19 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(10)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 20 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(11)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 21 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(12)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 22 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(13)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 23 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(14)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 24 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(15)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 25 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 26 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 27 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 28 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 29 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 30 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 31 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(8)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 32 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(9)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
   "top_spartan2.ucf".

Writing NGDBUILD log file "top_spartan2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "debounser.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf in Library work.
Entity <top_spartan2> (Architecture <behavioral>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "debounser.v"
Module <debounser> compiled
No errors in compilation
Analysis of file <top_spartan2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan2> (Architecture <behavioral>).
Entity <top_spartan2> analyzed. Unit <top_spartan2> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <debounser>.
Module <debounser> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <debounser>.
    Related source file is debounser.v.
    Found 1-bit register for signal <choice1>.
    Found 1-bit register for signal <choice2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <debounser> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf.
Unit <top_spartan2> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_spartan2, actual ratio is 37.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     278  out of    768    36%  
 Number of Slice Flip Flops:            66  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 18    |
XLXN_14(XLXI_8_choice31:O)         | NONE(*)(XLXI_1_spartan2_top_delay_synth_reg_srl_inst_last_srl17e_u26)| 40    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 8     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.275ns
   Maximum combinational path delay: 35.811ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan2.ucf -p xc2s50-pq208-6
top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan2.ucf" ...
ERROR:NgdBuild:755 - Line 8 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 9 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 10 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 11 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 12 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 13 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 14 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 15 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 17 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 18 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 19 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(10)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 20 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(11)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 21 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(12)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 22 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(13)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 23 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(14)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 24 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(15)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 25 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 26 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 27 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 28 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 29 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 30 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 31 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(8)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 32 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(9)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
   "top_spartan2.ucf".

Writing NGDBUILD log file "top_spartan2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan2.ucf -p xc2s50-pq208-6
top_spartan2.ngc top_spartan2.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan2.ucf" ...
ERROR:NgdBuild:755 - Line 8 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 9 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 10 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 11 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 12 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 13 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 14 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 15 in 'top_spartan2.ucf': Could not find net(s)
   'chatod(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 17 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 18 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 19 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(10)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 20 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(11)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 21 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(12)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 22 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(13)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 23 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(14)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 24 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(15)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 25 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 26 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 27 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 28 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 29 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 30 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 31 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(8)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 32 in 'top_spartan2.ucf': Could not find net(s)
   'in_x_0(9)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
   "top_spartan2.ucf".

Writing NGDBUILD log file "top_spartan2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_div.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <clk_div.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 18-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_div> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 1.36 / 2.38 s | Elapsed : 1.00 / 2.00 s
 
--> 

Total memory usage is 54028 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "debounser.v"
Module <debounser> compiled
No errors in compilation
Analysis of file <debounser.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <debounser>.
Module <debounser> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <debounser>.
    Related source file is debounser.v.
    Found 1-bit register for signal <choice1>.
    Found 1-bit register for signal <choice2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <debounser> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <debounser> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 1.26 / 2.30 s | Elapsed : 1.00 / 2.00 s
 
--> 

Total memory usage is 54028 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf in Library work.
Architecture behavioral of Entity top_spartan2 is up to date.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "debounser.v"
Module <debounser> compiled
No errors in compilation
Analysis of file <top_spartan2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan2> (Architecture <behavioral>).
Entity <top_spartan2> analyzed. Unit <top_spartan2> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <debounser>.
Module <debounser> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <debounser>.
    Related source file is debounser.v.
    Found 1-bit register for signal <choice1>.
    Found 1-bit register for signal <choice2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <debounser> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.vhf.
Unit <top_spartan2> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan2> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block top_spartan2, actual ratio is 36.
FlipFlop XLXI_2_anode0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode2 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     280  out of    768    36%  
 Number of Slice Flip Flops:            69  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 18    |
XLXN_14(XLXI_8_choice31:O)         | NONE(*)(XLXI_1_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u221)| 40    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 11    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.365ns
   Maximum combinational path delay: 35.901ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 top_spartan2.ngc
top_spartan2.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 39812 kilobytes

Writing NGD file "top_spartan2.ngd" ...

Writing NGDBUILD log file "top_spartan2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        48 out of  1,536    3%
  Number of 4 input LUTs:           384 out of  1,536   25%
Logic Distribution:
    Number of occupied Slices:                         209 out of    768   27%
    Number of Slices containing only related logic:    209 out of    209  100%
    Number of Slices containing unrelated logic:         0 out of    209    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          404 out of  1,536   26%
      Number used as logic:                       384
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              21
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  4,191
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan2_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan2_map.ncd top_spartan2.ngd top_spartan2.pcf
Mapping Module top_spartan2: DONE



Started process "Place & Route".





Constraints file: top_spartan2.pcf

Loading device database for application Par from file "top_spartan2_map.ncd".
   "top_spartan2" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs    0 out of 30      0%

   Number of SLICEs                  209 out of 768    27%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:9899ce) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
........
.
Phase 5.8 (Checksum:9d66b9) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_spartan2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1160 unrouted;       REAL time: 2 secs 

Phase 2: 1110 unrouted;       REAL time: 3 secs 

Phase 3: 259 unrouted;       REAL time: 4 secs 

Phase 4: 259 unrouted; (0)      REAL time: 4 secs 

Phase 5: 259 unrouted; (0)      REAL time: 4 secs 

Phase 6: 259 unrouted; (0)      REAL time: 4 secs 

Phase 7: 0 unrouted; (0)      REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |    9   |  0.000     |  0.465      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_14          |   Local  |   28   |  1.982     |  4.723      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt(17)    |   Local  |   10   |  1.803     |  4.674      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_8917ce66 = PERIOD TIMEGRP "clk_891 | 100.000ns  | 4.859ns    | 9    
  7ce66"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  57 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file top_spartan2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 15:41:08 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan2_map.ncd top_spartan2.ncd top_spartan2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <seg7_driver.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 1.47 / 2.48 s | Elapsed : 1.00 / 2.00 s
 
--> 

Total memory usage is 54028 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
ERROR:DesignEntry:77 - Net "out_(23)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(22)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(21)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(20)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(19)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(18)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(17)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(16)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(15)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(14)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(13)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(12)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(11)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(10)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(9)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(8)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(7)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(6)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(5)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(4)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(3)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(2)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(1)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(0)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:4 - Bus "out_(23:0)" and its subbus are connected to different
   IO Ports.
ERROR:DesignEntry:4 - Bus "out_(23:0)" and its subbus are connected to different
   IO Ports.
ERROR:DesignEntry:4 - Bus "out_(23:0)" and its subbus are connected to different
   IO Ports.
Error: 
Process "View VHDL Functional Model" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
ERROR:DesignEntry:77 - Net "out_(23)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(22)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(21)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(20)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(19)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(18)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(17)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(16)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(15)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(14)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(13)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(12)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(11)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(10)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(9)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(8)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(7)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(6)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(5)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(4)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(3)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(2)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(1)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:77 - Net "out_(0)" is connected to input ports and instance
   output pins. A net cannot be connected to both input ports and instance
   output pins
ERROR:DesignEntry:4 - Bus "out_(23:0)" and its subbus are connected to different
   IO Ports.
ERROR:DesignEntry:4 - Bus "out_(23:0)" and its subbus are connected to different
   IO Ports.
ERROR:DesignEntry:4 - Bus "out_(23:0)" and its subbus are connected to different
   IO Ports.
Error: 
Process "View VHDL Functional Model" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan22.vhf in Library work.
ERROR:HDLParsers:164 - C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan22.vhf Line 14. parse error, unexpected IN, expecting IDENTIFIER
--> 

Total memory usage is 47836 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan22.vhf in Library work.
Entity <top_spartan22> (Architecture <BEHAVIORAL>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "debounser.v"
Module <debounser> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_spartan22.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan22> (Architecture <BEHAVIORAL>).
Entity <top_spartan22> analyzed. Unit <top_spartan22> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <debounser>.
Module <debounser> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <debounser>.
    Related source file is debounser.v.
    Found 1-bit register for signal <choice1>.
    Found 1-bit register for signal <choice2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <debounser> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan22>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan22.vhf.
Unit <top_spartan22> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan22> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block top_spartan22, actual ratio is 36.
FlipFlop XLXI_2_anode0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode2 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     280  out of    768    36%  
 Number of Slice Flip Flops:            69  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 20    |
XLXN_1(XLXI_3_choice31:O)          | NONE(*)(XLXI_1_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u222)| 40    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 9     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.365ns
   Maximum combinational path delay: 35.901ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -i -p xc2s50-pq208-6 top_spartan22.ngc
top_spartan22.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan22.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_1_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 39812 kilobytes

Writing NGD file "top_spartan22.ngd" ...

Writing NGDBUILD log file "top_spartan22.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        48 out of  1,536    3%
  Number of 4 input LUTs:           384 out of  1,536   25%
Logic Distribution:
    Number of occupied Slices:                         209 out of    768   27%
    Number of Slices containing only related logic:    209 out of    209  100%
    Number of Slices containing unrelated logic:         0 out of    209    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          404 out of  1,536   26%
      Number used as logic:                       384
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              21
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  4,191
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan22_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan22 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan22_map.ncd top_spartan22.ngd top_spartan22.pcf
Mapping Module top_spartan22: DONE



Started process "Place & Route".





Constraints file: top_spartan22.pcf

Loading device database for application Par from file "top_spartan22_map.ncd".
   "top_spartan22" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs    0 out of 30      0%

   Number of SLICEs                  209 out of 768    27%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:9899ce) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
......
.
Phase 5.8 (Checksum:9d3ba8) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file top_spartan22.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1160 unrouted;       REAL time: 2 secs 

Phase 2: 1113 unrouted;       REAL time: 4 secs 

Phase 3: 220 unrouted;       REAL time: 4 secs 

Phase 4: 220 unrouted; (0)      REAL time: 4 secs 

Phase 5: 220 unrouted; (0)      REAL time: 4 secs 

Phase 6: 220 unrouted; (0)      REAL time: 4 secs 

Phase 7: 0 unrouted; (0)      REAL time: 4 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   11   |  0.114     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|            XLXN_1          |   Local  |   28   |  1.339     |  4.087      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt(17)    |   Local  |    8   |  0.767     |  2.951      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_8917ce66 = PERIOD TIMEGRP "clk_891 | 100.000ns  | 4.859ns    | 9    
  7ce66"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  57 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file top_spartan22.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 15:57:42 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan22 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan22_map.ncd top_spartan22.ncd top_spartan22.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 15.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 1.38 / 2.42 s | Elapsed : 1.00 / 2.00 s
 
--> 

Total memory usage is 54028 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
ERROR:DesignEntry:30 - Instance "XLXI_2" referencing symbol "clk_div" is out of
   date.
Error: 
Process "View VHDL Functional Model" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
ERROR:DesignEntry:30 - Instance "XLXI_2" referencing symbol "clk_div" is out of
   date.
Error: 
Process "View VHDL Functional Model" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Entity <top_spartan21> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 15.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <top_spartan21>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf.
Unit <top_spartan21> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 2
 18-bit up counter                 : 1
 32-bit up counter                 : 1
# Registers                        : 6
 1-bit register                    : 5
 2-bit register                    : 1
# Comparators                      : 1
 32-bit comparator less            : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan21> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 11.56 / 12.59 s | Elapsed : 12.00 / 13.00 s
 
--> 

Total memory usage is 73484 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "View RTL Schematic".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
WARNING:Xst:1780 - Signal <clock_cnt> is never used or assigned.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 15.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

=========================================================================
*                            Final Report                               *
=========================================================================
Completed process "View RTL Schematic".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "View RTL Schematic".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 22.
    Found 19-bit up counter for signal <clock_cnt>.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

=========================================================================
*                            Final Report                               *
=========================================================================
Completed process "View RTL Schematic".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "View RTL Schematic".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
WARNING:Xst:1780 - Signal <clock_div10ms_> is never used or assigned.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator less for signal <$n0000> created at line 22.
    Found 19-bit up counter for signal <clock_cnt>.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 1
 32-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

=========================================================================
*                            Final Report                               *
=========================================================================
Completed process "View RTL Schematic".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "View RTL Schematic".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
No errors in compilation
Analysis of file <clk_d10ms.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator greatequal for signal <$n0003> created at line 20.
    Found 19-bit up counter for signal <clock_cnt>.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
 32-bit up counter                 : 1
 19-bit up counter                 : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 1
 32-bit comparator greatequal      : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

=========================================================================
*                            Final Report                               *
=========================================================================
Completed process "View RTL Schematic".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_d10ms.v"
Module <clk_d10ms> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_spartan21.prj> succeeded.
 
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf in Library work.
Architecture behavioral of Entity top_spartan21 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan21> (Architecture <behavioral>).
Entity <top_spartan21> analyzed. Unit <top_spartan21> generated.

Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <clk_d10ms>.
Module <clk_d10ms> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_d10ms>.
    Related source file is clk_d10ms.v.
    Found 1-bit register for signal <clock_div10ms>.
    Found 32-bit comparator greatequal for signal <$n0003> created at line 20.
    Found 19-bit up counter for signal <clock_cnt>.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <clk_d10ms> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <top_spartan21>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.vhf.
Unit <top_spartan21> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 3
 18-bit up counter                 : 1
 32-bit up counter                 : 1
 19-bit up counter                 : 1
# Registers                        : 6
 1-bit register                    : 5
 2-bit register                    : 1
# Comparators                      : 1
 32-bit comparator greatequal      : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan21> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...

Optimizing unit <clk_d10ms> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_spartan21, actual ratio is 42.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     336  out of    768    43%  
 Number of Slice Flip Flops:           116  out of   1536     7%  
 Number of 4 input LUTs:               580  out of   1536    37%  
 Number of bonded IOBs:                 29  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_10_clock_div10ms:Q            | NONE                   | 40    |
clock                              | BUFGP                  | 70    |
XLXI_2_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.275ns
   Maximum combinational path delay: 35.811ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\isniamy\xspartan2/_ngo -uc top_spartan21.ucf -p xc2s50-pq208-6
top_spartan21.ngc top_spartan21.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan21.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_86c49814
0491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_9b2656d2
3c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0
a7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d
3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_5cb3e9894aa707
ba.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\multiplier_spartan2_6_0_22d1b55eb2467a
ac.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xspartan2\_ngo\adder_subtracter_spartan2_6_0_adf215fe
c985a9ef.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i

Annotating constraints to design from file "top_spartan21.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(38)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(39)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(40)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(41)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(42)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(43)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(44)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(45)' has no load
WARNING:NgdBuild:454 - logical net
   'XLXI_4_spartan2_top_addsub4_core_instance6/S(46)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  23

Total memory usage is 41860 kilobytes

Writing NGD file "top_spartan21.ngd" ...

Writing NGDBUILD log file "top_spartan21.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        99 out of  1,536    6%
  Number of 4 input LUTs:           410 out of  1,536   26%
Logic Distribution:
    Number of occupied Slices:                         250 out of    768   32%
    Number of Slices containing only related logic:    250 out of    250  100%
    Number of Slices containing unrelated logic:         0 out of    250    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          481 out of  1,536   31%
      Number used as logic:                       410
      Number used as a route-thru:                 71
   Number of bonded IOBs:            29 out of    140   20%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  5,071
Additional JTAG gate count for IOBs:  1,440
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_spartan21_map.mrp" for details.
Completed process "Map".

Mapping Module top_spartan21 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_spartan21_map.ncd top_spartan21.ngd top_spartan21.pcf
Mapping Module top_spartan21: DONE



Started process "Place & Route".





Constraints file: top_spartan21.pcf

Loading device database for application Par from file "top_spartan21_map.ncd".
   "top_spartan21" is an NCD, version 2.38, device xc2s50, package pq208, speed
-6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            29 out of 140    20%
      Number of LOCed External IOBs   27 out of 29     93%

   Number of SLICEs                  250 out of 768    32%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989ad0) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
...............
Phase 5.8 (Checksum:9e0b5f) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_spartan21.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1365 unrouted;       REAL time: 2 secs 

Phase 2: 1300 unrouted;       REAL time: 4 secs 

Phase 3: 313 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|       clock_BUFGP          |  Global  |   38   |  0.095     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|   XLXI_10_clock_div10ms    |   Local  |   29   |  1.523     |  3.506      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_2_clock_cnt<17>    |   Local  |    5   |  0.618     |  3.494      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  52 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_spartan21.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Aug 23 16:32:19 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_spartan21 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_spartan21_map.ncd top_spartan21.ncd top_spartan21.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv_8_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity spartan2_addsub1
# -- Compiling architecture behavior of spartan2_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: spartan2_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: spartan2_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: spartan2_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_adf215fec985a9ef". (No entity named "adder_subtracter_spartan2_6_0_adf215fec985a9ef" was found)
# WARNING[1]: spartan2_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity spartan2_kd
# -- Compiling architecture behavior of spartan2_kd
# WARNING[1]: spartan2_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: spartan2_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_5cb3e9894aa707ba". (No entity named "multiplier_spartan2_6_0_5cb3e9894aa707ba" was found)
# WARNING[1]: spartan2_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity spartan2
# -- Compiling architecture structural of spartan2
# -- Loading entity spartan2_addsub1
# -- Loading entity xldelay
# -- Loading entity spartan2_kd
# -- Loading entity xlsl2slv
# -- Compiling entity spartan2_clock_driver
# -- Compiling architecture structural of spartan2_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity spartan2_clk_wrapper
# -- Compiling architecture structural of spartan2_clk_wrapper
# -- Loading entity spartan2_clock_driver
# -- Loading entity spartan2
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv_8_tbw
# -- Compiling architecture testbench_arch of tv_8_tbw
# -- Loading entity spartan2_clk_wrapper
# -- Compiling configuration spartan2_clk_wrapper_cfg
# -- Loading entity tv_8_tbw
# -- Loading architecture testbench_arch of tv_8_tbw
# vsim -lib work -t 1ps tv_8_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv_8_tbw(testbench_arch)
# Loading work.spartan2_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.spartan2_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.spartan2(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.spartan2_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.spartan2_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5542 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 16016 ms  Iteration: 0  Process: /tv_8_tbw/line__81 File: tv_8_tbw.ant
# Break at tv_8_tbw.ant line 99
# Stopped at tv_8_tbw.ant line 99 


Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv_8_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity spartan2_addsub1
# -- Compiling architecture behavior of spartan2_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: spartan2_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: spartan2_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: spartan2_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_adf215fec985a9ef". (No entity named "adder_subtracter_spartan2_6_0_adf215fec985a9ef" was found)
# WARNING[1]: spartan2_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity spartan2_kd
# -- Compiling architecture behavior of spartan2_kd
# WARNING[1]: spartan2_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: spartan2_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_5cb3e9894aa707ba". (No entity named "multiplier_spartan2_6_0_5cb3e9894aa707ba" was found)
# WARNING[1]: spartan2_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity spartan2
# -- Compiling architecture structural of spartan2
# -- Loading entity spartan2_addsub1
# -- Loading entity xldelay
# -- Loading entity spartan2_kd
# -- Loading entity xlsl2slv
# -- Compiling entity spartan2_clock_driver
# -- Compiling architecture structural of spartan2_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity spartan2_clk_wrapper
# -- Compiling architecture structural of spartan2_clk_wrapper
# -- Loading entity spartan2_clock_driver
# -- Loading entity spartan2
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv_8_tbw
# -- Compiling architecture testbench_arch of tv_8_tbw
# -- Loading entity spartan2_clk_wrapper
# -- Compiling configuration spartan2_clk_wrapper_cfg
# -- Loading entity tv_8_tbw
# -- Loading architecture testbench_arch of tv_8_tbw
# vsim -lib work -t 1ps tv_8_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv_8_tbw(testbench_arch)
# Loading work.spartan2_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.spartan2_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.spartan2(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.spartan2_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.spartan2_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5542 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 16016 ms  Iteration: 0  Process: /tv_8_tbw/line__81 File: tv_8_tbw.ant
# Break at tv_8_tbw.ant line 99
# Stopped at tv_8_tbw.ant line 99 


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
ERROR:DesignEntry:30 - Instance "XLXI_9" referencing symbol "clk_div" is out of
   date.
Error: 
Process "View VHDL Functional Model" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".


