VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "spartan2"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        SIGNAL XLXN_6
        BEGIN SIGNAL dig(7:0)
        END SIGNAL
        BEGIN SIGNAL dig(15:8)
        END SIGNAL
        BEGIN SIGNAL dig(23:16)
        END SIGNAL
        SIGNAL clock_sys
        SIGNAL reset
        SIGNAL XLXN_20
        SIGNAL in_x_0(15:0)
        SIGNAL anode0
        SIGNAL anode1
        SIGNAL anode2
        SIGNAL anode3
        SIGNAL digit(7:0)
        BEGIN SIGNAL XLXN_36(23:0)
        END SIGNAL
        PORT Input clock_sys
        PORT Input reset
        PORT Input in_x_0(15:0)
        PORT Input anode0
        PORT Input anode1
        PORT Input anode2
        PORT Input anode3
        PORT Output digit(7:0)
        BEGIN BLOCKDEF clk_div
            TIMESTAMP 2005 7 26 8 11 44
            RECTANGLE N 64 -128 320 0 
            LINE N 64 -96 0 -96 
            LINE N 64 -32 0 -32 
            LINE N 320 -96 384 -96 
        END BLOCKDEF
        BEGIN BLOCKDEF seg7_driver
            TIMESTAMP 2005 7 26 8 11 56
            RECTANGLE N 64 -320 320 0 
            LINE N 64 -288 0 -288 
            LINE N 64 -224 0 -224 
            LINE N 64 -160 0 -160 
            RECTANGLE N 0 -172 64 -148 
            LINE N 64 -96 0 -96 
            RECTANGLE N 0 -108 64 -84 
            LINE N 64 -32 0 -32 
            RECTANGLE N 0 -44 64 -20 
            LINE N 320 -288 384 -288 
            LINE N 320 -224 384 -224 
            LINE N 320 -160 384 -160 
            LINE N 320 -96 384 -96 
            LINE N 320 -32 384 -32 
            RECTANGLE N 320 -44 384 -20 
        END BLOCKDEF
        BEGIN BLOCKDEF simple1_clk_wrapper
            TIMESTAMP 2005 7 26 8 12 50
            RECTANGLE N 64 -192 320 0 
            LINE N 64 -160 0 -160 
            LINE N 64 -96 0 -96 
            LINE N 64 -32 0 -32 
            RECTANGLE N 0 -44 64 -20 
            LINE N 320 -160 384 -160 
            RECTANGLE N 320 -172 384 -148 
        END BLOCKDEF
        BEGIN BLOCKDEF vcc
            TIMESTAMP 2001 2 2 12 52 44
            LINE N 64 -32 64 -64 
            LINE N 64 0 64 -32 
            LINE N 96 -64 32 -64 
        END BLOCKDEF
        BEGIN BLOCK XLXI_1 clk_div
            PIN clock_sys clock_sys
            PIN reset reset
            PIN clock_div XLXN_6
        END BLOCK
        BEGIN BLOCK XLXI_2 seg7_driver
            PIN clk_200hz XLXN_6
            PIN reset reset
            PIN dig0(7:0) dig(7:0)
            PIN dig1(7:0) dig(15:8)
            PIN dig2(7:0) dig(23:16)
            PIN anode0 anode0
            PIN anode1 anode1
            PIN anode2 anode2
            PIN anode3 anode3
            PIN digit(7:0) digit(7:0)
        END BLOCK
        BEGIN BLOCK XLXI_3 simple1_clk_wrapper
            PIN ce XLXN_20
            PIN clk clock_sys
            PIN in_x_0(15:0) in_x_0(15:0)
            PIN out_x_0(23:0) XLXN_36(23:0)
        END BLOCK
        BEGIN BLOCK XLXI_4 vcc
            PIN P XLXN_20
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 3520 2720
        BEGIN INSTANCE XLXI_2 1792 1264 R0
        END INSTANCE
        BEGIN INSTANCE XLXI_1 1136 864 R0
        END INSTANCE
        BEGIN BRANCH XLXN_6
            WIRE 1520 768 1648 768
            WIRE 1648 768 1648 976
            WIRE 1648 976 1792 976
        END BRANCH
        BEGIN BRANCH dig(7:0)
            WIRE 1712 1104 1792 1104
        END BRANCH
        BEGIN BRANCH dig(15:8)
            WIRE 1712 1168 1792 1168
        END BRANCH
        BEGIN BRANCH dig(23:16)
            WIRE 1712 1232 1792 1232
        END BRANCH
        BEGIN BRANCH reset
            WIRE 1056 1040 1136 1040
            WIRE 1136 1040 1792 1040
            WIRE 1136 832 1136 1040
        END BRANCH
        BEGIN BRANCH XLXN_20
            WIRE 992 1216 992 1312
            WIRE 992 1312 1136 1312
        END BRANCH
        BEGIN BRANCH clock_sys
            WIRE 784 768 912 768
            WIRE 912 768 1136 768
            WIRE 912 768 912 1376
            WIRE 912 1376 1136 1376
        END BRANCH
        INSTANCE XLXI_4 928 1216 R0
        BEGIN BRANCH in_x_0(15:0)
            WIRE 1056 1440 1136 1440
        END BRANCH
        BEGIN BRANCH anode0
            WIRE 2176 976 2224 976
        END BRANCH
        BEGIN BRANCH anode1
            WIRE 2176 1040 2224 1040
        END BRANCH
        BEGIN BRANCH anode2
            WIRE 2176 1104 2224 1104
        END BRANCH
        BEGIN BRANCH anode3
            WIRE 2176 1168 2224 1168
        END BRANCH
        IOMARKER 784 768 clock_sys R180 28
        IOMARKER 1056 1040 reset R180 28
        IOMARKER 1056 1440 in_x_0(15:0) R180 28
        IOMARKER 2224 976 anode0 R0 28
        IOMARKER 2224 1040 anode1 R0 28
        IOMARKER 2224 1104 anode2 R0 28
        IOMARKER 2224 1168 anode3 R0 28
        BEGIN BRANCH digit(7:0)
            WIRE 2176 1232 2208 1232
        END BRANCH
        IOMARKER 2208 1232 digit(7:0) R0 28
        BEGIN INSTANCE XLXI_3 1136 1472 R0
        END INSTANCE
        BEGIN BRANCH XLXN_36(23:0)
            WIRE 1520 1312 1552 1312
        END BRANCH
    END SHEET
END SCHEMATIC
