# do test4_tbw.ado 
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity test4_tbw
# -- Compiling architecture testbench_arch of test4_tbw
# WARNING[1]: test4_tbw.ant(42): No default binding for component: "pid_sysgen_clk_wrapper". (No entity named "pid_sysgen_clk_wrapper" was found)
# -- Compiling configuration pid_sysgen_clk_wrapper_cfg
# -- Loading entity test4_tbw
# -- Loading architecture testbench_arch of test4_tbw
# vsim -lib work -t 1ps test4_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.test4_tbw(testbench_arch)
# ** Warning: (vsim-3473) Component 'uut' is not bound.
#    Time: 0 ps  Iteration: 0  Region: /test4_tbw  File: test4_tbw.ant
# WARNING: Design size of 599 statements or 1 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 151 ms  Iteration: 0  Process: /test4_tbw/line__81 File: test4_tbw.ant
# Break at test4_tbw.ant line 139
# Stopped at test4_tbw.ant line 139 
