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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml test_pid_clk_wrapper
test_pid_clk_wrapper.ncd -o test_pid_clk_wrapper.twr test_pid_clk_wrapper.pcf


Design file:              test_pid_clk_wrapper.ncd
Physical constraint file: test_pid_clk_wrapper.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.

================================================================================
Timing constraint: TS_clk_24d42199 = PERIOD TIMEGRP "clk_24d42199"  100 nS   HIGH 50.000000 % ;

 510071 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is  23.244ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   23.244|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 510071 paths, 0 nets, and 667 connections

Design statistics:
   Minimum period:  23.244ns (Maximum frequency:  43.022MHz)


Analysis completed Wed Apr 06 21:33:25 2005
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Peak Memory Usage: 43 MB
