JDF G
// Created by Project Navigator ver 1.0
PROJECT spartan2_clk_wrapper.npl
DESIGN spartan2_clk_wrapper2
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE spartan2_pkgs.vhd
SOURCE spartan2_files.vhd
SOURCE spartan2_clk_wrapper.vhd
SOURCE top_spartan2.sch
SOURCE seg7_driver.v
SOURCE choosen_out.v
SOURCE clk_div.v
STIMULUS top_tb.tbw
STIMULUS top_tb2.vhd
STIMULUS sp2_tb.tbw
[STRATEGY-LIST]
Normal=True
