
function pid3sg_config(this_block)
  this_block.setTopLevelLanguage('VHDL');

  this_block.setEntityName('pid3sg');
  this_block.addSimulinkInport('gateway_in1');
  this_block.port('gateway_in1').useHDLVector(true);

  this_block.addSimulinkOutport('gateway_out');
  this_block.port('gateway_out').useHDLVector(true);
  this_block.port('gateway_out').setType('Fix_24_16');

  this_block.tagAsCombinational;

% -----------------------------
  % Do input type checking, and dynamic output type and 
  % generic setup here.
  if (this_block.inputTypesKnown)
    if (~ strcmp('Fix_20_8', this_block.port('gateway_in1').type))
      this_block.setError('Input data type for port "gateway_in1" must be "Fix_20_8".');
    end
  end

% -----------------------------

% -----------------------------
% Do input rate checking here.
  if (this_block.inputRatesKnown)
    if (this_block.port('gateway_in1').rate ~= 1)
      this_block.setError('Rate for port "gateway_in1" must be 1.');
    end
  end

% -----------------------------

% -----------------------------
% Set output rates here.
  this_block.port('gateway_out').setRate(1);


% -----------------------------
% Set up clocks and clock enables here.
  this_block.addClkCEPair('clk_sg', 'ce_sg', 1);


% -----------------------------
% Set up vhdl/verilog files here.
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/conv_pkg.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/clock_pkg.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/synth_reg.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/synth_reg_w_init.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/xlclkprobe.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/xlclockdriver.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/xlclockgenerator.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/xlsl2slv.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/xlslv2sl.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/synth_addsub.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/pid3sg_addsub1.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/synth_addsub.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/synth_addsub.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/synth_addsub.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/synth_addsub.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/synth_addsub.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/pid3sg_cmult3.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/xldelay.vhd');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/pid3sg.vhd');


% -----------------------------
% Set up .edn, .mif, .coe, ... files here.
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/adder_subtracter_spartan2_6_0_5c367c18f02e1774.edn');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/adder_subtracter_spartan2_6_0_7f6afff41f5f7a54.edn');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/adder_subtracter_spartan2_6_0_9b2656d23c19deaf.edn');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.edn');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/adder_subtracter_spartan2_6_0_c14c50981235b92f.edn');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/adder_subtracter_spartan2_6_0_c9cda3f921770426.edn');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/multiplier_spartan2_6_0_1b58cf9c5190cfad.edn');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/multiplier_spartan2_6_0_7808bd7aeb700524.edn');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/multiplier_spartan2_6_0_d65c3216ed700608.edn');
  this_block.addFile('C:/MATLAB6p5/work/xpid3sg/temp/multiplier_spartan2_6_0_eb0d20c59a93ecea.edn');

