
-- -----------------------------------------------------------------
-- System Generator version 6.2 vhdl source file.
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library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;

entity spartan2_clk_wrapper is 
  port (
    ce: in std_logic := '1';
    clk: in std_logic;
    in_x_0: in std_logic_vector(15 downto 0);
    out_x_0: out std_logic_vector(23 downto 0)
  );
end spartan2_clk_wrapper;

architecture structural of spartan2_clk_wrapper is
  component spartan2
    port (
      ce_sg: in std_logic;
      clk_sg: in std_logic;
      in_x_0: in std_logic_vector(15 downto 0);
      out_x_0: out std_logic_vector(23 downto 0)
    );
  end component;
  component spartan2_clock_driver
    port (
      sysce: in std_logic;
      sysclk: in std_logic;
      ce_sg: out std_logic;
      clk_sg: out std_logic
    );
  end component;
  component xlclkprobe
    port (
      ce: in std_logic;
      clk: in std_logic;
      clr: in std_logic;
      fakeoutforxst: out std_logic
    );
  end component;

  signal ce_sg: std_logic;
  signal clk_sg: std_logic;
  signal clk_sysgen: std_logic;
  signal in_x_1: std_logic_vector(15 downto 0);
  signal out_x_1: std_logic_vector(23 downto 0);

begin
  clk_sysgen <= clk;
  in_x_1 <= in_x_0;
  out_x_0 <= out_x_1;

  clock_driver: spartan2_clock_driver
    port map (
      sysce => '1',
      sysclk => clk_sysgen,
      ce_sg => ce_sg,
      clk_sg => clk_sg
    );
  spartan2_top: spartan2
    port map (
      ce_sg => ce_sg,
      clk_sg => clk_sg,
      in_x_0 => in_x_1,
      out_x_0 => out_x_1
    );
  xlclkprobe_x_0: xlclkprobe
    port map (
      ce => '1',
      clk => clk_sysgen,
      clr => '0'
    );
end structural;
