-- VHDL model created from top_spartan22.sch - Tue Aug 23 15:57:10 2005


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity top_spartan22 is
   port ( clk     : in    std_logic; 
          in_x    : in    std_logic_vector (15 downto 0); 
          pb      : in    std_logic; 
          reset   : in    std_logic; 
          anode0  : out   std_logic; 
          anode1  : out   std_logic; 
          anode2  : out   std_logic; 
          anode3  : out   std_logic; 
          cathode : out   std_logic_vector (7 downto 0));
end top_spartan22;

architecture BEHAVIORAL of top_spartan22 is
   attribute BOX_TYPE   : STRING ;
   signal out_x   : std_logic_vector (23 downto 0);
   signal XLXN_1  : std_logic;
   signal XLXN_2  : std_logic;
   signal XLXN_6  : std_logic;
   component spartan2_clk_wrapper
      port ( ce      : in    std_logic; 
             clk     : in    std_logic; 
             in_x_0  : in    std_logic_vector (15 downto 0); 
             out_x_0 : out   std_logic_vector (23 downto 0));
   end component;
   
   component seg7_driver
      port ( clk_200hz : in    std_logic; 
             reset     : in    std_logic; 
             dig0      : in    std_logic_vector (7 downto 0); 
             dig1      : in    std_logic_vector (7 downto 0); 
             dig2      : in    std_logic_vector (7 downto 0); 
             anode0    : out   std_logic; 
             anode1    : out   std_logic; 
             anode2    : out   std_logic; 
             anode3    : out   std_logic; 
             digit     : out   std_logic_vector (7 downto 0));
   end component;
   
   component debounser
      port ( clock   : in    std_logic; 
             choice  : in    std_logic; 
             choice3 : out   std_logic);
   end component;
   
   component clk_div
      port ( clock_sys : in    std_logic; 
             reset     : in    std_logic; 
             clock_div : out   std_logic);
   end component;
   
   component VCC
      port ( P : out   std_logic);
   end component;
   attribute BOX_TYPE of VCC : COMPONENT is "BLACK_BOX";
   
begin
   XLXI_1 : spartan2_clk_wrapper
      port map (ce=>XLXN_6, clk=>XLXN_1, in_x_0(15 downto 0)=>in_x(15 downto
            0), out_x_0(23 downto 0)=>out_x(23 downto 0));
   
   XLXI_2 : seg7_driver
      port map (clk_200hz=>XLXN_2, dig0(7 downto 0)=>out_x(7 downto 0), dig1(7
            downto 0)=>out_x(15 downto 8), dig2(7 downto 0)=>out_x(23 downto
            16), reset=>reset, anode0=>anode0, anode1=>anode1, anode2=>anode2,
            anode3=>anode3, digit(7 downto 0)=>cathode(7 downto 0));
   
   XLXI_3 : debounser
      port map (choice=>pb, clock=>clk, choice3=>XLXN_1);
   
   XLXI_4 : clk_div
      port map (clock_sys=>clk, reset=>reset, clock_div=>XLXN_2);
   
   XLXI_5 : VCC
      port map (P=>XLXN_6);
   
end BEHAVIORAL;


