

block pid_test {
  port ce_sg: in "std_logic"  "" 
    attrs {
      "width" => 1
      "domain" => ""
      "rate_pair" => [
        1
        1
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk_sg: in "std_logic"  "" 
    attrs {
      "width" => 1
      "domain" => ""
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port gateway_in1: in "std_logic_vector(15 downto 0)"  "[15 : 0]" 
    attrs {
      "bin_pt" => 4
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "Fix_16_4"
      "simulink_name" => "pid_test/Gateway In1"
      "width" => 16
      "period" => 1
    }
  port gateway_out: out "std_logic_vector(15 downto 0)"  "[15 : 0]" 
    attrs {
      "bin_pt" => 11
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "Fix_16_11"
      "simulink_name" => "pid_test/Gateway Out"
      "width" => 16
      "period" => 1
    }


  ce_sg <= ce_sg_x_0
  clk_sg <= clk_sg_x_0
  gateway_in1 <= gateway_in1_x_0
  s_x_4 <= gateway_out

  subblock addsub1 pid_test_addsub1 {
    a => q_x_1
    b => p
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    en => dout
    rst => dout_x_0
    s => s
  }
  subblock addsub2 pid_test_addsub1 {
    a => s
    b => gateway_in1_x_0
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    en => dout_x_1
    rst => dout_x_12
    s => s_x_0
  }
  subblock addsub3 pid_test_addsub1 {
    a => gateway_in1_x_0
    b => q
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    en => dout_x_18
    rst => dout_x_19
    s => s_x_1
  }
  subblock addsub4 pid_test_addsub1 {
    a => s_x_3
    b => p_x_2
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    en => dout_x_20
    rst => dout_x_21
    s => s_x_2
  }
  subblock addsub5 pid_test_addsub1 {
    a => p_x_0
    b => p_x_1
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    en => dout_x_22
    rst => dout_x_23
    s => s_x_3
  }
  subblock addsub6 pid_test_addsub1 {
    a => s_x_2
    b => q_x_0
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    en => dout_x_24
    rst => dout_x_2
    s => s_x_4
  }
  subblock cmult3 pid_test_cmult3 {
    a => q
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    en => dout_x_3
    rst => dout_x_4
    p => p
  }
  subblock delay xldelay {
    ce => ce_sg_x_0
    clk => clk_sg_x_0
    clr => '0' : 'b0
    d => gateway_in1_x_0
    en => dout_x_11
    rst => dout_x_13
    q => q
  }
  subblock delay1 xldelay {
    ce => ce_sg_x_0
    clk => clk_sg_x_0
    clr => '0' : 'b0
    d => s_x_4
    en => dout_x_14
    rst => dout_x_15
    q => q_x_0
  }
  subblock delay2 xldelay {
    ce => ce_sg_x_0
    clk => clk_sg_x_0
    clr => '0' : 'b0
    d => q
    en => dout_x_16
    rst => dout_x_17
    q => q_x_1
  }
  subblock kd pid_test_cmult3 {
    a => s_x_0
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    en => dout_x_5
    rst => dout_x_6
    p => p_x_0
  }
  subblock ki pid_test_cmult3 {
    a => gateway_in1_x_0
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    en => dout_x_7
    rst => dout_x_8
    p => p_x_1
  }
  subblock kp pid_test_cmult3 {
    a => s_x_1
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    en => dout_x_9
    rst => dout_x_10
    p => p_x_2
  }
  subblock x xlsl2slv {
    din => '1' : 'b1
    dout => dout
  }
  subblock x_x_0 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_0
  }
  subblock x_x_1 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_1
  }
  subblock x_x_10 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_2
  }
  subblock x_x_11 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_3
  }
  subblock x_x_12 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_4
  }
  subblock x_x_13 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_5
  }
  subblock x_x_14 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_6
  }
  subblock x_x_15 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_7
  }
  subblock x_x_16 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_8
  }
  subblock x_x_17 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_9
  }
  subblock x_x_18 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_10
  }
  subblock x_x_19 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_11
  }
  subblock x_x_2 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_12
  }
  subblock x_x_20 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_13
  }
  subblock x_x_21 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_14
  }
  subblock x_x_22 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_15
  }
  subblock x_x_23 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_16
  }
  subblock x_x_24 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_17
  }
  subblock x_x_3 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_18
  }
  subblock x_x_4 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_19
  }
  subblock x_x_5 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_20
  }
  subblock x_x_6 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_21
  }
  subblock x_x_7 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_22
  }
  subblock x_x_8 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_23
  }
  subblock x_x_9 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_24
  }
}
  attrs {
    "simulink_name" => "pid_test"
    "is_top_level" => true
  }


block pid_test_addsub1 {
  port a: in "std_logic_vector(a_width - 1 downto 0)"  "[15 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 4
      "must_be_hdl_vector" => true
      "type" => "Fix_16_4"
      "simulink_name" => "pid_test/AddSub1/a"
      "width" => 16
      "period" => 1
    }
  port b: in "std_logic_vector(b_width - 1 downto 0)"  "[31 : 0]" 
    attrs {
      "port_id" => "2"
      "bin_pt" => 8
      "must_be_hdl_vector" => true
      "type" => "Fix_32_8"
      "simulink_name" => "pid_test/AddSub1/b"
      "width" => 32
      "period" => 1
    }
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "type" => "logic"
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "4"
      "simulink_name" => "pid_test/AddSub1/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port rst: in "std_logic_vector(rst_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "3"
      "simulink_name" => "pid_test/AddSub1/rst"
      "period" => -1
      "width" => 1
      "dangling_value" => 0
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port s: out "std_logic_vector(s_width - 1 downto 0)"  "[15 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 4
      "must_be_hdl_vector" => true
      "type" => "Fix_16_4"
      "simulink_name" => "pid_test/AddSub1/s"
      "width" => 16
      "period" => 1
    }
}
  attrs {
    "simulink_name" => "pid_test/AddSub1"
    "generics" => [
      [
        "a_width"
        "integer"
        "16"
      ]
      [
        "a_arith"
        "integer"
        "xlSigned"
      ]
      [
        "a_bin_pt"
        "integer"
        "4"
      ]
      [
        "b_width"
        "integer"
        "32"
      ]
      [
        "b_arith"
        "integer"
        "xlSigned"
      ]
      [
        "b_bin_pt"
        "integer"
        "8"
      ]
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "rst_width"
        "integer"
        "1"
      ]
      [
        "rst_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "rst_bin_pt"
        "integer"
        "0"
      ]
      [
        "s_width"
        "integer"
        "16"
      ]
      [
        "s_arith"
        "integer"
        "xlSigned"
      ]
      [
        "s_bin_pt"
        "integer"
        "4"
      ]
      [
        "core_name0"
        "string"
        "\"adder_subtracter_spartan2_6_0_438ebd1a25415d4b\""
      ]
      [
        "c_a_type"
        "integer"
        "0"
      ]
      [
        "c_a_width"
        "integer"
        "33"
      ]
      [
        "c_add_mode"
        "integer"
        "1"
      ]
      [
        "c_b_type"
        "integer"
        "0"
      ]
      [
        "c_b_width"
        "integer"
        "33"
      ]
      [
        "c_enable_rlocs"
        "integer"
        "1"
      ]
      [
        "c_has_b_in"
        "integer"
        "0"
      ]
      [
        "c_has_b_out"
        "integer"
        "0"
      ]
      [
        "c_has_c_in"
        "integer"
        "0"
      ]
      [
        "c_has_c_out"
        "integer"
        "0"
      ]
      [
        "c_has_ce"
        "integer"
        "0"
      ]
      [
        "c_has_q"
        "integer"
        "0"
      ]
      [
        "c_has_q_b_out"
        "integer"
        "0"
      ]
      [
        "c_has_q_c_out"
        "integer"
        "0"
      ]
      [
        "c_has_s"
        "integer"
        "1"
      ]
      [
        "c_has_sclr"
        "integer"
        "0"
      ]
      [
        "c_latency"
        "integer"
        "0"
      ]
      [
        "c_output_width"
        "integer"
        "33"
      ]
      [
        "core"
        "boolean"
        "true"
      ]
      [
        "extra_registers"
        "integer"
        "0"
      ]
      [
        "full_s_arith"
        "integer"
        "xlSigned"
      ]
      [
        "full_s_width"
        "integer"
        "33"
      ]
      [
        "latency"
        "integer"
        "0"
      ]
      [
        "mode"
        "integer"
        "2"
      ]
      [
        "overflow"
        "integer"
        "xlWrap"
      ]
      [
        "quantization"
        "integer"
        "xlTruncate"
      ]
    ]
  }


block pid_test_cmult3 {
  port a: in "std_logic_vector(a_width - 1 downto 0)"  "[15 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 4
      "must_be_hdl_vector" => true
      "type" => "Fix_16_4"
      "simulink_name" => "pid_test/CMult3/a"
      "width" => 16
      "period" => 1
    }
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "type" => "logic"
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "3"
      "simulink_name" => "pid_test/CMult3/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port rst: in "std_logic_vector(rst_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "2"
      "simulink_name" => "pid_test/CMult3/rst"
      "period" => -1
      "width" => 1
      "dangling_value" => 0
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port p: out "std_logic_vector(p_width - 1 downto 0)"  "[31 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 8
      "must_be_hdl_vector" => true
      "type" => "Fix_32_8"
      "simulink_name" => "pid_test/CMult3/p"
      "width" => 32
      "period" => 1
    }
}
  attrs {
    "simulink_name" => "pid_test/CMult3"
    "generics" => [
      [
        "a_width"
        "integer"
        "16"
      ]
      [
        "a_arith"
        "integer"
        "xlSigned"
      ]
      [
        "a_bin_pt"
        "integer"
        "4"
      ]
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "p_width"
        "integer"
        "32"
      ]
      [
        "p_arith"
        "integer"
        "xlSigned"
      ]
      [
        "p_bin_pt"
        "integer"
        "8"
      ]
      [
        "rst_width"
        "integer"
        "1"
      ]
      [
        "rst_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "rst_bin_pt"
        "integer"
        "0"
      ]
      [
        "core_name0"
        "string"
        "\"multiplier_spartan2_6_0_4db32212508f9e05\""
      ]
      [
        "b_bin_pt"
        "integer"
        "4"
      ]
      [
        "bram_addr_width"
        "integer"
        "8"
      ]
      [
        "c_a_type"
        "integer"
        "0"
      ]
      [
        "c_a_width"
        "integer"
        "16"
      ]
      [
        "c_b_constant"
        "integer"
        "1"
      ]
      [
        "c_b_type"
        "integer"
        "1"
      ]
      [
        "c_b_value_hi"
        "integer"
        "0"
      ]
      [
        "c_b_value_low"
        "integer"
        "32"
      ]
      [
        "c_b_width"
        "integer"
        "6"
      ]
      [
        "c_baat"
        "integer"
        "16"
      ]
      [
        "c_has_b"
        "integer"
        "0"
      ]
      [
        "c_has_loadb"
        "integer"
        "0"
      ]
      [
        "c_has_nd"
        "integer"
        "0"
      ]
      [
        "c_has_o"
        "integer"
        "1"
      ]
      [
        "c_has_q"
        "integer"
        "0"
      ]
      [
        "c_mem_type"
        "integer"
        "0"
      ]
      [
        "c_mult_type"
        "integer"
        "2"
      ]
      [
        "c_output_hold"
        "integer"
        "0"
      ]
      [
        "c_output_width"
        "integer"
        "32"
      ]
      [
        "c_pipelined"
        "integer"
        "0"
      ]
      [
        "c_reg_inputs"
        "integer"
        "0"
      ]
      [
        "c_type"
        "integer"
        "0"
      ]
      [
        "const_bin_pt"
        "integer"
        "4"
      ]
      [
        "extra_registers"
        "integer"
        "0"
      ]
      [
        "latency"
        "integer"
        "0"
      ]
      [
        "multsign"
        "integer"
        "xlSigned"
      ]
      [
        "overflow"
        "integer"
        "xlWrap"
      ]
      [
        "oversample"
        "integer"
        "1"
      ]
      [
        "quantization"
        "integer"
        "xlTruncate"
      ]
      [
        "*c_b_value"
        "string"
        "\"0000000000100000\""
      ]
    ]
  }


block xldelay {
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "rate_pair" => [
        1
        1
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "type" => "logic"
    }
  port d: in "std_logic_vector(d_width - 1 downto 0)"  "[15 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 4
      "must_be_hdl_vector" => true
      "type" => "Fix_16_4"
      "simulink_name" => "pid_test/Delay/d"
      "width" => 16
      "period" => 1
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "3"
      "simulink_name" => "pid_test/Delay/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port rst: in "std_logic_vector(rst_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "2"
      "simulink_name" => "pid_test/Delay/rst"
      "period" => -1
      "width" => 1
      "dangling_value" => 0
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port q: out "std_logic_vector(q_width - 1 downto 0)"  "[15 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 4
      "must_be_hdl_vector" => true
      "type" => "Fix_16_4"
      "simulink_name" => "pid_test/Delay/q"
      "width" => 16
      "period" => 1
    }
}
  attrs {
    "simulink_name" => "pid_test/Delay"
    "generics" => [
      [
        "d_width"
        "integer"
        "16"
      ]
      [
        "d_arith"
        "integer"
        "xlSigned"
      ]
      [
        "d_bin_pt"
        "integer"
        "4"
      ]
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "q_width"
        "integer"
        "16"
      ]
      [
        "q_arith"
        "integer"
        "xlSigned"
      ]
      [
        "q_bin_pt"
        "integer"
        "4"
      ]
      [
        "rst_width"
        "integer"
        "1"
      ]
      [
        "rst_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "rst_bin_pt"
        "integer"
        "0"
      ]
      [
        "latency"
        "integer"
        "1"
      ]
      [
        "reg_retiming"
        "boolean"
        "false"
      ]
    ]
  }


block xlsl2slv {
  port din: in "std_logic"  "" 
    attrs {
      "width" => 1
      "type" => "logic"
      "period" => -1
    }
  port dout: out "std_logic_vector(dout_width - 1 downto 0)"  "" 
    attrs {
      "width" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
      "period" => -1
    }
}
  attrs {
    "generics" => [
      [
        "dout_width"
        "integer"
        "1"
      ]
      [
        "dout_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "dout_bin_pt"
        "integer"
        "0"
      ]
    ]
  }

attrs {
  "matlab_java_directory" => "C:/MATLAB6p5/sys/java/jre/win32/jre/bin"
  "clocks_gcd" => 0.01
  "mdl_path" => "C:/MATLAB6p5/work/pid_test.mdl"
  "design_file" => "C:/MATLAB6p5/work/xpid_test/temp/pid_test.vhd"
  "config_script" => "C:/MATLAB6p5/work/xpid_test/temp/pid_test_config.m"
  "part_family" => "Spartan2"
  "device" => "xc2s50-6pq208"
  "coregen_part_family" => "Spartan2"
  "synthesis_tool" => "XST"
  "hdl_kind" => "vhdl"
  "start_time" => 0
  "xilinx" => "C:/Xilinx"
  "system_clock_period" => 100
  "target_dir" => "C:/MATLAB6p5/work/xpid_test"
  "stop_time" => 10
  "matlab_perl_directory" => "C:/MATLAB6p5/sys/perl/win32/bin/"
  "version" => "6.2"
  "ise_version" => "6.2i"
  "top_level" => "pid_test"
  "hdl_files" => [
    "conv_pkg.vhd"
    "clock_pkg.vhd"
    "synth_reg.vhd"
    "synth_reg_w_init.vhd"
    "xlclkprobe.vhd"
    "xlclockdriver.vhd"
    "xlclockgenerator.vhd"
    "xlsl2slv.vhd"
    "xlslv2sl.vhd"
    "synth_addsub.vhd"
    "pid_test_addsub1.vhd"
    "synth_addsub.vhd"
    "synth_addsub.vhd"
    "synth_addsub.vhd"
    "synth_addsub.vhd"
    "synth_addsub.vhd"
    "pid_test_cmult3.vhd"
    "xldelay.vhd"
    "pid_test.vhd"
  ]
  "design" => "pid_test"
  "vhdl" => [  ]
  "verilog" => [  ]
  "sysgen" => "C:/MATLAB6p5/toolbox/xilinx/sysgen"
}
