-- HIERARCHY
-- MODULE test1
-- ENDHIERARCHY


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity srl17e is
    generic (width : integer:=16;
             latency : integer :=8);
    port (clk   : in std_logic;
          ce    : in std_logic;
          d     : in std_logic_vector(width-1 downto 0);
          q     : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
    component SRL16E
        port (D   : in STD_ULOGIC;
              CE  : in STD_ULOGIC;
              CLK : in STD_ULOGIC;
              A0  : in STD_ULOGIC;
              A1  : in STD_ULOGIC;
              A2  : in STD_ULOGIC;
              A3  : in STD_ULOGIC;
              Q   : out STD_ULOGIC);
    end component;
    attribute syn_black_box of SRL16E : component is true;
    attribute fpga_dont_touch of SRL16E : component is "true";
    component FDE
        port(
            Q  :        out   STD_ULOGIC;
            D  :        in    STD_ULOGIC;
            C  :        in    STD_ULOGIC;
            CE :        in    STD_ULOGIC);
    end component;
    attribute syn_black_box of FDE : component is true;
    attribute fpga_dont_touch of FDE : component is "true";
    constant a : std_logic_vector(4 downto 0) :=
        integer_to_std_logic_vector(latency-2,5,xlSigned);
    signal d_delayed : std_logic_vector(width-1 downto 0);
    signal srl16_out : std_logic_vector(width-1 downto 0);
begin
    d_delayed <= d after 200 ps;
    reg_array : for i in 0 to width-1 generate
        srl16_used: if latency > 1 generate
            u1 : srl16e port map(clk => clk,
                                 d => d_delayed(i),
                                 q => srl16_out(i),
                                 ce => ce,
                                 a0 => a(0),
                                 a1 => a(1),
                                 a2 => a(2),
                                 a3 => a(3));
        end generate;
        srl16_not_used: if latency <= 1 generate
            srl16_out(i) <= d_delayed(i);
        end generate;
        fde_used: if latency /= 0  generate
            u2 : fde port map(c => clk,
                              d => srl16_out(i),
                              q => q(i),
                              ce => ce);
        end generate;
        fde_not_used: if latency = 0  generate
            q(i) <= srl16_out(i);
        end generate;
    end generate;
 end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
    generic (width           : integer := 8;
             latency         : integer := 1);
    port (i       : in std_logic_vector(width-1 downto 0);
          ce      : in std_logic;
          clr     : in std_logic;
          clk     : in std_logic;
          o       : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
    component srl17e
        generic (width : integer:=16;
                 latency : integer :=8);
        port (clk : in std_logic;
              ce  : in std_logic;
              d   : in std_logic_vector(width-1 downto 0);
              q   : out std_logic_vector(width-1 downto 0));
    end component;
    function calc_num_srl17es (latency : integer)
        return integer
    is
        variable remaining_latency : integer;
        variable result : integer;
    begin
        result := latency / 17;
        remaining_latency := latency - (result * 17);
        if (remaining_latency /= 0) then
            result := result + 1;
        end if;
        return result;
    end;
    constant complete_num_srl17es : integer := latency / 17;
    constant num_srl17es : integer := calc_num_srl17es(latency);
    constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
    type register_array is array (num_srl17es downto 0) of
        std_logic_vector(width-1 downto 0);
    signal z : register_array;
begin
    z(0) <= i;
    complete_ones : if complete_num_srl17es > 0 generate
        srl17e_array: for i in 0 to complete_num_srl17es-1 generate
            delay_comp : srl17e
                generic map (width => width,
                             latency => 17)
                port map (clk => clk,
                          ce  => ce,
                          d       => z(i),
                          q       => z(i+1));
        end generate;
    end generate;
    partial_one : if remaining_latency > 0 generate
        last_srl17e : srl17e
            generic map (width => width,
                         latency => remaining_latency)
            port map (clk => clk,
                      ce  => ce,
                      d   => z(num_srl17es-1),
                      q   => z(num_srl17es));
    end generate;
    o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
    generic (width           : integer := 8;
             latency         : integer := 1);
    port (i       : in std_logic_vector(width-1 downto 0);
          ce      : in std_logic;
          clr     : in std_logic;
          clk     : in std_logic;
          o       : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
  type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
  signal reg_bank : reg_array_type := (others => (others => '0'));
  signal reg_bank_in : reg_array_type := (others => (others => '0'));
  attribute syn_allow_retiming : boolean;
  attribute syn_srlstyle : string;
  attribute syn_allow_retiming of reg_bank : signal is true;
  attribute syn_allow_retiming of reg_bank_in : signal is true;
  attribute syn_srlstyle of reg_bank : signal is "registers";
  attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
  latency_eq_0: if latency = 0 generate
    o <= i;
  end generate latency_eq_0;
  latency_gt_0: if latency >= 1 generate
    o <= reg_bank(latency-1);
    reg_bank_in(0) <= i;
    loop_gen: for idx in latency-2 downto 0 generate
      reg_bank_in(idx+1) <= reg_bank(idx);
    end generate loop_gen;
    sync_loop: for sync_idx in latency-1 downto 0 generate
      sync_proc: process (clk)
      begin
        if clk'event and clk = '1' then
          if ce = '1'  then
            reg_bank(sync_idx) <= reg_bank_in(sync_idx);
          end if;
        end if;
      end process sync_proc;
    end generate sync_loop;
  end generate latency_gt_0;
end behav;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity single_reg_w_init is
  generic (
    width: integer := 8;
    init_index: integer := 0;
    init_value: bit_vector := b"0000"
  );
  port (
    i: in std_logic_vector(width - 1 downto 0);
    ce: in std_logic;
    clr: in std_logic;
    clk: in std_logic;
    o: out std_logic_vector(width - 1 downto 0)
  );
end single_reg_w_init;
architecture structural of single_reg_w_init is
  function build_init_const(width: integer;
                            init_index: integer;
                            init_value: bit_vector)
    return std_logic_vector
  is
    variable result: std_logic_vector(width - 1 downto 0);
  begin
    if init_index = 0 then
      result := (others => '0');
    elsif init_index = 1 then
      result := (others => '0');
      result(0) := '1';
    else
      result := to_stdlogicvector(init_value);
    end if;
    return result;
  end;
  component fdre
    port (
      q: out std_ulogic;
      d: in  std_ulogic;
      c: in  std_ulogic;
      ce: in  std_ulogic;
      r: in  std_ulogic
    );
  end component;
  attribute syn_black_box of fdre: component is true;
  attribute fpga_dont_touch of fdre: component is "true";
  component fdse
    port (
      q: out std_ulogic;
      d: in  std_ulogic;
      c: in  std_ulogic;
      ce: in  std_ulogic;
      s: in  std_ulogic
    );
  end component;
  attribute syn_black_box of fdse: component is true;
  attribute fpga_dont_touch of fdse: component is "true";
  constant init_const: std_logic_vector(width - 1 downto 0)
    := build_init_const(width, init_index, init_value);
begin
  fd_prim_array: for index in 0 to width - 1 generate
    bit_is_0: if (init_const(index) = '0') generate
      fdre_comp: fdre
        port map (
          c => clk,
          d => i(index),
          q => o(index),
          ce => ce,
          r => clr
        );
    end generate;
    bit_is_1: if (init_const(index) = '1') generate
      fdse_comp: fdse
        port map (
          c => clk,
          d => i(index),
          q => o(index),
          ce => ce,
          s => clr
        );
    end generate;
  end generate;
end architecture structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity synth_reg_w_init is
  generic (
    width: integer := 8;
    init_index: integer := 0;
    init_value: bit_vector := b"0000";
    latency: integer := 1
  );
  port (
    i: in std_logic_vector(width - 1 downto 0);
    ce: in std_logic;
    clr: in std_logic;
    clk: in std_logic;
    o: out std_logic_vector(width - 1 downto 0)
  );
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
  component single_reg_w_init
    generic (
      width: integer := 8;
      init_index: integer := 0;
      init_value: bit_vector := b"0000"
    );
    port (
      i: in std_logic_vector(width - 1 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      o: out std_logic_vector(width - 1 downto 0)
    );
  end component;
  signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
  signal dly_clr: std_logic;
begin
  latency_eq_0: if (latency = 0) generate
    o <= i;
  end generate;
  latency_gt_0: if (latency >= 1) generate
    dly_i((latency + 1) * width - 1 downto latency * width) <= i
      after 200 ps;
    dly_clr <= clr after 200 ps;
    fd_array: for index in latency downto 1 generate
       reg_comp: single_reg_w_init
          generic map (
            width => width,
            init_index => init_index,
            init_value => init_value
          )
          port map (
            clk => clk,
            i => dly_i((index + 1) * width - 1 downto index * width),
            o => dly_i(index * width - 1 downto (index - 1) * width),
            ce => ce,
            clr => dly_clr
          );
    end generate;
    o <= dly_i(width - 1 downto 0);
  end generate;
end structural;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;
entity xlclkprobe is
  port (clk             : in std_logic;
        clr             : in std_logic;
        ce              : in std_logic;
        fakeOutForXst   : out std_logic);
end xlclkprobe;
architecture behavior of xlclkprobe is
begin
   fakeOutForXst <= '0';
-- synopsys translate_off
   work.clock_pkg.int_clk <= clk;
-- synopsys translate_on
end behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
  generic (
    period: integer := 2;
    use_bufg: boolean := false
  );
  port (
    sysclk: in std_logic;
    sysclr: in std_logic;
    sysce: in std_logic;
    clk: out std_logic;
    clr: out std_logic;
    ce: out std_logic
  );
end xlclockdriver;
architecture behavior of xlclockdriver is
  component bufg
    port (
      i: in std_logic;
      o: out std_logic
    );
  end component;
  component synth_reg_w_init
    generic (
      width: integer;
      init_index: integer;
      init_value: bit_vector;
      latency: integer
    );
    port (
      i: in std_logic_vector(width - 1 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      o: out std_logic_vector(width - 1 downto 0)
    );
  end component;
  function size_of_uint(inp: integer; power_of_2: boolean)
    return integer
  is
    constant inp_vec: std_logic_vector(31 downto 0) :=
      integer_to_std_logic_vector(inp,32, xlUnsigned);
    variable result: integer;
  begin
    result := 32;
    for i in 0 to 31 loop
      if inp_vec(i) = '1' then
        result := i;
      end if;
    end loop;
    if power_of_2 then
      return result;
    else
      return result+1;
    end if;
  end;
  function is_power_of_2(inp: std_logic_vector)
    return boolean
  is
    constant width: integer := inp'length;
    variable vec: std_logic_vector(width - 1 downto 0);
    variable single_bit_set: boolean;
    variable more_than_one_bit_set: boolean;
    variable result: boolean;
  begin
    vec := inp;
    single_bit_set := false;
    more_than_one_bit_set := false;
    -- synopsys translate_off
    if (is_XorU(vec)) then
      return false;
    end if;
     -- synopsys translate_on
    if width > 0 then
      for i in 0 to width - 1 loop
        if vec(i) = '1' then
          if single_bit_set then
            more_than_one_bit_set := true;
          end if;
          single_bit_set := true;
        end if;
      end loop;
    end if;
    if (single_bit_set and not(more_than_one_bit_set)) then
      result := true;
    else
      result := false;
    end if;
    return result;
  end;
  constant period_floor: integer := max(2, period);
  constant power_of_2_counter: boolean :=
    is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
  constant cnt_width: integer :=
    size_of_uint(period_floor, power_of_2_counter);
  constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
    integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
  constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
    integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
  signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
  signal ce_vec, internal_ce: std_logic_vector(0 downto 0);
  signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
  clk <= sysclk;
  clr <= sysclr;
  cntr_gen: process(sysclk)
  begin
    if sysclk'event and sysclk = '1'  then
      if (sysce = '1') then
        if (cnt_clr_dly(0) = '1') then
          clk_num <= (others => '0');
        else
          clk_num <= clk_num + 1;
        end if;
    end if;
    end if;
  end process;
  clr_gen: process(clk_num, sysclr)
  begin
    if power_of_2_counter then
      cnt_clr(0) <= sysclr;
    else
      if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
          or sysclr = '1') then
        cnt_clr(0) <= '1';
      else
        cnt_clr(0) <= '0';
      end if;
    end if;
  end process;
  clr_reg: synth_reg_w_init
    generic map (
      width => 1,
      init_index => 0,
      init_value => b"0000",
      latency => 1
    )
    port map (
      i => cnt_clr,
      ce => sysce,
      clr => sysclr,
      clk => sysclk,
      o => cnt_clr_dly
    );
  non_pipelined_ce : if period = 2 generate
      ce_gen: process(clk_num)
      begin
          if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 then
              ce_vec(0) <= '1';
          else
              ce_vec(0) <= '0';
          end if;
      end process;
      ce_reg: synth_reg_w_init
          generic map (
              width => 1,
              init_index => 0,
              init_value => b"0000",
              latency => 1
              )
          port map (
              i => ce_vec,
              ce => sysce,
              clr => sysclr,
              clk => sysclk,
              o => internal_ce
              );
  end generate;
  pipelined_ce : if period > 2 generate
      ce_gen: process(clk_num)
      begin
          if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus2 then
              ce_vec(0) <= '1';
          else
              ce_vec(0) <= '0';
          end if;
      end process;
      ce_reg: synth_reg_w_init
          generic map (
              width => 1,
              init_index => 0,
              init_value => b"0000",
              latency => 2
              )
          port map (
              i => ce_vec,
              ce => sysce,
              clr => sysclr,
              clk => sysclk,
              o => internal_ce
              );
  end generate;
  use_bufg_true: if period > 1 and use_bufg generate
    ce_bufg_inst: bufg
      port map (
        i => internal_ce(0),
        o => ce
      );
  end generate;
  use_bufg_false: if period > 1 and not(use_bufg) generate
    ce <= internal_ce(0);
  end generate;
  generate_system_clk: if period = 1 generate
    ce <= sysce;
  end generate;
end architecture behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockgenerator is
    generic (ensure_clks_stable       : boolean := false;
             lcm_select               : integer := 0;
             frequency_mode           : string  := "low";
             clkdv_divide_generic     : real    := 2.0;
             clkdv_divide_attribute   : string  := "2.0";
             clkfx_multiply_generic   : integer := 4;
             clkfx_multiply_attribute : string  := "4";
             clkfx_divide_generic     : integer := 1;
             clkfx_divide_attribute   : string  := "1");
    port (clk   : in std_logic;
          rst   : in std_logic;
          clk0  : out std_logic;
          clk2x : out std_logic;
          clkfx : out std_logic;
          clkdv : out std_logic;
          lock  : out std_logic);
end xlclockgenerator;
architecture structural of xlclockgenerator is
   component bufg
      port(i: in std_logic;
           o: out std_logic);
   end component;
   component bufgmux
      port(i0 : in std_logic;
           i1 : in std_logic;
           s  : in std_logic;
           o  : out std_logic);
   end component;
   component dcm
      -- synopsys translate_off
      generic (clkout_phase_shift    : string := "fixed";
               dll_frequency_mode    : string := "low";
               duty_cycle_correction : boolean := true;
               clkdv_divide          : real := 2.0;
               clkfx_multiply        : integer := 4;
               clkfx_divide          : integer := 1);
      -- synopsys translate_on
      port (clkin    : in  std_logic;
            clkfb    : in  std_logic;
            dssen    : in  std_logic;
            psincdec : in  std_logic;
            psen     : in  std_logic;
            psclk    : in  std_logic;
            rst      : in  std_logic;
            clk0     : out std_logic;
            clk90    : out std_logic;
            clk180   : out std_logic;
            clk270   : out std_logic;
            clk2x    : out std_logic;
            clk2x180 : out std_logic;
            clkdv    : out std_logic;
            clkfx    : out std_logic;
            clkfx180 : out std_logic;
            locked   : out std_logic;
            psdone   : out std_logic;
            status   : out std_logic_vector(7 downto 0));
   end component;
   attribute dll_frequency_mode    : string;
   attribute duty_cycle_correction : string;
   attribute startup_wait          : string;
   attribute clkdv_divide          : string;
   attribute clkfx_multiply        : string;
   attribute clkfx_divide          : string;
   attribute duty_cycle_correction of dcm_comp1 : label is "true";
   attribute startup_wait of dcm_comp1          : label is "false";
   attribute dll_frequency_mode of dcm_comp1    : label is frequency_mode;
   attribute clkdv_divide of dcm_comp1   : label is clkdv_divide_attribute;
   attribute clkfx_multiply of dcm_comp1 : label is clkfx_multiply_attribute;
   attribute clkfx_divide of dcm_comp1   : label is clkfx_divide_attribute;
   component fdre
      port(q  : out   std_ulogic;
           d  : in    std_ulogic;
           c  : in    std_ulogic;
           r  : in    std_ulogic;
           ce : in    std_ulogic);
   end component;
   signal feedback    : std_logic;
   signal clklcm      : std_logic;
   signal clk0unbuf   : std_logic;
   signal clk0buf     : std_logic;
   signal clk2xunbuf  : std_logic;
   signal clkfxunbuf  : std_logic;
   signal clkdvunbuf  : std_logic;
   signal clkswitch   : std_logic;
   signal intlock     : std_logic;
begin
   dcm_comp1: dcm
      -- synopsys translate_off
      generic map (dll_frequency_mode => frequency_mode,
                   clkdv_divide       => clkdv_divide_generic,
                   clkfx_multiply     => clkfx_multiply_generic,
                   clkfx_divide       => clkfx_divide_generic)
      -- synopsys translate_on
      port map (clkin    => clk,
                clkfb    => feedback,
                dssen    => '0',
                psincdec => '0',
                psen     => '0',
                psclk    => '0',
                rst      => rst,
                clk0     => clk0unbuf,
                clk2x    => clk2xunbuf,
                clkfx    => clkfxunbuf,
                clkdv    => clkdvunbuf,
                locked   => intlock);
   bufgmux_clk0: bufgmux
      port map (i0 => '0',
                i1 => clk0unbuf,
                o  => clk0buf,
                s  => clkswitch);
   bufgmux_clk2x: bufgmux
      port map (i0 => '0',
                i1 => clk2xunbuf,
                o  => clk2x,
                s  => clkswitch);
   bufgmux_clkfx: bufgmux
      port map (i0 => '0',
                i1 => clkfxunbuf,
                o  => clkfx,
                s  => clkswitch);
   bufgmux_clkdv: bufgmux
      port map (i0 => '0',
                i1 => clkdvunbuf,
                o  => clkdv,
                s  => clkswitch);
   stability_req: if (ensure_clks_stable = true) generate
      mux_ctrl_reg: fdre
         port map (d  => intlock,
                   q  => clkswitch,
                   ce => '1',
                   c  => clklcm,
                   r  => rst);
      bufg_feedback: bufg
         port map(i => clk0unbuf,
                  o => feedback);
      lcm_is_clk0: if (lcm_select = 0) generate
         clklcm <= feedback;
      end generate;
      lcm_is_clkdv: if (lcm_select = 1) generate
         bufg_lcmclk: bufg
            port map(i => clkdvunbuf,
                     o => feedback);
      end generate;
   end generate;
   stability_not_req: if (ensure_clks_stable = false) generate
      feedback  <= clk0buf;
      clkswitch <= '1';
   end generate;
   lock <= intlock;
   clk0 <= clk0buf;
end architecture structural;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlsl2slv is
  generic (
    dout_width: integer := 1;
    dout_bin_pt: integer := 0;
    dout_arith: integer := xlUnsigned
  );
  port (
    din: in std_logic;
    dout: out std_logic_vector(dout_width - 1 downto 0)
  );
end xlsl2slv;
architecture behavior of xlsl2slv is
begin
    dout(0) <= din;
end behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslv2sl is
  generic (
    din_width: integer := 1;
    din_bin_pt: integer := 0;
    din_arith: integer := xlUnsigned
  );
  port (
    din: in std_logic_vector(din_width - 1 downto 0);
    dout: out std_logic
  );
end xlslv2sl;
architecture behavior of xlslv2sl is
begin
    dout <= din(0);
end behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity synth_addsub is
  generic (
    arith_type : integer;
    a_width    : integer;
    b_width    : integer;
    s_width    : integer;
    mode       : integer;
    use_cin    : integer;
    use_bin    : integer;
    latency    : integer);
  port (
    a   : in std_logic_vector(a_width-1 downto 0);
    b   : in std_logic_vector(b_width-1 downto 0);
    cin  : in std_logic_vector(0 downto 0) := "0";
    ce  : in std_logic;
    clr : in std_logic;
    clk : in std_logic;
    cout : out std_logic_vector(0 downto 0) := (others => '0');
    s   : out std_logic_vector(s_width-1 downto 0));
end synth_addsub;
architecture behavior of synth_addsub is
  component synth_reg
    generic (
      width   : integer := 16;
      latency : integer := 5);
    port (
      i    : in std_logic_vector(width-1 downto 0);
      ce   : in std_logic;
      clr  : in std_logic;
      clk  : in std_logic;
      o    : out std_logic_vector(width-1 downto 0));
  end component;
  signal result : std_logic_vector(s_width-1 downto 0);
  signal cout_temp : std_logic_vector(0 downto 0) := "0";
  signal internal_cin : std_logic_vector(0 downto 0);
  signal cin_sub : std_logic_vector(0 downto 0);
begin
 cin_test: if  (use_cin = 1 or use_bin = 1)  generate
    internal_cin <= cin;
    cin_sub <= not(cin);
  end generate cin_test;
 cin_test2: if  (use_cin = 0 and use_bin = 0)  generate
    internal_cin(0) <= '0';
    cin_sub(0) <= '0';
  end generate cin_test2;
  addsub_process :  process (a, b, internal_cin, cin_sub)
  begin
    if (mode = xlAddMode) then
      if (arith_type = xlUnsigned) then
        result <= unsigned_to_std_logic_vector( std_logic_vector_to_unsigned(a) +
                                std_logic_vector_to_unsigned(b) +
                                std_logic_vector_to_unsigned(internal_cin));
      else
        result <= signed_to_std_logic_vector( std_logic_vector_to_signed(a) +
                                std_logic_vector_to_signed(b) +
                                std_logic_vector_to_signed(internal_cin));
      end if;
    else
      if (arith_type = xlUnsigned) then
        result <= unsigned_to_std_logic_vector( std_logic_vector_to_unsigned(a) -
                                std_logic_vector_to_unsigned(b) -
                                std_logic_vector_to_unsigned(cin_sub));
      else
        result <= signed_to_std_logic_vector( std_logic_vector_to_signed(a) -
                               std_logic_vector_to_signed(b) -
                               std_logic_vector_to_signed(cin_sub));
      end if;
    end if;
  end process addsub_process;
  cout_process :  process (result, internal_cin,a,b, cin_sub)
  begin
    if(mode = xlAddMode) then
      cout_temp(0) <= result(s_width - 1);
    else
      if (arith_type = xlUnsigned) then
        if (std_logic_vector_to_signed(b) <= std_logic_vector_to_signed(unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(a) - std_logic_vector_to_unsigned(cin_sub)))) then
                cout_temp(0) <= '1';
        else
                cout_temp(0) <= '0';
        end if;
      else
        if (std_logic_vector_to_signed(b) <= (std_logic_vector_to_signed(a) -
                        std_logic_vector_to_signed(cin_sub))) then
                cout_temp(0) <= '1';
        else
                cout_temp(0) <= '0';
        end if;
      end if;
    end if;
  end process cout_process;
  latency_test : if (latency > 0) generate
    reg : synth_reg
       generic map (
         width   => s_width,
         latency => latency)
       port map (
         i   => result,
         ce  => ce,
         clr => clr,
         clk => clk,
         o   => s);
  end generate;
  cout_test : if (latency > 0) generate
    cout_reg : synth_reg
       generic map (
         width   => 1,
         latency => latency)
       port map (
         i   => cout_temp,
         ce  => ce,
         clr => clr,
         clk => clk,
         o   => cout);
  end generate;
  latency0 : if (latency = 0) generate
    s <= result;
    cout <= cout_temp;
  end generate latency0;
end architecture behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity test1_addsub1 is
  generic (
    core_name0: string := "";
    a_width: integer := 16;
    a_bin_pt: integer := 4;
    a_arith: integer := xlUnsigned;
    c_in_width: integer := 16;
    c_in_bin_pt: integer := 4;
    c_in_arith: integer := xlUnsigned;
    c_out_width: integer := 16;
    c_out_bin_pt: integer := 4;
    c_out_arith: integer := xlUnsigned;
    b_width: integer := 8;
    b_bin_pt: integer := 2;
    b_arith: integer := xlUnsigned;
    s_width: integer := 17;
    s_bin_pt: integer := 4;
    s_arith: integer := xlUnsigned;
    rst_width: integer := 1;
    rst_bin_pt: integer := 0;
    rst_arith: integer := xlUnsigned;
    en_width: integer := 1;
    en_bin_pt: integer := 0;
    en_arith: integer := xlUnsigned;
    full_s_width: integer := 17;
    full_s_arith: integer := xlUnsigned;
    mode: integer := xlAddMode;
    extra_registers: integer := 0;
    latency: integer := 0;
    quantization: integer := xlTruncate;
    overflow: integer := xlWrap;
    c_a_width: integer := 16;
    c_b_width: integer := 8;
    c_a_type: integer := 1;
    c_b_type: integer := 1;
    c_add_mode: integer := 0;
    c_has_s: integer := 1;
    c_has_q: integer := 0;
    c_has_sclr: integer := 0;
    c_has_ce: integer := 0;
    c_latency: integer := 0;
    c_output_width: integer := 17;
    c_enable_rlocs: integer := 1;
    c_has_c_in  : integer := 0;
    c_has_b_in  : integer := 0;
    c_has_c_out : integer := 0;
    c_has_q_c_out : integer := 0;
    c_has_b_out : integer := 0;
    c_has_q_b_out : integer := 0;
    c_has_q_ovfl : integer := 0;
    c_has_ovfl : integer := 0;
    core: boolean := false
  );
  port (
    a: in std_logic_vector(a_width - 1 downto 0);
    b: in std_logic_vector(b_width - 1 downto 0);
    c_in : in std_logic_vector (0 downto 0) := "0";
    ce: in std_logic;
    clr: in std_logic;
    clk: in std_logic;
    rst: in std_logic_vector(rst_width - 1 downto 0);
    en: in std_logic_vector(en_width - 1 downto 0);
    c_out : out std_logic_vector (0 downto 0);
    s: out std_logic_vector(s_width - 1 downto 0)
  );
end test1_addsub1;
architecture behavior of test1_addsub1 is
  component synth_addsub
    generic (
      arith_type: integer;
      a_width: integer;
      b_width: integer;
      s_width: integer;
      mode: integer;
      use_cin : integer;
      use_bin : integer;
      latency: integer
    );
    port (
      a: in std_logic_vector(a_width - 1 downto 0);
      b: in std_logic_vector(b_width - 1 downto 0);
      cin : in std_logic_vector(0 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      cout : out std_logic_vector(0 downto 0);
      s: out std_logic_vector(s_width - 1 downto 0)
    );
  end component;
  component synth_reg
    generic (
      width: integer := 16;
      latency: integer := 5
    );
    port (
      i: in std_logic_vector(width - 1 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      o: out std_logic_vector(width - 1 downto 0)
    );
  end component;
  function format_input(inp: std_logic_vector; old_width, delta, new_arith,
                        new_width: integer)
    return std_logic_vector
  is
    variable vec: std_logic_vector(old_width-1 downto 0);
    variable padded_inp: std_logic_vector((old_width + delta)-1  downto 0);
    variable result: std_logic_vector(new_width-1 downto 0);
  begin
    vec := inp;
    if delta > 0 then
      padded_inp := pad_LSB(vec, old_width+delta);
      result := extend_MSB(padded_inp, new_width, new_arith);
    else
      result := extend_MSB(vec, new_width, new_arith);
    end if;
    return result;
  end;
  constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
  constant full_a_width: integer := full_s_width;
  constant full_b_width: integer := full_s_width;
  signal full_a: std_logic_vector(full_a_width - 1 downto 0);
  signal full_b: std_logic_vector(full_b_width - 1 downto 0);
  signal full_s: std_logic_vector(full_s_width - 1 downto 0);
  signal core_s: std_logic_vector(full_s_width - 1 downto 0);
  signal conv_s: std_logic_vector(s_width - 1 downto 0);
  signal temp_cout : std_logic;
  -- synopsys translate_off
  signal real_a, real_b, real_s: real;
  -- synopsys translate_on
  signal internal_clr: std_logic;
  signal internal_ce: std_logic;
  signal extra_reg_ce: std_logic;
  signal override: std_logic;
  signal logic1: std_logic_vector(0 downto 0);
  component adder_subtracter_spartan2_6_0_438ebd1a25415d4b
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_438ebd1a25415d4b:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_438ebd1a25415d4b:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_438ebd1a25415d4b:
    component  is "black_box";
  component adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0:
    component  is "black_box";
  component adder_subtracter_spartan2_6_0_86c498140491d6df
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_86c498140491d6df:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_86c498140491d6df:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_86c498140491d6df:
    component  is "black_box";
  component adder_subtracter_spartan2_6_0_59d46904916909df
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_59d46904916909df:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_59d46904916909df:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_59d46904916909df:
    component  is "black_box";
  component adder_subtracter_spartan2_6_0_350b80de9e916006
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_350b80de9e916006:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_350b80de9e916006:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_350b80de9e916006:
    component  is "black_box";
  component adder_subtracter_spartan2_6_0_bfeb857b6aedd324
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_bfeb857b6aedd324:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_bfeb857b6aedd324:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_bfeb857b6aedd324:
    component  is "black_box";
begin
  internal_clr <= (clr or (rst(0))) and ce;
  internal_ce <= ce and en(0);
  logic1(0) <= '1';
  addsub_process: process(a, b, core_s)
  begin
    full_a <= format_input(a, a_width, b_bin_pt - a_bin_pt, a_arith,
                           full_a_width);
    full_b <= format_input(b, b_width, a_bin_pt - b_bin_pt, b_arith,
                           full_b_width);
    conv_s <= convert_type(core_s, full_s_width, full_s_bin_pt, full_s_arith,
                           s_width, s_bin_pt, s_arith, quantization, overflow);
    -- synopsys translate_off
    -- synopsys translate_on
  end process addsub_process;
  synth_behavioral_inst: if not(core) generate
    synth_addsub_inst: synth_addsub
      generic map (
        arith_type => full_s_arith,
        a_width => full_a_width,
        b_width => full_b_width,
        s_width => full_s_width,
        mode => mode,
        use_cin => c_has_c_in,
        use_bin => c_has_b_in,
        latency => latency
      )
      port map (
        a => full_a,
        b => full_b,
        cin => c_in,
        ce => internal_ce,
        clr => internal_clr,
        clk => clk,
        cout(0) => temp_cout,
        s => core_s
      );
  end generate;
  comp0: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_438ebd1a25415d4b")) generate
    core_instance0: adder_subtracter_spartan2_6_0_438ebd1a25415d4b
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp1: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_438ebd1a25415d4b")) generate
    core_instance1: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  comp2: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0")) generate
    core_instance2: adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp3: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0")) generate
    core_instance3: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  comp4: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df")) generate
    core_instance4: adder_subtracter_spartan2_6_0_86c498140491d6df
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp5: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df")) generate
    core_instance5: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  comp6: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_59d46904916909df")) generate
    core_instance6: adder_subtracter_spartan2_6_0_59d46904916909df
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp7: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_59d46904916909df")) generate
    core_instance7: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  comp8: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_350b80de9e916006")) generate
    core_instance8: adder_subtracter_spartan2_6_0_350b80de9e916006
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp9: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_350b80de9e916006")) generate
    core_instance9: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  comp10: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_bfeb857b6aedd324")) generate
    core_instance10: adder_subtracter_spartan2_6_0_bfeb857b6aedd324
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp11: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_bfeb857b6aedd324")) generate
    core_instance11: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  latency_test: if (core) and (extra_registers > 0) generate
      override_test: if (c_latency > 1) generate
       override_pipe: synth_reg
          generic map (
            width => 1,
            latency => c_latency)
          port map (
            i => logic1,
            ce => internal_ce,
            clr => internal_clr,
            clk => clk,
            o(0) => override);
       extra_reg_ce <= ce and en(0) and override;
      end generate override_test;
      no_override: if (c_latency = 0) or (c_latency = 1) generate
       extra_reg_ce <= ce and en(0);
      end generate no_override;
      extra_reg: synth_reg
        generic map (
          width => s_width,
          latency => extra_registers
        )
        port map (
          i => conv_s,
          ce => extra_reg_ce,
          clr => internal_clr,
          clk => clk,
          o => s
        );
      cout_test : if((c_has_c_out = 1) or
                (c_has_b_out = 1) or
                (c_has_q_c_out = 1) or
                (c_has_q_b_out = 1)) generate
      c_out_extra_reg: synth_reg
        generic map (
          width => 1,
          latency => extra_registers
        )
        port map (
          i(0) => temp_cout,
          ce => extra_reg_ce,
          clr => internal_clr,
          clk => clk,
          o => c_out
        );
      end generate cout_test;
  end generate;
  latency_s: if  (not(core) or (latency = 0) or (extra_registers = 0))  generate
    s <= conv_s;
  end generate latency_s;
  latency0: if ( (not(core) or (latency = 0) or (extra_registers = 0)) and
                ((c_has_b_out = 1) or
                (c_has_q_c_out = 1) or
                (c_has_c_out = 1) or
                (c_has_q_b_out = 1)))  generate
    c_out(0) <= temp_cout;
  end generate latency0;
  tie_dangling_cout: if ((c_has_c_out = 0) and
                        (c_has_b_out = 0) and
                        (c_has_q_c_out = 0) and
                        (c_has_q_b_out = 0)) generate
    c_out <= "0";
  end generate tie_dangling_cout;
end architecture behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity test1_cmult3 is
  generic (
    core_name0: string := "";
    a_width: integer := 4;
    a_bin_pt: integer := 2;
    a_arith: integer := xlSigned;
    b_width: integer := 4;
    b_bin_pt: integer := 2;
    b_arith: integer := xlSigned;
    p_width: integer := 8;
    p_bin_pt: integer := 2;
    p_arith: integer := xlSigned;
    rst_width: integer := 1;
    rst_bin_pt: integer := 0;
    rst_arith: integer := xlUnsigned;
    en_width: integer := 1;
    en_bin_pt: integer := 0;
    en_arith: integer := xlUnsigned;
    latency: integer := 1;
    multsign: integer := xlSigned;
    quantization: integer := xlTruncate;
    overflow: integer := xlWrap;
    extra_registers: integer := 0;
    c_a_width: integer := 7;
    c_b_width: integer := 7;
    c_a_type: integer := 0;
    c_b_type: integer := 0;
    c_type: integer := 0;
    c_pipelined: integer := 1;
    bram_addr_width: integer := 8;
    c_baat: integer := 4;
    c_mult_type: integer := 0;
    c_has_q: integer := 1;
    c_has_nd: integer := 0;
    c_has_o: integer := 0;
    oversample: integer := 1;
    const_bin_pt: integer := 1;
    c_reg_inputs: integer := 0;
    c_enable_rlocs: integer := 1;
                -- synopsys translate_off
    c_b_value: string := "0";
                -- synopsys translate_on
    c_b_value_hi: integer := 0;
    c_b_value_low: integer := 0;
    c_has_b: integer := 0;
    c_has_loadb: integer := 0;
    c_b_constant: integer := 0;
    c_mem_type: integer := 0;
    c_output_width: integer := 16;
    c_output_hold: integer := 0
  );
  port (
    a: in std_logic_vector(a_width - 1 downto 0);
    ce: in std_logic;
    clr: in std_logic;
    clk: in std_logic;
    core_ce: in std_logic:= '0';
    core_clr: in std_logic:= '0';
    core_clk: in std_logic:= '0';
    rst: in std_logic_vector(rst_width - 1 downto 0);
    en: in std_logic_vector(en_width - 1 downto 0);
    p: out std_logic_vector(p_width - 1 downto 0)
  );
end test1_cmult3;
architecture behavior of test1_cmult3 is
  component synth_reg
    generic (
      width: integer := 16;
      latency: integer := 5
    );
    port (
      i: in std_logic_vector(width - 1 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      o: out std_logic_vector(width - 1 downto 0)
    );
  end component;
  signal tmp_a: std_logic_vector(c_a_width - 1 downto 0);
  signal tmp_p: std_logic_vector(c_output_width - 1 downto 0);
  signal conv_p: std_logic_vector(p_width - 1 downto 0);
  -- synopsys translate_off
  signal real_a, real_p: real;
  -- synopsys translate_on
  signal nd: std_logic;
  signal internal_ce: std_logic;
  signal internal_clr: std_logic;
  signal internal_core_ce: std_logic;
  component multiplier_spartan2_6_0_c898a6c13135c6d0
    port (
      o: out std_logic_vector(c_output_width - 1 downto 0);
      a: in std_logic_vector(c_a_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of multiplier_spartan2_6_0_c898a6c13135c6d0:
    component is true;
  attribute fpga_dont_touch of multiplier_spartan2_6_0_c898a6c13135c6d0:
    component is "true";
  attribute box_type of multiplier_spartan2_6_0_c898a6c13135c6d0:
    component  is "black_box";
  component multiplier_spartan2_6_0_7d52cda8234e03c2
    port (
      o: out std_logic_vector(c_output_width - 1 downto 0);
      a: in std_logic_vector(c_a_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of multiplier_spartan2_6_0_7d52cda8234e03c2:
    component is true;
  attribute fpga_dont_touch of multiplier_spartan2_6_0_7d52cda8234e03c2:
    component is "true";
  attribute box_type of multiplier_spartan2_6_0_7d52cda8234e03c2:
    component  is "black_box";
  component multiplier_spartan2_6_0_13a3d468139afdbd
    port (
      o: out std_logic_vector(c_output_width - 1 downto 0);
      a: in std_logic_vector(c_a_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of multiplier_spartan2_6_0_13a3d468139afdbd:
    component is true;
  attribute fpga_dont_touch of multiplier_spartan2_6_0_13a3d468139afdbd:
    component is "true";
  attribute box_type of multiplier_spartan2_6_0_13a3d468139afdbd:
    component  is "black_box";
  component multiplier_spartan2_6_0_6f13cc9ee672d655
    port (
      o: out std_logic_vector(c_output_width - 1 downto 0);
      a: in std_logic_vector(c_a_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of multiplier_spartan2_6_0_6f13cc9ee672d655:
    component is true;
  attribute fpga_dont_touch of multiplier_spartan2_6_0_6f13cc9ee672d655:
    component is "true";
  attribute box_type of multiplier_spartan2_6_0_6f13cc9ee672d655:
    component  is "black_box";
begin
  -- synopsys translate_off
  -- synopsys translate_on
  input_process: process(a)
    variable tmp_p_bin_pt, tmp_p_arith: integer;
  begin
    tmp_a <= zero_ext(a, c_a_width);
  end process;
  output_process: process(tmp_p)
  begin
    conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign,
                           p_width, p_bin_pt, p_arith, quantization, overflow);
  end process;
  internal_ce <= ce and en(0);
  internal_core_ce <= core_ce and en(0);
  internal_clr <= (clr or rst(0)) and ce;
  nd <= internal_ce;
  comp0: if (not simulating and
             (core_name0 = "multiplier_spartan2_6_0_c898a6c13135c6d0")) generate
    core_instance0: multiplier_spartan2_6_0_c898a6c13135c6d0
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_off
  comp1: if (simulating and
             (core_name0 = "multiplier_spartan2_6_0_c898a6c13135c6d0")) generate
    core_instance1: entity XilinxCoreLib.mult_gen_v6_0(behavioral)
      generic map (
        c_baat => c_baat,
        c_a_type => c_a_type,
        c_sync_enable => 1,
        c_mult_type => c_mult_type,
        c_b_type => c_b_type,
        c_use_luts => 1,
        c_b_width => c_b_width,
        c_stack_adders => 1,
        c_has_rfd => c_has_nd,
        c_has_q => c_has_q,
        c_has_load_done => 0,
        c_has_o => c_has_o,
        c_has_a_signed => 0,
        c_has_b => c_has_b,
        c_has_sclr => c_has_q,
        c_mem_init_prefix => "mem",
        c_b_value => c_b_value,
        c_has_loadb => c_has_loadb,
        c_mem_type => c_mem_type,
        c_out_width => c_output_width,
        c_a_width =>c_a_width,
        c_b_constant => c_b_constant,
        c_reg_a_b_inputs => c_reg_inputs,
        c_has_nd => c_has_nd,
        c_output_hold => c_output_hold,
        c_has_ce => c_has_q,
        c_has_swapb => 0,
        c_has_aclr => 0,
        c_sqm_type => 0,
        c_pipeline => c_pipelined,
        c_enable_rlocs => c_enable_rlocs,
        bram_addr_width => bram_addr_width,
        c_has_rdy => c_has_nd
      )
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_on
  comp2: if (not simulating and
             (core_name0 = "multiplier_spartan2_6_0_7d52cda8234e03c2")) generate
    core_instance2: multiplier_spartan2_6_0_7d52cda8234e03c2
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_off
  comp3: if (simulating and
             (core_name0 = "multiplier_spartan2_6_0_7d52cda8234e03c2")) generate
    core_instance3: entity XilinxCoreLib.mult_gen_v6_0(behavioral)
      generic map (
        c_baat => c_baat,
        c_a_type => c_a_type,
        c_sync_enable => 1,
        c_mult_type => c_mult_type,
        c_b_type => c_b_type,
        c_use_luts => 1,
        c_b_width => c_b_width,
        c_stack_adders => 1,
        c_has_rfd => c_has_nd,
        c_has_q => c_has_q,
        c_has_load_done => 0,
        c_has_o => c_has_o,
        c_has_a_signed => 0,
        c_has_b => c_has_b,
        c_has_sclr => c_has_q,
        c_mem_init_prefix => "mem",
        c_b_value => c_b_value,
        c_has_loadb => c_has_loadb,
        c_mem_type => c_mem_type,
        c_out_width => c_output_width,
        c_a_width =>c_a_width,
        c_b_constant => c_b_constant,
        c_reg_a_b_inputs => c_reg_inputs,
        c_has_nd => c_has_nd,
        c_output_hold => c_output_hold,
        c_has_ce => c_has_q,
        c_has_swapb => 0,
        c_has_aclr => 0,
        c_sqm_type => 0,
        c_pipeline => c_pipelined,
        c_enable_rlocs => c_enable_rlocs,
        bram_addr_width => bram_addr_width,
        c_has_rdy => c_has_nd
      )
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_on
  comp4: if (not simulating and
             (core_name0 = "multiplier_spartan2_6_0_13a3d468139afdbd")) generate
    core_instance4: multiplier_spartan2_6_0_13a3d468139afdbd
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_off
  comp5: if (simulating and
             (core_name0 = "multiplier_spartan2_6_0_13a3d468139afdbd")) generate
    core_instance5: entity XilinxCoreLib.mult_gen_v6_0(behavioral)
      generic map (
        c_baat => c_baat,
        c_a_type => c_a_type,
        c_sync_enable => 1,
        c_mult_type => c_mult_type,
        c_b_type => c_b_type,
        c_use_luts => 1,
        c_b_width => c_b_width,
        c_stack_adders => 1,
        c_has_rfd => c_has_nd,
        c_has_q => c_has_q,
        c_has_load_done => 0,
        c_has_o => c_has_o,
        c_has_a_signed => 0,
        c_has_b => c_has_b,
        c_has_sclr => c_has_q,
        c_mem_init_prefix => "mem",
        c_b_value => c_b_value,
        c_has_loadb => c_has_loadb,
        c_mem_type => c_mem_type,
        c_out_width => c_output_width,
        c_a_width =>c_a_width,
        c_b_constant => c_b_constant,
        c_reg_a_b_inputs => c_reg_inputs,
        c_has_nd => c_has_nd,
        c_output_hold => c_output_hold,
        c_has_ce => c_has_q,
        c_has_swapb => 0,
        c_has_aclr => 0,
        c_sqm_type => 0,
        c_pipeline => c_pipelined,
        c_enable_rlocs => c_enable_rlocs,
        bram_addr_width => bram_addr_width,
        c_has_rdy => c_has_nd
      )
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_on
  comp6: if (not simulating and
             (core_name0 = "multiplier_spartan2_6_0_6f13cc9ee672d655")) generate
    core_instance6: multiplier_spartan2_6_0_6f13cc9ee672d655
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_off
  comp7: if (simulating and
             (core_name0 = "multiplier_spartan2_6_0_6f13cc9ee672d655")) generate
    core_instance7: entity XilinxCoreLib.mult_gen_v6_0(behavioral)
      generic map (
        c_baat => c_baat,
        c_a_type => c_a_type,
        c_sync_enable => 1,
        c_mult_type => c_mult_type,
        c_b_type => c_b_type,
        c_use_luts => 1,
        c_b_width => c_b_width,
        c_stack_adders => 1,
        c_has_rfd => c_has_nd,
        c_has_q => c_has_q,
        c_has_load_done => 0,
        c_has_o => c_has_o,
        c_has_a_signed => 0,
        c_has_b => c_has_b,
        c_has_sclr => c_has_q,
        c_mem_init_prefix => "mem",
        c_b_value => c_b_value,
        c_has_loadb => c_has_loadb,
        c_mem_type => c_mem_type,
        c_out_width => c_output_width,
        c_a_width =>c_a_width,
        c_b_constant => c_b_constant,
        c_reg_a_b_inputs => c_reg_inputs,
        c_has_nd => c_has_nd,
        c_output_hold => c_output_hold,
        c_has_ce => c_has_q,
        c_has_swapb => 0,
        c_has_aclr => 0,
        c_sqm_type => 0,
        c_pipeline => c_pipelined,
        c_enable_rlocs => c_enable_rlocs,
        bram_addr_width => bram_addr_width,
        c_has_rdy => c_has_nd
      )
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_on
  latency_gt_0: if (extra_registers > 0) and
                    not ((c_b_value_low = 0) and (c_b_value_hi = 0))
  generate
    reg: synth_reg
      generic map (
        width => p_width,
        latency => extra_registers
      )
      port map (
        i => conv_p,
        ce => internal_ce,
        clr => internal_clr,
        clk => clk,
        o => p
      );
  end generate;
  latency0: if ((latency = 0) or (extra_registers = 0)) and
                not((c_b_value_low = 0) and (c_b_value_hi = 0))
  generate
    p <= conv_p;
  end generate latency0;
  zero_constant: if (c_b_value_low = 0)and (c_b_value_hi = 0)
  generate
    p <= integer_to_std_logic_vector(0,p_width,p_arith);
  end generate zero_constant;
end architecture behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xldelay is
   generic(d_width    : integer := 5;
           d_bin_pt   : integer := 2;
           d_arith    : integer := xlUnsigned;
           q_width    : integer := 5;
           q_bin_pt   : integer := 2;
           q_arith    : integer := xlUnsigned;
           rst_width  : integer := 1;
           rst_bin_pt : integer := 0;
           en_width   : integer := 5;
           en_bin_pt  : integer := 2;
           en_arith   : integer := xlUnsigned;
           rst_arith  : integer := xlUnsigned;
           latency    : integer := 10;
           reg_retiming: boolean := false);
   port(d       : in std_logic_vector (d_width-1 downto 0);
        ce      : in std_logic;
        clr     : in std_logic;
        clk     : in std_logic;
        rst     : in std_logic_vector (rst_width-1 downto 0);
        en      : in std_logic_vector (en_width-1 downto 0);
        q       : out std_logic_vector (q_width-1 downto 0));
end xldelay;
architecture behavior of xldelay is
   component synth_reg
      generic (width       : integer;
               latency     : integer);
      port (i           : in std_logic_vector(width-1 downto 0);
            ce      : in std_logic;
            clr     : in std_logic;
            clk     : in std_logic;
            o       : out std_logic_vector(width-1 downto 0));
   end component;
   component synth_reg_reg
      generic (width       : integer;
               latency     : integer);
      port (i           : in std_logic_vector(width-1 downto 0);
            ce      : in std_logic;
            clr     : in std_logic;
            clk     : in std_logic;
            o       : out std_logic_vector(width-1 downto 0));
   end component;
   signal internal_ce  : std_logic;
   signal internal_clr : std_logic;
begin
   internal_ce  <= ce and (en(0));
   internal_clr <= (clr or (rst(0))) and ce;
   srl_delay: if (not reg_retiming) or (latency<1) generate
     synth_reg_srl_inst : synth_reg
       generic map (
         width   => d_width,
         latency => latency)
       port map (
         i   => d,
         ce  => internal_ce,
         clr => internal_clr,
         clk => clk,
         o   => q);
   end generate srl_delay;
   reg_delay: if reg_retiming and (latency>=1) generate
     synth_reg_reg_inst : synth_reg_reg
       generic map (
         width   => d_width,
         latency => latency)
       port map (
         i   => d,
         ce  => internal_ce,
         clr => internal_clr,
         clk => clk,
         o   => q);
   end generate reg_delay;
end architecture behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2005 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2005 Xilinx, Inc. 
-- All rights reserved.
--------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;

entity test1 is
  port (
    ce_sg: in std_logic;
    clk_sg: in std_logic;
    gateway_in1: in std_logic_vector(15 downto 0);
    gateway_out: out std_logic_vector(19 downto 0)
  );
end test1;

architecture structural of test1 is
  signal ce_sg_x_0: std_logic;
  signal clk_sg_x_0: std_logic;
  signal dout: std_logic_vector(0 downto 0);
  signal dout_x_0: std_logic_vector(0 downto 0);
  signal dout_x_1: std_logic_vector(0 downto 0);
  signal dout_x_10: std_logic_vector(0 downto 0);
  signal dout_x_11: std_logic_vector(0 downto 0);
  signal dout_x_12: std_logic_vector(0 downto 0);
  signal dout_x_13: std_logic_vector(0 downto 0);
  signal dout_x_14: std_logic_vector(0 downto 0);
  signal dout_x_15: std_logic_vector(0 downto 0);
  signal dout_x_16: std_logic_vector(0 downto 0);
  signal dout_x_17: std_logic_vector(0 downto 0);
  signal dout_x_18: std_logic_vector(0 downto 0);
  signal dout_x_19: std_logic_vector(0 downto 0);
  signal dout_x_2: std_logic_vector(0 downto 0);
  signal dout_x_20: std_logic_vector(0 downto 0);
  signal dout_x_21: std_logic_vector(0 downto 0);
  signal dout_x_22: std_logic_vector(0 downto 0);
  signal dout_x_23: std_logic_vector(0 downto 0);
  signal dout_x_24: std_logic_vector(0 downto 0);
  signal dout_x_3: std_logic_vector(0 downto 0);
  signal dout_x_4: std_logic_vector(0 downto 0);
  signal dout_x_5: std_logic_vector(0 downto 0);
  signal dout_x_6: std_logic_vector(0 downto 0);
  signal dout_x_7: std_logic_vector(0 downto 0);
  signal dout_x_8: std_logic_vector(0 downto 0);
  signal dout_x_9: std_logic_vector(0 downto 0);
  signal gateway_in1_x_0: std_logic_vector(15 downto 0);
  signal p: std_logic_vector(31 downto 0);
  signal p_x_0: std_logic_vector(34 downto 0);
  signal p_x_1: std_logic_vector(33 downto 0);
  signal p_x_2: std_logic_vector(31 downto 0);
  signal q: std_logic_vector(15 downto 0);
  signal q_x_0: std_logic_vector(19 downto 0);
  signal q_x_1: std_logic_vector(15 downto 0);
  signal s: std_logic_vector(15 downto 0);
  signal s_x_0: std_logic_vector(16 downto 0);
  signal s_x_1: std_logic_vector(15 downto 0);
  signal s_x_2: std_logic_vector(18 downto 0);
  signal s_x_3: std_logic_vector(17 downto 0);
  signal s_x_4: std_logic_vector(19 downto 0);

begin
  ce_sg_x_0 <= ce_sg;
  clk_sg_x_0 <= clk_sg;
  gateway_in1_x_0 <= gateway_in1;
  gateway_out <= s_x_4;

  addsub1: entity work.test1_addsub1
    generic map (
      a_width => 16,
      a_arith => xlSigned,
      a_bin_pt => 8,
      b_width => 32,
      b_arith => xlSigned,
      b_bin_pt => 16,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 16,
      s_arith => xlSigned,
      s_bin_pt => 8,
      core_name0 => "adder_subtracter_spartan2_6_0_438ebd1a25415d4b",
      c_a_type => 0,
      c_a_width => 33,
      c_add_mode => 1,
      c_b_type => 0,
      c_b_width => 33,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 33,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 33,
      latency => 0,
      mode => 2,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => q_x_1,
      b => p,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout,
      rst => dout_x_0,
      s => s
    );
  addsub2: entity work.test1_addsub1
    generic map (
      a_width => 16,
      a_arith => xlSigned,
      a_bin_pt => 8,
      b_width => 16,
      b_arith => xlSigned,
      b_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 17,
      s_arith => xlSigned,
      s_bin_pt => 8,
      core_name0 => "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0",
      c_a_type => 0,
      c_a_width => 17,
      c_add_mode => 0,
      c_b_type => 0,
      c_b_width => 17,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 17,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 17,
      latency => 0,
      mode => 1,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => s,
      b => gateway_in1_x_0,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_1,
      rst => dout_x_12,
      s => s_x_0
    );
  addsub3: entity work.test1_addsub1
    generic map (
      a_width => 16,
      a_arith => xlSigned,
      a_bin_pt => 8,
      b_width => 16,
      b_arith => xlSigned,
      b_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 16,
      s_arith => xlSigned,
      s_bin_pt => 8,
      core_name0 => "adder_subtracter_spartan2_6_0_86c498140491d6df",
      c_a_type => 0,
      c_a_width => 17,
      c_add_mode => 1,
      c_b_type => 0,
      c_b_width => 17,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 17,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 17,
      latency => 0,
      mode => 2,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => gateway_in1_x_0,
      b => q,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_18,
      rst => dout_x_19,
      s => s_x_1
    );
  addsub4: entity work.test1_addsub1
    generic map (
      a_width => 18,
      a_arith => xlSigned,
      a_bin_pt => 8,
      b_width => 32,
      b_arith => xlSigned,
      b_bin_pt => 15,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 19,
      s_arith => xlSigned,
      s_bin_pt => 8,
      core_name0 => "adder_subtracter_spartan2_6_0_59d46904916909df",
      c_a_type => 0,
      c_a_width => 33,
      c_add_mode => 0,
      c_b_type => 0,
      c_b_width => 33,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 33,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 33,
      latency => 0,
      mode => 1,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => s_x_3,
      b => p_x_2,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_20,
      rst => dout_x_21,
      s => s_x_2
    );
  addsub5: entity work.test1_addsub1
    generic map (
      a_width => 35,
      a_arith => xlSigned,
      a_bin_pt => 16,
      b_width => 34,
      b_arith => xlSigned,
      b_bin_pt => 22,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 18,
      s_arith => xlSigned,
      s_bin_pt => 8,
      core_name0 => "adder_subtracter_spartan2_6_0_350b80de9e916006",
      c_a_type => 0,
      c_a_width => 42,
      c_add_mode => 0,
      c_b_type => 0,
      c_b_width => 42,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 42,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 42,
      latency => 0,
      mode => 1,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => p_x_0,
      b => p_x_1,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_22,
      rst => dout_x_23,
      s => s_x_3
    );
  addsub6: entity work.test1_addsub1
    generic map (
      a_width => 19,
      a_arith => xlSigned,
      a_bin_pt => 8,
      b_width => 20,
      b_arith => xlSigned,
      b_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 20,
      s_arith => xlSigned,
      s_bin_pt => 8,
      core_name0 => "adder_subtracter_spartan2_6_0_bfeb857b6aedd324",
      c_a_type => 0,
      c_a_width => 21,
      c_add_mode => 0,
      c_b_type => 0,
      c_b_width => 21,
      c_enable_rlocs => 0,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 21,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 21,
      latency => 0,
      mode => 1,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => s_x_2,
      b => q_x_0,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_24,
      rst => dout_x_2,
      s => s_x_4
    );
  cmult3: entity work.test1_cmult3
    generic map (
-- synopsys translate_off
      c_b_value => "0000001000000000",
-- synopsys translate_on
      a_width => 16,
      a_arith => xlSigned,
      a_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      p_width => 32,
      p_arith => xlSigned,
      p_bin_pt => 16,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      core_name0 => "multiplier_spartan2_6_0_c898a6c13135c6d0",
      b_bin_pt => 8,
      bram_addr_width => 8,
      c_a_type => 0,
      c_a_width => 16,
      c_b_constant => 1,
      c_b_type => 1,
      c_b_value_hi => 0,
      c_b_value_low => 512,
      c_b_width => 10,
      c_baat => 16,
      c_has_b => 0,
      c_has_loadb => 0,
      c_has_nd => 0,
      c_has_o => 1,
      c_has_q => 0,
      c_mem_type => 0,
      c_mult_type => 2,
      c_output_hold => 0,
      c_output_width => 32,
      c_pipelined => 0,
      c_reg_inputs => 0,
      c_type => 0,
      const_bin_pt => 8,
      extra_registers => 0,
      latency => 0,
      multsign => xlSigned,
      overflow => xlWrap,
      oversample => 1,
      quantization => xlTruncate
    )
    port map (
      a => q,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_3,
      rst => dout_x_4,
      p => p
    );
  delay: entity work.xldelay
    generic map (
      d_width => 16,
      d_arith => xlSigned,
      d_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      q_width => 16,
      q_arith => xlSigned,
      q_bin_pt => 8,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      latency => 1,
      reg_retiming => false
    )
    port map (
      ce => ce_sg_x_0,
      clk => clk_sg_x_0,
      clr => '0',
      d => gateway_in1_x_0,
      en => dout_x_11,
      rst => dout_x_13,
      q => q
    );
  delay1: entity work.xldelay
    generic map (
      d_width => 20,
      d_arith => xlSigned,
      d_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      q_width => 20,
      q_arith => xlSigned,
      q_bin_pt => 8,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      latency => 1,
      reg_retiming => false
    )
    port map (
      ce => ce_sg_x_0,
      clk => clk_sg_x_0,
      clr => '0',
      d => s_x_4,
      en => dout_x_14,
      rst => dout_x_15,
      q => q_x_0
    );
  delay2: entity work.xldelay
    generic map (
      d_width => 16,
      d_arith => xlSigned,
      d_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      q_width => 16,
      q_arith => xlSigned,
      q_bin_pt => 8,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      latency => 1,
      reg_retiming => false
    )
    port map (
      ce => ce_sg_x_0,
      clk => clk_sg_x_0,
      clr => '0',
      d => q,
      en => dout_x_16,
      rst => dout_x_17,
      q => q_x_1
    );
  kd: entity work.test1_cmult3
    generic map (
-- synopsys translate_off
      c_b_value => "001100001100000000",
-- synopsys translate_on
      a_width => 17,
      a_arith => xlSigned,
      a_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      p_width => 35,
      p_arith => xlSigned,
      p_bin_pt => 16,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      core_name0 => "multiplier_spartan2_6_0_7d52cda8234e03c2",
      b_bin_pt => 8,
      bram_addr_width => 8,
      c_a_type => 0,
      c_a_width => 17,
      c_b_constant => 1,
      c_b_type => 1,
      c_b_value_hi => 0,
      c_b_value_low => 49920,
      c_b_width => 16,
      c_baat => 17,
      c_has_b => 0,
      c_has_loadb => 0,
      c_has_nd => 0,
      c_has_o => 1,
      c_has_q => 0,
      c_mem_type => 0,
      c_mult_type => 2,
      c_output_hold => 0,
      c_output_width => 35,
      c_pipelined => 0,
      c_reg_inputs => 0,
      c_type => 0,
      const_bin_pt => 8,
      extra_registers => 0,
      latency => 0,
      multsign => xlSigned,
      overflow => xlWrap,
      oversample => 1,
      quantization => xlTruncate
    )
    port map (
      a => s_x_0,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_5,
      rst => dout_x_6,
      p => p_x_0
    );
  ki: entity work.test1_cmult3
    generic map (
-- synopsys translate_off
      c_b_value => "000000000000000010",
-- synopsys translate_on
      a_width => 16,
      a_arith => xlSigned,
      a_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      p_width => 34,
      p_arith => xlSigned,
      p_bin_pt => 22,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      core_name0 => "multiplier_spartan2_6_0_13a3d468139afdbd",
      b_bin_pt => 14,
      bram_addr_width => 8,
      c_a_type => 0,
      c_a_width => 16,
      c_b_constant => 1,
      c_b_type => 1,
      c_b_value_hi => 0,
      c_b_value_low => 2,
      c_b_width => 2,
      c_baat => 16,
      c_has_b => 0,
      c_has_loadb => 0,
      c_has_nd => 0,
      c_has_o => 1,
      c_has_q => 0,
      c_mem_type => 0,
      c_mult_type => 2,
      c_output_hold => 0,
      c_output_width => 34,
      c_pipelined => 0,
      c_reg_inputs => 0,
      c_type => 0,
      const_bin_pt => 14,
      extra_registers => 0,
      latency => 0,
      multsign => xlSigned,
      overflow => xlWrap,
      oversample => 1,
      quantization => xlTruncate
    )
    port map (
      a => gateway_in1_x_0,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_7,
      rst => dout_x_8,
      p => p_x_1
    );
  kp: entity work.test1_cmult3
    generic map (
-- synopsys translate_off
      c_b_value => "0000001000101111",
-- synopsys translate_on
      a_width => 16,
      a_arith => xlSigned,
      a_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      p_width => 32,
      p_arith => xlSigned,
      p_bin_pt => 15,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      core_name0 => "multiplier_spartan2_6_0_6f13cc9ee672d655",
      b_bin_pt => 7,
      bram_addr_width => 8,
      c_a_type => 0,
      c_a_width => 16,
      c_b_constant => 1,
      c_b_type => 1,
      c_b_value_hi => 0,
      c_b_value_low => 559,
      c_b_width => 10,
      c_baat => 16,
      c_has_b => 0,
      c_has_loadb => 0,
      c_has_nd => 0,
      c_has_o => 1,
      c_has_q => 0,
      c_mem_type => 0,
      c_mult_type => 2,
      c_output_hold => 0,
      c_output_width => 32,
      c_pipelined => 0,
      c_reg_inputs => 0,
      c_type => 0,
      const_bin_pt => 7,
      extra_registers => 0,
      latency => 0,
      multsign => xlSigned,
      overflow => xlWrap,
      oversample => 1,
      quantization => xlTruncate
    )
    port map (
      a => s_x_1,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_9,
      rst => dout_x_10,
      p => p_x_2
    );
  x: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout
    );
  x_x_0: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_0
    );
  x_x_1: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_1
    );
  x_x_10: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_2
    );
  x_x_11: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_3
    );
  x_x_12: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_4
    );
  x_x_13: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_5
    );
  x_x_14: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_6
    );
  x_x_15: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_7
    );
  x_x_16: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_8
    );
  x_x_17: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_9
    );
  x_x_18: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_10
    );
  x_x_19: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_11
    );
  x_x_2: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_12
    );
  x_x_20: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_13
    );
  x_x_21: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_14
    );
  x_x_22: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_15
    );
  x_x_23: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_16
    );
  x_x_24: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_17
    );
  x_x_3: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_18
    );
  x_x_4: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_19
    );
  x_x_5: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_20
    );
  x_x_6: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_21
    );
  x_x_7: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_22
    );
  x_x_8: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_23
    );
  x_x_9: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_24
    );
end structural;


-- -----------------------------------------------------------------
-- System Generator version 6.2 vhdl source file.
-- 
-- Copyright(C) 2005 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
-- 
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
-- 
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
-- 
-- Any modifications that are made to source code are done at the user’s
-- sole risk and will be unsupported.
-- 
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2005 Xilinx, Inc. 
-- All rights reserved.
-- -----------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;

entity test1_clock_driver is 
  port (
    sysce: in std_logic;
    sysclk: in std_logic;
    ce_sg: out std_logic;
    clk_sg: out std_logic
  );
end test1_clock_driver;

architecture structural of test1_clock_driver is
  component xlclockdriver
    generic (
      period: integer := 1;
      use_bufg: boolean := false
    );
    port (
      sysce: in std_logic;
      sysclk: in std_logic;
      sysclr: in std_logic;
      ce: out std_logic;
      clk: out std_logic
    );
  end component;

  signal ce_sg_x_0: std_logic;
  signal clk_sg_x_0: std_logic;
  signal clk_sysgen: std_logic;

begin
  clk_sysgen <= sysclk;
  ce_sg <= ce_sg_x_0;
  clk_sg <= clk_sg_x_0;

  xlclockdriver1: xlclockdriver
    generic map (
      period => 1,
      use_bufg => false
    )
    port map (
      sysce => '1',
      sysclk => clk_sysgen,
      sysclr => '0',
      ce => ce_sg_x_0,
      clk => clk_sg_x_0
    );
end structural;

