module choosen_out(clock,choice,choice_yy);

input clock;
input choice;

output choice_yy;

reg choice_y,choice_nyy;
wire choice_yy;

//rangkaian choice
always @(posedge clock)
       choice_y<=choice;

always @(posedge clock)
       choice_nyy<=~choice_y;

assign choice_yy=choice_y & choice_nyy;

endmodule
