

block logic {
  port gateway_in: in "std_logic_vector(7 downto 0)"  "[7 : 0]" 
    attrs {
      "bin_pt" => 6
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Gateway In"
      "width" => 8
      "period" => 1
    }
  port gateway_in1: in "std_logic_vector(7 downto 0)"  "[7 : 0]" 
    attrs {
      "bin_pt" => 6
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Gateway In1"
      "width" => 8
      "period" => 1
    }
  port gateway_in2: in "std_logic_vector(7 downto 0)"  "[7 : 0]" 
    attrs {
      "bin_pt" => 6
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Gateway In2"
      "width" => 8
      "period" => 1
    }
  port gateway_in3: in "std_logic_vector(7 downto 0)"  "[7 : 0]" 
    attrs {
      "bin_pt" => 6
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Gateway In3"
      "width" => 8
      "period" => 1
    }
  port gateway_out: out "std_logic_vector(7 downto 0)"  "[7 : 0]" 
    attrs {
      "bin_pt" => 6
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Gateway Out"
      "width" => 8
      "period" => 1
    }
  port gateway_out1: out "std_logic_vector(7 downto 0)"  "[7 : 0]" 
    attrs {
      "bin_pt" => 6
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Gateway Out1"
      "width" => 8
      "period" => 1
    }


  gateway_in <= gateway_in_x_0
  gateway_in1 <= gateway_in1_x_0
  gateway_in2 <= gateway_in2_x_0
  gateway_in3 <= gateway_in3_x_0
  dout_x_4 <= gateway_out
  dout_x_0 <= gateway_out1

  subblock inverter xlinv {
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    din => gateway_in2_x_0
    en => dout_x_5
    dout => dout
  }
  subblock inverter1 xlinv {
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    din => dout_x_1
    en => dout_x_6
    dout => dout_x_0
  }
  subblock logical xllogical3 {
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    din0 => gateway_in3_x_0
    din1 => dout
    din2 => dout_x_2
    en => dout_x_10
    dout => dout_x_1
  }
  subblock logical1 xllogical2 {
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    din0 => gateway_in_x_0
    din1 => gateway_in1_x_0
    en => dout_x_7
    dout => dout_x_2
  }
  subblock logical2 xllogical2 {
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    din0 => gateway_in_x_0
    din1 => gateway_in1_x_0
    en => dout_x_8
    dout => dout_x_3
  }
  subblock logical3 xllogical2 {
    ce => '0' : 'b0
    clk => '0' : 'b0
    clr => '0' : 'b0
    din0 => dout_x_0
    din1 => dout_x_3
    en => dout_x_9
    dout => dout_x_4
  }
  subblock x xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_5
  }
  subblock x_x_0 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_6
  }
  subblock x_x_1 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_7
  }
  subblock x_x_2 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_8
  }
  subblock x_x_3 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_9
  }
  subblock x_x_4 xlsl2slv {
    din => '1' : 'b1
    dout => dout_x_10
  }
}
  attrs {
    "simulink_name" => "logic"
    "is_top_level" => true
  }


block xlinv {
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "type" => "logic"
    }
  port din: in "std_logic_vector(din_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Inverter/din"
      "width" => 8
      "period" => 1
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "2"
      "simulink_name" => "logic/Inverter/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port dout: out "std_logic_vector(dout_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Inverter/dout"
      "width" => 8
      "period" => 1
    }
}
  attrs {
    "simulink_name" => "logic/Inverter"
    "generics" => [
      [
        "din_width"
        "integer"
        "8"
      ]
      [
        "din_arith"
        "integer"
        "xlSigned"
      ]
      [
        "din_bin_pt"
        "integer"
        "6"
      ]
      [
        "dout_width"
        "integer"
        "8"
      ]
      [
        "dout_arith"
        "integer"
        "xlSigned"
      ]
      [
        "dout_bin_pt"
        "integer"
        "6"
      ]
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "latency"
        "integer"
        "0"
      ]
    ]
  }


block xllogical3 {
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "type" => "logic"
    }
  port din0: in "std_logic_vector(din0_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Logical/din0"
      "width" => 8
      "period" => 1
    }
  port din1: in "std_logic_vector(din1_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "2"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Logical/din1"
      "width" => 8
      "period" => 1
    }
  port din2: in "std_logic_vector(din2_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "3"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Logical/din2"
      "width" => 8
      "period" => 1
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "4"
      "simulink_name" => "logic/Logical/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port dout: out "std_logic_vector(dout_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Logical/dout"
      "width" => 8
      "period" => 1
    }
}
  attrs {
    "simulink_name" => "logic/Logical"
    "generics" => [
      [
        "din0_width"
        "integer"
        "8"
      ]
      [
        "din0_arith"
        "integer"
        "xlSigned"
      ]
      [
        "din0_bin_pt"
        "integer"
        "6"
      ]
      [
        "din1_width"
        "integer"
        "8"
      ]
      [
        "din1_arith"
        "integer"
        "xlSigned"
      ]
      [
        "din1_bin_pt"
        "integer"
        "6"
      ]
      [
        "din2_width"
        "integer"
        "8"
      ]
      [
        "din2_arith"
        "integer"
        "xlSigned"
      ]
      [
        "din2_bin_pt"
        "integer"
        "6"
      ]
      [
        "dout_width"
        "integer"
        "8"
      ]
      [
        "dout_arith"
        "integer"
        "xlSigned"
      ]
      [
        "dout_bin_pt"
        "integer"
        "6"
      ]
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "full_arith"
        "integer"
        "xlSigned"
      ]
      [
        "full_bin_pt"
        "integer"
        "6"
      ]
      [
        "full_width"
        "integer"
        "8"
      ]
      [
        "gate_type"
        "integer"
        "1"
      ]
      [
        "latency"
        "integer"
        "0"
      ]
      [
        "num_inputs"
        "integer"
        "3"
      ]
    ]
  }


block xllogical2 {
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "type" => "logic"
    }
  port din0: in "std_logic_vector(din0_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Logical1/din0"
      "width" => 8
      "period" => 1
    }
  port din1: in "std_logic_vector(din1_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "2"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Logical1/din1"
      "width" => 8
      "period" => 1
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "3"
      "simulink_name" => "logic/Logical1/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port dout: out "std_logic_vector(dout_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "logic/Logical1/dout"
      "width" => 8
      "period" => 1
    }
}
  attrs {
    "simulink_name" => "logic/Logical1"
    "generics" => [
      [
        "din0_width"
        "integer"
        "8"
      ]
      [
        "din0_arith"
        "integer"
        "xlSigned"
      ]
      [
        "din0_bin_pt"
        "integer"
        "6"
      ]
      [
        "din1_width"
        "integer"
        "8"
      ]
      [
        "din1_arith"
        "integer"
        "xlSigned"
      ]
      [
        "din1_bin_pt"
        "integer"
        "6"
      ]
      [
        "dout_width"
        "integer"
        "8"
      ]
      [
        "dout_arith"
        "integer"
        "xlSigned"
      ]
      [
        "dout_bin_pt"
        "integer"
        "6"
      ]
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "full_arith"
        "integer"
        "xlSigned"
      ]
      [
        "full_bin_pt"
        "integer"
        "6"
      ]
      [
        "full_width"
        "integer"
        "8"
      ]
      [
        "gate_type"
        "integer"
        "2"
      ]
      [
        "latency"
        "integer"
        "0"
      ]
      [
        "num_inputs"
        "integer"
        "2"
      ]
    ]
  }


block xlsl2slv {
  port din: in "std_logic"  "" 
    attrs {
      "width" => 1
      "type" => "logic"
      "period" => -1
    }
  port dout: out "std_logic_vector(dout_width - 1 downto 0)"  "" 
    attrs {
      "width" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
      "period" => -1
    }
}
  attrs {
    "generics" => [
      [
        "dout_width"
        "integer"
        "1"
      ]
      [
        "dout_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "dout_bin_pt"
        "integer"
        "0"
      ]
    ]
  }

attrs {
  "system_clock_period" => 100
  "version" => "6.2"
  "sysgen" => "C:/MATLAB6p5/toolbox/xilinx/sysgen"
  "design" => "logic"
  "top_level" => "logic"
  "vhdl" => [  ]
  "config_script" => "C:/MATLAB6p5/work/isniamy/xlogic/temp/logic_config.m"
  "coregen_part_family" => "Spartan2"
  "mdl_path" => "C:/MATLAB6p5/work/isniamy/logic.mdl"
  "matlab_java_directory" => "C:/MATLAB6p5/sys/java/jre/win32/jre/bin"
  "verilog" => [  ]
  "matlab_perl_directory" => "C:/MATLAB6p5/sys/perl/win32/bin/"
  "start_time" => 0
  "device" => "xc2s50-6pq208"
  "synthesis_tool" => "XST"
  "ise_version" => "6.2i"
  "target_dir" => "C:/MATLAB6p5/work/isniamy/xlogic"
  "hdl_kind" => "vhdl"
  "design_file" => "C:/MATLAB6p5/work/isniamy/xlogic/temp/logic.vhd"
  "is_combinatorial" => true
  "part_family" => "Spartan2"
  "clocks_gcd" => 1
  "xilinx" => "C:/xilinx_62i"
  "stop_time" => 10
  "hdl_files" => [
    "conv_pkg.vhd"
    "clock_pkg.vhd"
    "synth_reg.vhd"
    "synth_reg_w_init.vhd"
    "xlclkprobe.vhd"
    "xlclockdriver.vhd"
    "xlclockgenerator.vhd"
    "xlsl2slv.vhd"
    "xlslv2sl.vhd"
    "xlinv.vhd"
    "xllogical2.vhd"
    "xllogical3.vhd"
    "logic.vhd"
  ]
}
