# do logic2_tbw.ado 
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity xlinv
# -- Compiling architecture dataflow of xlinv
# -- Loading entity synth_reg
# -- Compiling entity xllogical2
# -- Compiling architecture behavior of xllogical2
# -- Compiling entity xllogical3
# -- Compiling architecture behavior of xllogical3
# -- Compiling entity logic2
# -- Compiling architecture structural of logic2
# -- Loading entity xlinv
# -- Loading entity xllogical3
# -- Loading entity xllogical2
# -- Loading entity xlsl2slv
# -- Loading entity xlslv2sl
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity logic2_clk_wrapper
# -- Compiling architecture structural of logic2_clk_wrapper
# -- Loading entity logic2
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity logic2_tbw
# -- Compiling architecture testbench_arch of logic2_tbw
# -- Loading entity logic2_clk_wrapper
# -- Compiling configuration logic2_clk_wrapper_cfg
# -- Loading entity logic2_tbw
# -- Loading architecture testbench_arch of logic2_tbw
# vsim -lib work -t 1ps logic2_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.logic2_tbw(testbench_arch)
# Loading work.logic2_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.logic2(structural)
# Loading work.xlinv(dataflow)
# Loading work.xllogical3(behavior)
# Loading work.xllogical2(behavior)
# Loading work.xlsl2slv(behavior)
# Loading work.xlslv2sl(behavior)
# WARNING: Design size of 718 statements or 29 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 1950 ms  Iteration: 0  Process: /logic2_tbw/line__97 File: logic2_tbw.ant
# Break at logic2_tbw.ant line 182
# Stopped at logic2_tbw.ant line 182 
