# Xilinx CORE Generator 6.2i
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET create_rpm = true
CSET clock_enable = true
CSET output_options = non_registered
CSET overflow_output = false
CSET port_b_constant = false
CSET port_b_width = 54
CSET port_a_width = 54
CSET ce_overrides = sync_controls_override_ce
CSET bypass_sense = active_high
CSET port_a_sign = signed
CSET ce_override_for_bypass = true
CSET sync_init_value = 0
CSET operation = add
CSET latency = 0
CSET port_b_sign = signed
CSET component_name = adder_subtracter_spartan2_6_0_43856abc3712fb4f
CSET asynchronous_settings = none
CSET bypass = false
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET port_b_constant_value = 0
CSET set_clear_priority = clear_overrides_set
CSET output_width = 54
CSET synchronous_settings = clear
GENERATE
