# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do test2_tbw.tdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Compiling entity test2_clk_wrapper
# -- Compiling architecture structure of test2_clk_wrapper
# -- Loading entity x_mux2
# -- Loading entity x_xor2
# -- Loading entity x_lut4
# -- Loading entity x_buf
# -- Loading entity x_zero
# -- Loading entity x_one
# -- Loading entity x_tri
# -- Loading entity x_inv
# -- Loading entity x_ff
# -- Loading entity x_ckbuf
# -- Loading package vital_timing
# -- Loading entity x_roc
# -- Loading entity x_toc
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity test2_tbw
# -- Compiling architecture testbench_arch of test2_tbw
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package vpackage
# -- Loading entity test2_clk_wrapper
# -- Compiling configuration test2_clk_wrapper_cfg
# -- Loading entity test2_tbw
# -- Loading architecture testbench_arch of test2_tbw
# vsim -lib work -sdfmax /UUT=test2_clk_wrapper_timesim.sdf -t 1ps test2_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../vital2000.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.vcomponents
# Loading C:/Modeltech_xe_starter/win32xoem/../vital2000.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.vpackage(body)
# Loading work.test2_tbw(testbench_arch)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading work.test2_clk_wrapper(structure)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_mux2(x_mux2_v)
# Loading test2_clk_wrapper_timesim.sdf
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_xor2(x_xor2_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_lut4(x_lut4_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_buf(x_buf_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_zero(x_zero_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_one(x_one_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_tri(x_tri_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_inv(x_inv_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_ff(x_ff_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_ckbuf(x_ckbuf_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_toc(x_toc_v)
# WARNING: Design size of 5967 statements or 0 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Region: /test2_tbw  File: test2_tbw.timesim_vhw
# .wave
# .structure
# .signals
# ** Error: Error at time=20ns gateway_out=XXXXXXXXXXXXXXXXXX00, Expected = 00000000000000000000 
#    Time: 20 ns  Iteration: 0  Instance: /test2_tbw
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.318 ns; At : 111.702 ns
#    Time: 111702 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u215
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.399 ns; At : 111.702 ns
#    Time: 111702 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u213
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.248 ns; At : 111.702 ns
#    Time: 111702 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u216
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.329 ns; At : 111.702 ns
#    Time: 111702 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u214
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.41 ns; At : 111.702 ns
#    Time: 111702 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u212
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.228 ns; At : 111.774 ns
#    Time: 111774 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u219
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.309 ns; At : 111.774 ns
#    Time: 111774 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u217
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.239 ns; At : 111.774 ns
#    Time: 111774 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u218
# ** Error: Error at time=120ns gateway_out=11111111111111110000, Expected = 10110100001111100000 
#    Time: 120 ns  Iteration: 0  Instance: /test2_tbw
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.027 ns; At : 211.702 ns
#    Time: 211702 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u211
# ** Error: Error at time=220ns gateway_out=XXXXXXXX110111101000, Expected = 11111010000111100000 
#    Time: 220 ns  Iteration: 0  Instance: /test2_tbw
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.025 ns; At : 311.702 ns
#    Time: 311702 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u29
# ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.404 ns; At : 311.702 ns
#    Time: 311702 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u210
# ** Error: Error at time=320ns gateway_out=XXXXXXXXX00011100100, Expected = 00011101000011100000 
#    Time: 320 ns  Iteration: 0  Instance: /test2_tbw
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.417 ns; At : 411.774 ns
#    Time: 411774 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u28
# ** Error: Error at time=420ns gateway_out=XXXXXXXXXXX001100000, Expected = 00101110100001011100 
#    Time: 420 ns  Iteration: 0  Instance: /test2_tbw
# ** Error: Error at time=520ns gateway_out=XXXXXXXXXXXX00011100, Expected = 00110111010000011000 
#    Time: 520 ns  Iteration: 0  Instance: /test2_tbw
# ** Error: Error at time=620ns gateway_out=XXXXXXXXXXXX11111000, Expected = 00111011100111110100 
#    Time: 620 ns  Iteration: 0  Instance: /test2_tbw
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.162 ns; At : 711.774 ns
#    Time: 711774 ps  Iteration: 1  Instance: /test2_tbw/uut/test2_top_delay1_synth_reg_srl_inst_last_srl17e_u27
# ** Error: Error at time=720ns gateway_out=XXXXXXXXXXXX11100100, Expected = 00111101110011100000 
#    Time: 720 ns  Iteration: 0  Instance: /test2_tbw
# ** Error: Error at time=820ns gateway_out=XXXXXXXXXXXXX1100000, Expected = 00111101110011011100 
#    Time: 820 ns  Iteration: 0  Instance: /test2_tbw
# ** Error: Error at time=920ns gateway_out=XXXXXXXXXXXXX1011100, Expected = 00111101110011011000 
#    Time: 920 ns  Iteration: 0  Instance: /test2_tbw
# ** Error: Error at time=1020ns gateway_out=XXXXXXXXXXXXX1011000, Expected = 00111101110011010100 
#    Time: 1020 ns  Iteration: 0  Instance: /test2_tbw
# ** Failure: Errors found during simulation
#    Time: 1110 ns  Iteration: 0  Process: /test2_tbw/line__66 File: test2_tbw.timesim_vhw
# Break at test2_tbw.timesim_vhw line 182
# Simulation Breakpoint: Break at test2_tbw.timesim_vhw line 182
# MACRO ./test2_tbw.tdo PAUSED at line 14
# WARNING: No extended dataflow License exists
destroy .structure
destroy .signals
destroy .wave
