
function coba_config(this_block)
  this_block.setTopLevelLanguage('VHDL');

  this_block.setEntityName('coba');
  this_block.addSimulinkInport('gateway_in');
  this_block.port('gateway_in').useHDLVector(true);
  this_block.addSimulinkInport('gateway_in1');
  this_block.port('gateway_in1').useHDLVector(true);

  this_block.addSimulinkOutport('gateway_out1');
  this_block.port('gateway_out1').useHDLVector(true);
  this_block.port('gateway_out1').setType('UFix_16_4');

  this_block.tagAsCombinational;

% -----------------------------
  % Do input type checking, and dynamic output type and 
  % generic setup here.
  if (this_block.inputTypesKnown)
    if (~ strcmp('UFix_8_4', this_block.port('gateway_in').type))
      this_block.setError('Input data type for port "gateway_in" must be "UFix_8_4".');
    end
    if (~ strcmp('UFix_8_4', this_block.port('gateway_in1').type))
      this_block.setError('Input data type for port "gateway_in1" must be "UFix_8_4".');
    end
  end

% -----------------------------

% -----------------------------
% Do input rate checking here.
  if (this_block.inputRatesKnown)
    if (this_block.port('gateway_in').rate ~= 1)
      this_block.setError('Rate for port "gateway_in" must be 1.');
    end
    if (this_block.port('gateway_in1').rate ~= 1)
      this_block.setError('Rate for port "gateway_in1" must be 1.');
    end
  end

% -----------------------------

% -----------------------------
% Set output rates here.
  this_block.port('gateway_out1').setRate(1);


% -----------------------------
% Set up clocks and clock enables here.
  this_block.addClkCEPair('clk_sg', 'ce_sg', 1);


% -----------------------------
% Set up vhdl/verilog files here.
  this_block.addFile('xcoba/temp/conv_pkg.vhd');
  this_block.addFile('xcoba/temp/clock_pkg.vhd');
  this_block.addFile('xcoba/temp/synth_reg.vhd');
  this_block.addFile('xcoba/temp/synth_reg_w_init.vhd');
  this_block.addFile('xcoba/temp/xlclkprobe.vhd');
  this_block.addFile('xcoba/temp/xlclockdriver.vhd');
  this_block.addFile('xcoba/temp/xlclockgenerator.vhd');
  this_block.addFile('xcoba/temp/xlsl2slv.vhd');
  this_block.addFile('xcoba/temp/xlslv2sl.vhd');
  this_block.addFile('xcoba/temp/synth_addsub.vhd');
  this_block.addFile('xcoba/temp/coba_addsub.vhd');
  this_block.addFile('xcoba/temp/coba.vhd');


% -----------------------------
% Set up .edn, .mif, .coe, ... files here.
  this_block.addFile('xcoba/temp/adder_subtracter_spartan2_6_0_565e6fc4f8af6f53.edn');

