-- C:\MATLAB6P5\WORK\ISNIAMY\XLOGIC2
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Wed May 18 16:57:15 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.CONV_PKG.ALL;
USE WORK.CLOCK_PKG.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY logic2_tbw IS
END logic2_tbw;

ARCHITECTURE testbench_arch OF logic2_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\matlab6p5\work\isniamy\xlogic2\logic2_tbw.ano";
	COMPONENT logic2_clk_wrapper
		PORT (
			gateway_in : In  std_logic;
			gateway_in1 : In  std_logic;
			gateway_in2 : In  std_logic;
			gateway_in3 : In  std_logic;
			gateway_out : Out  std_logic;
			gateway_out1 : Out  std_logic
		);
	END COMPONENT;

	SIGNAL gateway_in : std_logic;
	SIGNAL gateway_in1 : std_logic;
	SIGNAL gateway_in2 : std_logic;
	SIGNAL gateway_in3 : std_logic;
	SIGNAL gateway_out : std_logic;
	SIGNAL gateway_out1 : std_logic;

BEGIN
	UUT : logic2_clk_wrapper
	PORT MAP (
		gateway_in => gateway_in,
		gateway_in1 => gateway_in1,
		gateway_in2 => gateway_in2,
		gateway_in3 => gateway_in3,
		gateway_out => gateway_out,
		gateway_out1 => gateway_out1
	);

	PROCESS -- Annotate outputs process
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_gateway_out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",gateway_out,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, gateway_out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_gateway_out1(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",gateway_out1,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, gateway_out1);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CHECK_LOOP : LOOP
		WAIT FOR 50 ms;
		TX_TIME := TX_TIME + 50;
		ANNOTATE_gateway_out(TX_TIME);
		ANNOTATE_gateway_out1(TX_TIME);
		WAIT FOR 50 ms;
		TX_TIME := TX_TIME + 50;
		END LOOP CHECK_LOOP;
	END PROCESS;

	PROCESS
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		gateway_in <= transport '0';
		gateway_in1 <= transport '0';
		gateway_in2 <= transport '0';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=100 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=200 ms
		gateway_in2 <= transport '1';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=300 ms
		gateway_in1 <= transport '0';
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=400 ms
		gateway_in1 <= transport '1';
		gateway_in2 <= transport '0';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=500 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=600 ms
		gateway_in2 <= transport '1';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=700 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=800 ms
		gateway_in <= transport '1';
		gateway_in1 <= transport '0';
		gateway_in2 <= transport '0';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=900 ms
		gateway_in <= transport '1';
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1000 ms
		gateway_in <= transport '1';
		gateway_in2 <= transport '1';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1100 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1200 ms
		gateway_in1 <= transport '1';
		gateway_in2 <= transport '0';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1300 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1400 ms
		gateway_in2 <= transport '1';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1500 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1600 ms
		gateway_in <= transport '0';
		gateway_in1 <= transport '0';
		gateway_in2 <= transport '0';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 200 ms; -- Time=1800 ms
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 150 ms; -- Time=1950 ms
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION logic2_clk_wrapper_cfg OF logic2_tbw IS
	FOR testbench_arch
	END FOR;
END logic2_clk_wrapper_cfg;
