
-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2005 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
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-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
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--
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-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2005 Xilinx, Inc. 
-- All rights reserved.
--------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;

entity pid_sg_full_001 is
  port (
    ce_sg: in std_logic;
    clk_sg: in std_logic;
    gateway_in1: in std_logic_vector(15 downto 0);
    gateway_out: out std_logic_vector(19 downto 0)
  );
end pid_sg_full_001;

architecture structural of pid_sg_full_001 is
  signal ce_sg_x_0: std_logic;
  signal clk_sg_x_0: std_logic;
  signal dout: std_logic_vector(0 downto 0);
  signal dout_x_0: std_logic_vector(0 downto 0);
  signal dout_x_1: std_logic_vector(0 downto 0);
  signal dout_x_10: std_logic_vector(0 downto 0);
  signal dout_x_11: std_logic_vector(0 downto 0);
  signal dout_x_12: std_logic_vector(0 downto 0);
  signal dout_x_13: std_logic_vector(0 downto 0);
  signal dout_x_14: std_logic_vector(0 downto 0);
  signal dout_x_15: std_logic_vector(0 downto 0);
  signal dout_x_16: std_logic_vector(0 downto 0);
  signal dout_x_17: std_logic_vector(0 downto 0);
  signal dout_x_18: std_logic_vector(0 downto 0);
  signal dout_x_19: std_logic_vector(0 downto 0);
  signal dout_x_2: std_logic_vector(0 downto 0);
  signal dout_x_20: std_logic_vector(0 downto 0);
  signal dout_x_21: std_logic_vector(0 downto 0);
  signal dout_x_22: std_logic_vector(0 downto 0);
  signal dout_x_23: std_logic_vector(0 downto 0);
  signal dout_x_24: std_logic_vector(0 downto 0);
  signal dout_x_3: std_logic_vector(0 downto 0);
  signal dout_x_4: std_logic_vector(0 downto 0);
  signal dout_x_5: std_logic_vector(0 downto 0);
  signal dout_x_6: std_logic_vector(0 downto 0);
  signal dout_x_7: std_logic_vector(0 downto 0);
  signal dout_x_8: std_logic_vector(0 downto 0);
  signal dout_x_9: std_logic_vector(0 downto 0);
  signal gateway_in1_x_0: std_logic_vector(15 downto 0);
  signal p: std_logic_vector(31 downto 0);
  signal p_x_0: std_logic_vector(51 downto 0);
  signal p_x_1: std_logic_vector(31 downto 0);
  signal p_x_2: std_logic_vector(32 downto 0);
  signal q: std_logic_vector(15 downto 0);
  signal q_x_0: std_logic_vector(19 downto 0);
  signal q_x_1: std_logic_vector(15 downto 0);
  signal s: std_logic_vector(32 downto 0);
  signal s_x_0: std_logic_vector(33 downto 0);
  signal s_x_1: std_logic_vector(16 downto 0);
  signal s_x_2: std_logic_vector(53 downto 0);
  signal s_x_3: std_logic_vector(52 downto 0);
  signal s_x_4: std_logic_vector(19 downto 0);

begin
  ce_sg_x_0 <= ce_sg;
  clk_sg_x_0 <= clk_sg;
  gateway_in1_x_0 <= gateway_in1;
  gateway_out <= s_x_4;

  addsub1: entity work.pid_sg_full_001_addsub1
    generic map (
      a_width => 16,
      a_arith => xlSigned,
      a_bin_pt => 4,
      b_width => 32,
      b_arith => xlSigned,
      b_bin_pt => 12,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 33,
      s_arith => xlSigned,
      s_bin_pt => 12,
      core_name0 => "adder_subtracter_spartan2_6_0_438ebd1a25415d4b",
      c_a_type => 0,
      c_a_width => 33,
      c_add_mode => 1,
      c_b_type => 0,
      c_b_width => 33,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 33,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 33,
      latency => 0,
      mode => 2,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => q_x_1,
      b => p,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout,
      rst => dout_x_0,
      s => s
    );
  addsub2: entity work.pid_sg_full_001_addsub1
    generic map (
      a_width => 33,
      a_arith => xlSigned,
      a_bin_pt => 12,
      b_width => 16,
      b_arith => xlSigned,
      b_bin_pt => 4,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 34,
      s_arith => xlSigned,
      s_bin_pt => 12,
      core_name0 => "adder_subtracter_spartan2_6_0_317484e55db19a4e",
      c_a_type => 0,
      c_a_width => 34,
      c_add_mode => 0,
      c_b_type => 0,
      c_b_width => 34,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 34,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 34,
      latency => 0,
      mode => 1,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => s,
      b => gateway_in1_x_0,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_1,
      rst => dout_x_12,
      s => s_x_0
    );
  addsub3: entity work.pid_sg_full_001_addsub1
    generic map (
      a_width => 16,
      a_arith => xlSigned,
      a_bin_pt => 4,
      b_width => 16,
      b_arith => xlSigned,
      b_bin_pt => 4,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 17,
      s_arith => xlSigned,
      s_bin_pt => 4,
      core_name0 => "adder_subtracter_spartan2_6_0_86c498140491d6df",
      c_a_type => 0,
      c_a_width => 17,
      c_add_mode => 1,
      c_b_type => 0,
      c_b_width => 17,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 17,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 17,
      latency => 0,
      mode => 2,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => gateway_in1_x_0,
      b => q,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_18,
      rst => dout_x_19,
      s => s_x_1
    );
  addsub4: entity work.pid_sg_full_001_addsub1
    generic map (
      a_width => 53,
      a_arith => xlSigned,
      a_bin_pt => 20,
      b_width => 33,
      b_arith => xlSigned,
      b_bin_pt => 11,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 54,
      s_arith => xlSigned,
      s_bin_pt => 20,
      core_name0 => "adder_subtracter_spartan2_6_0_43856abc3712fb4f",
      c_a_type => 0,
      c_a_width => 54,
      c_add_mode => 0,
      c_b_type => 0,
      c_b_width => 54,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 54,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 54,
      latency => 0,
      mode => 1,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => s_x_3,
      b => p_x_2,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_20,
      rst => dout_x_21,
      s => s_x_2
    );
  addsub5: entity work.pid_sg_full_001_addsub1
    generic map (
      a_width => 52,
      a_arith => xlSigned,
      a_bin_pt => 20,
      b_width => 32,
      b_arith => xlSigned,
      b_bin_pt => 18,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 53,
      s_arith => xlSigned,
      s_bin_pt => 20,
      core_name0 => "adder_subtracter_spartan2_6_0_7e2e2ff90f08677d",
      c_a_type => 0,
      c_a_width => 53,
      c_add_mode => 0,
      c_b_type => 0,
      c_b_width => 53,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 53,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 53,
      latency => 0,
      mode => 1,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => p_x_0,
      b => p_x_1,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_22,
      rst => dout_x_23,
      s => s_x_3
    );
  addsub6: entity work.pid_sg_full_001_addsub1
    generic map (
      a_width => 54,
      a_arith => xlSigned,
      a_bin_pt => 20,
      b_width => 20,
      b_arith => xlSigned,
      b_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 20,
      s_arith => xlSigned,
      s_bin_pt => 8,
      core_name0 => "adder_subtracter_spartan2_6_0_b0bfdb99fc98b3ec",
      c_a_type => 0,
      c_a_width => 55,
      c_add_mode => 0,
      c_b_type => 0,
      c_b_width => 55,
      c_enable_rlocs => 0,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 0,
      c_has_q => 0,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 1,
      c_has_sclr => 0,
      c_latency => 0,
      c_output_width => 55,
      core => true,
      extra_registers => 0,
      full_s_arith => xlSigned,
      full_s_width => 55,
      latency => 0,
      mode => 1,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => s_x_2,
      b => q_x_0,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_24,
      rst => dout_x_2,
      s => s_x_4
    );
  cmult3: entity work.pid_sg_full_001_cmult3
    generic map (
-- synopsys translate_off
      c_b_value => "0000001000000000",
-- synopsys translate_on
      a_width => 16,
      a_arith => xlSigned,
      a_bin_pt => 4,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      p_width => 32,
      p_arith => xlSigned,
      p_bin_pt => 12,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      core_name0 => "multiplier_spartan2_6_0_c898a6c13135c6d0",
      b_bin_pt => 8,
      bram_addr_width => 8,
      c_a_type => 0,
      c_a_width => 16,
      c_b_constant => 1,
      c_b_type => 1,
      c_b_value_hi => 0,
      c_b_value_low => 512,
      c_b_width => 10,
      c_baat => 16,
      c_has_b => 0,
      c_has_loadb => 0,
      c_has_nd => 0,
      c_has_o => 1,
      c_has_q => 0,
      c_mem_type => 0,
      c_mult_type => 2,
      c_output_hold => 0,
      c_output_width => 32,
      c_pipelined => 0,
      c_reg_inputs => 0,
      c_type => 0,
      const_bin_pt => 8,
      extra_registers => 0,
      latency => 0,
      multsign => xlSigned,
      overflow => xlWrap,
      oversample => 1,
      quantization => xlTruncate
    )
    port map (
      a => q,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_3,
      rst => dout_x_4,
      p => p
    );
  delay: entity work.xldelay
    generic map (
      d_width => 16,
      d_arith => xlSigned,
      d_bin_pt => 4,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      q_width => 16,
      q_arith => xlSigned,
      q_bin_pt => 4,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      latency => 1,
      reg_retiming => false
    )
    port map (
      ce => ce_sg_x_0,
      clk => clk_sg_x_0,
      clr => '0',
      d => gateway_in1_x_0,
      en => dout_x_11,
      rst => dout_x_13,
      q => q
    );
  delay1: entity work.xldelay
    generic map (
      d_width => 20,
      d_arith => xlSigned,
      d_bin_pt => 8,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      q_width => 20,
      q_arith => xlSigned,
      q_bin_pt => 8,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      latency => 1,
      reg_retiming => false
    )
    port map (
      ce => ce_sg_x_0,
      clk => clk_sg_x_0,
      clr => '0',
      d => s_x_4,
      en => dout_x_14,
      rst => dout_x_15,
      q => q_x_0
    );
  delay2: entity work.xldelay
    generic map (
      d_width => 16,
      d_arith => xlSigned,
      d_bin_pt => 4,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      q_width => 16,
      q_arith => xlSigned,
      q_bin_pt => 4,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      latency => 1,
      reg_retiming => false
    )
    port map (
      ce => ce_sg_x_0,
      clk => clk_sg_x_0,
      clr => '0',
      d => q,
      en => dout_x_16,
      rst => dout_x_17,
      q => q_x_1
    );
  kd: entity work.pid_sg_full_001_cmult3
    generic map (
-- synopsys translate_off
      c_b_value => "001100001100000000",
-- synopsys translate_on
      a_width => 34,
      a_arith => xlSigned,
      a_bin_pt => 12,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      p_width => 52,
      p_arith => xlSigned,
      p_bin_pt => 20,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      core_name0 => "multiplier_spartan2_6_0_378271e886b68b2a",
      b_bin_pt => 8,
      bram_addr_width => 8,
      c_a_type => 0,
      c_a_width => 34,
      c_b_constant => 1,
      c_b_type => 1,
      c_b_value_hi => 0,
      c_b_value_low => 49920,
      c_b_width => 16,
      c_baat => 34,
      c_has_b => 0,
      c_has_loadb => 0,
      c_has_nd => 0,
      c_has_o => 1,
      c_has_q => 0,
      c_mem_type => 0,
      c_mult_type => 2,
      c_output_hold => 0,
      c_output_width => 52,
      c_pipelined => 0,
      c_reg_inputs => 0,
      c_type => 0,
      const_bin_pt => 8,
      extra_registers => 0,
      latency => 0,
      multsign => xlSigned,
      overflow => xlWrap,
      oversample => 1,
      quantization => xlTruncate
    )
    port map (
      a => s_x_0,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_5,
      rst => dout_x_6,
      p => p_x_0
    );
  ki: entity work.pid_sg_full_001_cmult3
    generic map (
-- synopsys translate_off
      c_b_value => "0000000000000010",
-- synopsys translate_on
      a_width => 16,
      a_arith => xlSigned,
      a_bin_pt => 4,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      p_width => 32,
      p_arith => xlSigned,
      p_bin_pt => 18,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      core_name0 => "multiplier_spartan2_6_0_ec7571a02d602c36",
      b_bin_pt => 14,
      bram_addr_width => 8,
      c_a_type => 0,
      c_a_width => 16,
      c_b_constant => 1,
      c_b_type => 1,
      c_b_value_hi => 0,
      c_b_value_low => 2,
      c_b_width => 2,
      c_baat => 16,
      c_has_b => 0,
      c_has_loadb => 0,
      c_has_nd => 0,
      c_has_o => 1,
      c_has_q => 0,
      c_mem_type => 0,
      c_mult_type => 2,
      c_output_hold => 0,
      c_output_width => 32,
      c_pipelined => 0,
      c_reg_inputs => 0,
      c_type => 0,
      const_bin_pt => 14,
      extra_registers => 0,
      latency => 0,
      multsign => xlSigned,
      overflow => xlWrap,
      oversample => 1,
      quantization => xlTruncate
    )
    port map (
      a => gateway_in1_x_0,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_7,
      rst => dout_x_8,
      p => p_x_1
    );
  kp: entity work.pid_sg_full_001_cmult3
    generic map (
-- synopsys translate_off
      c_b_value => "0000001000101111",
-- synopsys translate_on
      a_width => 17,
      a_arith => xlSigned,
      a_bin_pt => 4,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      p_width => 33,
      p_arith => xlSigned,
      p_bin_pt => 11,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      core_name0 => "multiplier_spartan2_6_0_e5bc92dce938ed6f",
      b_bin_pt => 7,
      bram_addr_width => 8,
      c_a_type => 0,
      c_a_width => 17,
      c_b_constant => 1,
      c_b_type => 1,
      c_b_value_hi => 0,
      c_b_value_low => 559,
      c_b_width => 10,
      c_baat => 17,
      c_has_b => 0,
      c_has_loadb => 0,
      c_has_nd => 0,
      c_has_o => 1,
      c_has_q => 0,
      c_mem_type => 0,
      c_mult_type => 2,
      c_output_hold => 0,
      c_output_width => 33,
      c_pipelined => 0,
      c_reg_inputs => 0,
      c_type => 0,
      const_bin_pt => 7,
      extra_registers => 0,
      latency => 0,
      multsign => xlSigned,
      overflow => xlWrap,
      oversample => 1,
      quantization => xlTruncate
    )
    port map (
      a => s_x_1,
      ce => '0',
      clk => '0',
      clr => '0',
      en => dout_x_9,
      rst => dout_x_10,
      p => p_x_2
    );
  x: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout
    );
  x_x_0: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_0
    );
  x_x_1: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_1
    );
  x_x_10: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_2
    );
  x_x_11: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_3
    );
  x_x_12: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_4
    );
  x_x_13: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_5
    );
  x_x_14: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_6
    );
  x_x_15: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_7
    );
  x_x_16: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_8
    );
  x_x_17: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_9
    );
  x_x_18: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_10
    );
  x_x_19: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_11
    );
  x_x_2: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_12
    );
  x_x_20: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_13
    );
  x_x_21: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_14
    );
  x_x_22: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_15
    );
  x_x_23: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_16
    );
  x_x_24: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_17
    );
  x_x_3: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_18
    );
  x_x_4: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_19
    );
  x_x_5: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_20
    );
  x_x_6: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_21
    );
  x_x_7: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_22
    );
  x_x_8: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_23
    );
  x_x_9: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_24
    );
end structural;
