
-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity synth_addsub is
  generic (
    arith_type : integer;
    a_width    : integer;
    b_width    : integer;
    s_width    : integer;
    mode       : integer;
    use_cin    : integer;
    use_bin    : integer;
    latency    : integer);
  port (
    a   : in std_logic_vector(a_width-1 downto 0);
    b   : in std_logic_vector(b_width-1 downto 0);
    cin  : in std_logic_vector(0 downto 0) := "0";
    ce  : in std_logic;
    clr : in std_logic;
    clk : in std_logic;
    cout : out std_logic_vector(0 downto 0) := (others => '0');
    s   : out std_logic_vector(s_width-1 downto 0));
end synth_addsub;
architecture behavior of synth_addsub is
  component synth_reg
    generic (
      width   : integer := 16;
      latency : integer := 5);
    port (
      i    : in std_logic_vector(width-1 downto 0);
      ce   : in std_logic;
      clr  : in std_logic;
      clk  : in std_logic;
      o    : out std_logic_vector(width-1 downto 0));
  end component;
  signal result : std_logic_vector(s_width-1 downto 0);
  signal cout_temp : std_logic_vector(0 downto 0) := "0";
  signal internal_cin : std_logic_vector(0 downto 0);
  signal cin_sub : std_logic_vector(0 downto 0);
begin
 cin_test: if  (use_cin = 1 or use_bin = 1)  generate
    internal_cin <= cin;
    cin_sub <= not(cin);
  end generate cin_test;
 cin_test2: if  (use_cin = 0 and use_bin = 0)  generate
    internal_cin(0) <= '0';
    cin_sub(0) <= '0';
  end generate cin_test2;
  addsub_process :  process (a, b, internal_cin, cin_sub)
  begin
    if (mode = xlAddMode) then
      if (arith_type = xlUnsigned) then
        result <= unsigned_to_std_logic_vector( std_logic_vector_to_unsigned(a) +
                                std_logic_vector_to_unsigned(b) +
                                std_logic_vector_to_unsigned(internal_cin));
      else
        result <= signed_to_std_logic_vector( std_logic_vector_to_signed(a) +
                                std_logic_vector_to_signed(b) +
                                std_logic_vector_to_signed(internal_cin));
      end if;
    else
      if (arith_type = xlUnsigned) then
        result <= unsigned_to_std_logic_vector( std_logic_vector_to_unsigned(a) -
                                std_logic_vector_to_unsigned(b) -
                                std_logic_vector_to_unsigned(cin_sub));
      else
        result <= signed_to_std_logic_vector( std_logic_vector_to_signed(a) -
                               std_logic_vector_to_signed(b) -
                               std_logic_vector_to_signed(cin_sub));
      end if;
    end if;
  end process addsub_process;
  cout_process :  process (result, internal_cin,a,b, cin_sub)
  begin
    if(mode = xlAddMode) then
      cout_temp(0) <= result(s_width - 1);
    else
      if (arith_type = xlUnsigned) then
        if (std_logic_vector_to_signed(b) <= std_logic_vector_to_signed(unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(a) - std_logic_vector_to_unsigned(cin_sub)))) then
                cout_temp(0) <= '1';
        else
                cout_temp(0) <= '0';
        end if;
      else
        if (std_logic_vector_to_signed(b) <= (std_logic_vector_to_signed(a) -
                        std_logic_vector_to_signed(cin_sub))) then
                cout_temp(0) <= '1';
        else
                cout_temp(0) <= '0';
        end if;
      end if;
    end if;
  end process cout_process;
  latency_test : if (latency > 0) generate
    reg : synth_reg
       generic map (
         width   => s_width,
         latency => latency)
       port map (
         i   => result,
         ce  => ce,
         clr => clr,
         clk => clk,
         o   => s);
  end generate;
  cout_test : if (latency > 0) generate
    cout_reg : synth_reg
       generic map (
         width   => 1,
         latency => latency)
       port map (
         i   => cout_temp,
         ce  => ce,
         clr => clr,
         clk => clk,
         o   => cout);
  end generate;
  latency0 : if (latency = 0) generate
    s <= result;
    cout <= cout_temp;
  end generate latency0;
end architecture behavior;
