-- C:\MATLAB6P5\WORK\XTEST1_NO_ZOH
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Wed Mar 30 20:15:41 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.CONV_PKG.ALL;
USE WORK.CLOCK_PKG.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test1_no_zoh IS
END test1_no_zoh;

ARCHITECTURE testbench_arch OF test1_no_zoh IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\matlab6p5\work\xtest1_no_zoh\test1_no_zoh.ano";
	COMPONENT test1_no_zoh
		PORT (
			ce_sg : In  std_logic;
			clk_sg : In  std_logic;
			gateway_in1 : In  std_logic_vector (15 DOWNTO 0);
			gateway_out : Out  std_logic_vector (19 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL ce_sg : std_logic;
	SIGNAL clk_sg : std_logic;
	SIGNAL gateway_in1 : std_logic_vector (15 DOWNTO 0);
	SIGNAL gateway_out : std_logic_vector (19 DOWNTO 0);

BEGIN
	UUT : test1_no_zoh
	PORT MAP (
		ce_sg => ce_sg,
		clk_sg => clk_sg,
		gateway_in1 => gateway_in1,
		gateway_out => gateway_out
	);

	PROCESS -- clock process for clk_sg,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_gateway_out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",gateway_out,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, gateway_out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk_sg <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clk_sg <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_gateway_out(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clk_sg <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk_sg
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		ce_sg <= transport '1';
		gateway_in1 <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		ce_sg <= transport '0';
		gateway_in1 <= transport std_logic_vector'("1000000000000000"); --8000
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		ce_sg <= transport '1';
		gateway_in1 <= transport std_logic_vector'("1100000000000000"); --C000
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		gateway_in1 <= transport std_logic_vector'("1110000000000000"); --E000
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		gateway_in1 <= transport std_logic_vector'("1111000000000000"); --F000
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		gateway_in1 <= transport std_logic_vector'("1111100000000000"); --F800
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		gateway_in1 <= transport std_logic_vector'("1111110000000000"); --FC00
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		gateway_in1 <= transport std_logic_vector'("1111111000000000"); --FE00
		-- --------------------
		WAIT FOR 110 ns; -- Time=810 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION test1_no_zoh_cfg OF test1_no_zoh IS
	FOR testbench_arch
	END FOR;
END test1_no_zoh_cfg;
