# Xilinx CORE Generator 6.2i
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET create_rpm = true
CSET clock_enable = false
CSET output_options = Non_Registered
CSET port_b_constant = true
CSET reloadable = false
CSET port_b_width = 2
CSET nd = false
CSET multiplier_type = Parallel
CSET port_a_width = 16
CSET memory_type = Distributed_Memory
CSET port_a_data = Signed
CSET rdy = false
CSET register_input = false
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_13a3d468139afdbd
CSET port_b_data = Unsigned
CSET asynchronous_clear = false
CSET rfd = false
CSET clk_cycles_per_input = 1
CSET port_b_constant_value = 2
CSET style = Rectangular_Shape
CSET pipelined = Minimum
CSET output_hold_register = false
CSET output_width = 34
GENERATE
