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library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;

entity coba is
  port (
    ce_sg: in std_logic;
    clk_sg: in std_logic;
    gateway_in: in std_logic_vector(7 downto 0);
    gateway_in1: in std_logic_vector(7 downto 0);
    gateway_out1: out std_logic_vector(15 downto 0)
  );
end coba;

architecture structural of coba is
  signal ce_sg_x_0: std_logic;
  signal clk_sg_x_0: std_logic;
  signal dout: std_logic_vector(0 downto 0);
  signal dout_x_0: std_logic_vector(0 downto 0);
  signal gateway_in1_x_0: std_logic_vector(7 downto 0);
  signal gateway_in_x_0: std_logic_vector(7 downto 0);
  signal s: std_logic_vector(15 downto 0);

begin
  ce_sg_x_0 <= ce_sg;
  clk_sg_x_0 <= clk_sg;
  gateway_in_x_0 <= gateway_in;
  gateway_in1_x_0 <= gateway_in1;
  gateway_out1 <= s;

  addsub: entity work.coba_addsub
    generic map (
      a_width => 8,
      a_arith => xlUnsigned,
      a_bin_pt => 4,
      b_width => 8,
      b_arith => xlUnsigned,
      b_bin_pt => 4,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      rst_width => 1,
      rst_arith => xlUnsigned,
      rst_bin_pt => 0,
      s_width => 16,
      s_arith => xlUnsigned,
      s_bin_pt => 4,
      core_name0 => "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53",
      c_a_type => 1,
      c_a_width => 9,
      c_add_mode => 0,
      c_b_type => 1,
      c_b_width => 9,
      c_enable_rlocs => 1,
      c_has_b_in => 0,
      c_has_b_out => 0,
      c_has_c_in => 0,
      c_has_c_out => 0,
      c_has_ce => 1,
      c_has_q => 1,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 0,
      c_has_sclr => 1,
      c_latency => 1,
      c_output_width => 9,
      core => true,
      extra_registers => 0,
      full_s_arith => xlUnsigned,
      full_s_width => 9,
      latency => 1,
      mode => 1,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      a => gateway_in_x_0,
      b => gateway_in1_x_0,
      ce => ce_sg_x_0,
      clk => clk_sg_x_0,
      clr => '0',
      en => dout,
      rst => dout_x_0,
      s => s
    );
  x: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout
    );
  x_x_0: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '0',
      dout => dout_x_0
    );
end structural;
