module clk_div10ms (clk_sys, reset, clk_10ms);

input clk_sys, reset;
output clk_div10ms;

reg [18:0] clk_cnt;
wire clk_10ms;

always @ (clk_cnt)
begin
     if (clk_cnt==256000)
     begin
          if (count < 1500)
          clk_div <= !clk_div
          count <= count + 1
          end
end

assign clk_10ms = clk_cnt[18];

endmodule
