-- C:\MATLAB6P5\WORK\ISNIAMY\XSPARTAN2
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu Aug 18 14:57:15 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.CONV_PKG.ALL;
USE WORK.CLOCK_PKG.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY tv_6_tbw IS
END tv_6_tbw;

ARCHITECTURE testbench_arch OF tv_6_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\matlab6p5\work\isniamy\xspartan2\tv_6_tbw.ano";
	COMPONENT spartan2_clk_wrapper
		PORT (
			ce : In  std_logic;
			clk : In  std_logic;
			in_x_0 : In  std_logic_vector (15 DOWNTO 0);
			out_x_0 : Out  std_logic_vector (23 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL ce : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL in_x_0 : std_logic_vector (15 DOWNTO 0);
	SIGNAL out_x_0 : std_logic_vector (23 DOWNTO 0);

BEGIN
	UUT : spartan2_clk_wrapper
	PORT MAP (
		ce => ce,
		clk => clk,
		in_x_0 => in_x_0,
		out_x_0 => out_x_0
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_out_x_0(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",out_x_0,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, out_x_0);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clk <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_out_x_0(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clk <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		ce <= transport '1';
		in_x_0 <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		in_x_0 <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		in_x_0 <= transport std_logic_vector'("0000001100000000"); --300
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		in_x_0 <= transport std_logic_vector'("0000001100000000"); --300
		-- --------------------
		WAIT FOR 1000 ns; -- Time=1300 ns
		ce <= transport '1';
		-- --------------------
		WAIT FOR 3000 ns; -- Time=4300 ns
		ce <= transport '1';
		-- --------------------
		WAIT FOR 2600 ns; -- Time=6900 ns
		ce <= transport '1';
		-- --------------------
		WAIT FOR 1800 ns; -- Time=8700 ns
		ce <= transport '1';
		-- --------------------
		WAIT FOR 600 ns; -- Time=9300 ns
		ce <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=9500 ns
		ce <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=9600 ns
		ce <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=9700 ns
		ce <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=9800 ns
		ce <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=9900 ns
		ce <= transport '0';
		-- --------------------
		WAIT FOR 460 ns; -- Time=10360 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION spartan2_clk_wrapper_cfg OF tv_6_tbw IS
	FOR testbench_arch
	END FOR;
END spartan2_clk_wrapper_cfg;
