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-- System Generator version 6.2 vhdl source file.
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library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;

entity pid_test_clock_driver is 
  port (
    sysce: in std_logic;
    sysclk: in std_logic;
    ce_sg: out std_logic;
    clk_sg: out std_logic
  );
end pid_test_clock_driver;

architecture structural of pid_test_clock_driver is
  component xlclockdriver
    generic (
      period: integer := 1;
      use_bufg: boolean := false
    );
    port (
      sysce: in std_logic;
      sysclk: in std_logic;
      sysclr: in std_logic;
      ce: out std_logic;
      clk: out std_logic
    );
  end component;

  signal ce_sg_x_0: std_logic;
  signal clk_sg_x_0: std_logic;
  signal clk_sysgen: std_logic;

begin
  clk_sysgen <= sysclk;
  ce_sg <= ce_sg_x_0;
  clk_sg <= clk_sg_x_0;

  xlclockdriver1: xlclockdriver
    generic map (
      period => 1,
      use_bufg => false
    )
    port map (
      sysce => '1',
      sysclk => clk_sysgen,
      sysclr => '0',
      ce => ce_sg_x_0,
      clk => clk_sg_x_0
    );
end structural;
