-- C:\MATLAB6P5\WORK\ISNIAMY\XSPARTAN2
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Aug 21 15:02:50 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY count_1_tbw IS
END count_1_tbw;

ARCHITECTURE testbench_arch OF count_1_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\matlab6p5\work\isniamy\xspartan2\count_1_tbw.ano";
	COMPONENT counter
		PORT (
			in : In  bit;
			out : Out  vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL in : bit;
	SIGNAL out : vector (7 DOWNTO 0);

BEGIN
	UUT : counter
	PORT MAP (
		in => in,
		out => out
	);

	PROCESS -- clock process for in,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",out,"));
			STD.TEXTIO.write(TX_LOC, out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		in <= transport '0';
		WAIT FOR 1 ms;
		TX_TIME := TX_TIME + 1;
		in <= transport '1';
		WAIT FOR 1 ms;
		TX_TIME := TX_TIME + 1;
		ANNOTATE_out(TX_TIME);
		WAIT FOR 4 ms;
		TX_TIME := TX_TIME + 4;
		in <= transport '0';
		WAIT FOR 4 ms;
		TX_TIME := TX_TIME + 4;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for in
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		-- --------------------
		WAIT FOR 10 ms; -- Time=10 ms
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION counter_cfg OF count_1_tbw IS
	FOR testbench_arch
	END FOR;
END counter_cfg;
