
function simple1_sg_core_config(this_block)
  this_block.setTopLevelLanguage('VHDL');

  this_block.setEntityName('simple1_sg_core');
  this_block.addSimulinkInport('in_x_0');
  this_block.port('in_x_0').useHDLVector(true);

  this_block.addSimulinkOutport('out1');
  this_block.port('out1').useHDLVector(true);
  this_block.port('out1').setType('Fix_24_16');
  this_block.addSimulinkOutport('out2');
  this_block.port('out2').useHDLVector(true);
  this_block.port('out2').setType('Fix_24_16');
  this_block.addSimulinkOutport('out_x_0');
  this_block.port('out_x_0').useHDLVector(true);
  this_block.port('out_x_0').setType('Fix_24_16');

  this_block.tagAsCombinational;

% -----------------------------
  % Do input type checking, and dynamic output type and 
  % generic setup here.
  if (this_block.inputTypesKnown)
    if (~ strcmp('Fix_16_8', this_block.port('in_x_0').type))
      this_block.setError('Input data type for port "in_x_0" must be "Fix_16_8".');
    end
  end

% -----------------------------

% -----------------------------
% Do input rate checking here.
  if (this_block.inputRatesKnown)
    if (this_block.port('in_x_0').rate ~= 1)
      this_block.setError('Rate for port "in_x_0" must be 1.');
    end
  end

% -----------------------------

% -----------------------------
% Set output rates here.
  this_block.port('out1').setRate(1);
  this_block.port('out2').setRate(1);
  this_block.port('out_x_0').setRate(1);


% -----------------------------
% Set up clocks and clock enables here.
  this_block.addClkCEPair('clk_sg', 'ce_sg', 1);


% -----------------------------
% Set up vhdl/verilog files here.
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/conv_pkg.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/clock_pkg.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/synth_reg.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/synth_reg_w_init.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/xlclkprobe.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/xlclockdriver.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/xlclockgenerator.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/xlsl2slv.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/xlslv2sl.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/synth_addsub.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/simple1_sg_core_addsub1.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/synth_addsub.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/synth_addsub.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/synth_addsub.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/simple1_sg_core_kd.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/xldelay.vhd');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/simple1_sg_core.vhd');


% -----------------------------
% Set up .edn, .mif, .coe, ... files here.
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.edn');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/adder_subtracter_spartan2_6_0_86c498140491d6df.edn');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.edn');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/adder_subtracter_spartan2_6_0_9b2656d23c19deaf.edn');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/multiplier_spartan2_6_0_22d1b55eb2467aac.edn');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/multiplier_spartan2_6_0_e880a1b4a8ae9201.edn');
  this_block.addFile('C:/MATLAB6p5/work/isniamy/xcorecoba/temp/multiplier_spartan2_6_0_fe654cf32dc31d3a.edn');

