JDF G
// Created by Project Navigator ver 1.0
PROJECT test_pid_clk_wrapper.npl
DESIGN test_pid_clk_wrapper
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE test_pid_pkgs.vhd
SOURCE test_pid_files.vhd
SOURCE test_pid_clk_wrapper.vhd
STIMULUS test_pid_tbw.tbw
[STATUS-ALL]
test_pid_tbw.anoFile=ERRORS,0
[STRATEGY-LIST]
Normal=True
