
-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity test_pid_cmult3 is
  generic (
    core_name0: string := "";
    a_width: integer := 4;
    a_bin_pt: integer := 2;
    a_arith: integer := xlSigned;
    b_width: integer := 4;
    b_bin_pt: integer := 2;
    b_arith: integer := xlSigned;
    p_width: integer := 8;
    p_bin_pt: integer := 2;
    p_arith: integer := xlSigned;
    rst_width: integer := 1;
    rst_bin_pt: integer := 0;
    rst_arith: integer := xlUnsigned;
    en_width: integer := 1;
    en_bin_pt: integer := 0;
    en_arith: integer := xlUnsigned;
    latency: integer := 1;
    multsign: integer := xlSigned;
    quantization: integer := xlTruncate;
    overflow: integer := xlWrap;
    extra_registers: integer := 0;
    c_a_width: integer := 7;
    c_b_width: integer := 7;
    c_a_type: integer := 0;
    c_b_type: integer := 0;
    c_type: integer := 0;
    c_pipelined: integer := 1;
    bram_addr_width: integer := 8;
    c_baat: integer := 4;
    c_mult_type: integer := 0;
    c_has_q: integer := 1;
    c_has_nd: integer := 0;
    c_has_o: integer := 0;
    oversample: integer := 1;
    const_bin_pt: integer := 1;
    c_reg_inputs: integer := 0;
    c_enable_rlocs: integer := 1;
                -- synopsys translate_off
    c_b_value: string := "0";
                -- synopsys translate_on
    c_b_value_hi: integer := 0;
    c_b_value_low: integer := 0;
    c_has_b: integer := 0;
    c_has_loadb: integer := 0;
    c_b_constant: integer := 0;
    c_mem_type: integer := 0;
    c_output_width: integer := 16;
    c_output_hold: integer := 0
  );
  port (
    a: in std_logic_vector(a_width - 1 downto 0);
    ce: in std_logic;
    clr: in std_logic;
    clk: in std_logic;
    core_ce: in std_logic:= '0';
    core_clr: in std_logic:= '0';
    core_clk: in std_logic:= '0';
    rst: in std_logic_vector(rst_width - 1 downto 0);
    en: in std_logic_vector(en_width - 1 downto 0);
    p: out std_logic_vector(p_width - 1 downto 0)
  );
end test_pid_cmult3;
architecture behavior of test_pid_cmult3 is
  component synth_reg
    generic (
      width: integer := 16;
      latency: integer := 5
    );
    port (
      i: in std_logic_vector(width - 1 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      o: out std_logic_vector(width - 1 downto 0)
    );
  end component;
  signal tmp_a: std_logic_vector(c_a_width - 1 downto 0);
  signal tmp_p: std_logic_vector(c_output_width - 1 downto 0);
  signal conv_p: std_logic_vector(p_width - 1 downto 0);
  -- synopsys translate_off
  signal real_a, real_p: real;
  -- synopsys translate_on
  signal nd: std_logic;
  signal internal_ce: std_logic;
  signal internal_clr: std_logic;
  signal internal_core_ce: std_logic;
  component multiplier_spartan2_6_0_4db32212508f9e05
    port (
      o: out std_logic_vector(c_output_width - 1 downto 0);
      a: in std_logic_vector(c_a_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of multiplier_spartan2_6_0_4db32212508f9e05:
    component is true;
  attribute fpga_dont_touch of multiplier_spartan2_6_0_4db32212508f9e05:
    component is "true";
  attribute box_type of multiplier_spartan2_6_0_4db32212508f9e05:
    component  is "black_box";
  component multiplier_spartan2_6_0_7b47885db091842a
    port (
      o: out std_logic_vector(c_output_width - 1 downto 0);
      a: in std_logic_vector(c_a_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of multiplier_spartan2_6_0_7b47885db091842a:
    component is true;
  attribute fpga_dont_touch of multiplier_spartan2_6_0_7b47885db091842a:
    component is "true";
  attribute box_type of multiplier_spartan2_6_0_7b47885db091842a:
    component  is "black_box";
  component multiplier_spartan2_6_0_e880a1b4a8ae9201
    port (
      o: out std_logic_vector(c_output_width - 1 downto 0);
      a: in std_logic_vector(c_a_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of multiplier_spartan2_6_0_e880a1b4a8ae9201:
    component is true;
  attribute fpga_dont_touch of multiplier_spartan2_6_0_e880a1b4a8ae9201:
    component is "true";
  attribute box_type of multiplier_spartan2_6_0_e880a1b4a8ae9201:
    component  is "black_box";
  component multiplier_spartan2_6_0_22d1b55eb2467aac
    port (
      o: out std_logic_vector(c_output_width - 1 downto 0);
      a: in std_logic_vector(c_a_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of multiplier_spartan2_6_0_22d1b55eb2467aac:
    component is true;
  attribute fpga_dont_touch of multiplier_spartan2_6_0_22d1b55eb2467aac:
    component is "true";
  attribute box_type of multiplier_spartan2_6_0_22d1b55eb2467aac:
    component  is "black_box";
begin
  -- synopsys translate_off
  -- synopsys translate_on
  input_process: process(a)
    variable tmp_p_bin_pt, tmp_p_arith: integer;
  begin
    tmp_a <= zero_ext(a, c_a_width);
  end process;
  output_process: process(tmp_p)
  begin
    conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign,
                           p_width, p_bin_pt, p_arith, quantization, overflow);
  end process;
  internal_ce <= ce and en(0);
  internal_core_ce <= core_ce and en(0);
  internal_clr <= (clr or rst(0)) and ce;
  nd <= internal_ce;
  comp0: if (not simulating and
             (core_name0 = "multiplier_spartan2_6_0_4db32212508f9e05")) generate
    core_instance0: multiplier_spartan2_6_0_4db32212508f9e05
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_off
  comp1: if (simulating and
             (core_name0 = "multiplier_spartan2_6_0_4db32212508f9e05")) generate
    core_instance1: entity XilinxCoreLib.mult_gen_v6_0(behavioral)
      generic map (
        c_baat => c_baat,
        c_a_type => c_a_type,
        c_sync_enable => 1,
        c_mult_type => c_mult_type,
        c_b_type => c_b_type,
        c_use_luts => 1,
        c_b_width => c_b_width,
        c_stack_adders => 1,
        c_has_rfd => c_has_nd,
        c_has_q => c_has_q,
        c_has_load_done => 0,
        c_has_o => c_has_o,
        c_has_a_signed => 0,
        c_has_b => c_has_b,
        c_has_sclr => c_has_q,
        c_mem_init_prefix => "mem",
        c_b_value => c_b_value,
        c_has_loadb => c_has_loadb,
        c_mem_type => c_mem_type,
        c_out_width => c_output_width,
        c_a_width =>c_a_width,
        c_b_constant => c_b_constant,
        c_reg_a_b_inputs => c_reg_inputs,
        c_has_nd => c_has_nd,
        c_output_hold => c_output_hold,
        c_has_ce => c_has_q,
        c_has_swapb => 0,
        c_has_aclr => 0,
        c_sqm_type => 0,
        c_pipeline => c_pipelined,
        c_enable_rlocs => c_enable_rlocs,
        bram_addr_width => bram_addr_width,
        c_has_rdy => c_has_nd
      )
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_on
  comp2: if (not simulating and
             (core_name0 = "multiplier_spartan2_6_0_7b47885db091842a")) generate
    core_instance2: multiplier_spartan2_6_0_7b47885db091842a
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_off
  comp3: if (simulating and
             (core_name0 = "multiplier_spartan2_6_0_7b47885db091842a")) generate
    core_instance3: entity XilinxCoreLib.mult_gen_v6_0(behavioral)
      generic map (
        c_baat => c_baat,
        c_a_type => c_a_type,
        c_sync_enable => 1,
        c_mult_type => c_mult_type,
        c_b_type => c_b_type,
        c_use_luts => 1,
        c_b_width => c_b_width,
        c_stack_adders => 1,
        c_has_rfd => c_has_nd,
        c_has_q => c_has_q,
        c_has_load_done => 0,
        c_has_o => c_has_o,
        c_has_a_signed => 0,
        c_has_b => c_has_b,
        c_has_sclr => c_has_q,
        c_mem_init_prefix => "mem",
        c_b_value => c_b_value,
        c_has_loadb => c_has_loadb,
        c_mem_type => c_mem_type,
        c_out_width => c_output_width,
        c_a_width =>c_a_width,
        c_b_constant => c_b_constant,
        c_reg_a_b_inputs => c_reg_inputs,
        c_has_nd => c_has_nd,
        c_output_hold => c_output_hold,
        c_has_ce => c_has_q,
        c_has_swapb => 0,
        c_has_aclr => 0,
        c_sqm_type => 0,
        c_pipeline => c_pipelined,
        c_enable_rlocs => c_enable_rlocs,
        bram_addr_width => bram_addr_width,
        c_has_rdy => c_has_nd
      )
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_on
  comp4: if (not simulating and
             (core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201")) generate
    core_instance4: multiplier_spartan2_6_0_e880a1b4a8ae9201
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_off
  comp5: if (simulating and
             (core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201")) generate
    core_instance5: entity XilinxCoreLib.mult_gen_v6_0(behavioral)
      generic map (
        c_baat => c_baat,
        c_a_type => c_a_type,
        c_sync_enable => 1,
        c_mult_type => c_mult_type,
        c_b_type => c_b_type,
        c_use_luts => 1,
        c_b_width => c_b_width,
        c_stack_adders => 1,
        c_has_rfd => c_has_nd,
        c_has_q => c_has_q,
        c_has_load_done => 0,
        c_has_o => c_has_o,
        c_has_a_signed => 0,
        c_has_b => c_has_b,
        c_has_sclr => c_has_q,
        c_mem_init_prefix => "mem",
        c_b_value => c_b_value,
        c_has_loadb => c_has_loadb,
        c_mem_type => c_mem_type,
        c_out_width => c_output_width,
        c_a_width =>c_a_width,
        c_b_constant => c_b_constant,
        c_reg_a_b_inputs => c_reg_inputs,
        c_has_nd => c_has_nd,
        c_output_hold => c_output_hold,
        c_has_ce => c_has_q,
        c_has_swapb => 0,
        c_has_aclr => 0,
        c_sqm_type => 0,
        c_pipeline => c_pipelined,
        c_enable_rlocs => c_enable_rlocs,
        bram_addr_width => bram_addr_width,
        c_has_rdy => c_has_nd
      )
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_on
  comp6: if (not simulating and
             (core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac")) generate
    core_instance6: multiplier_spartan2_6_0_22d1b55eb2467aac
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_off
  comp7: if (simulating and
             (core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac")) generate
    core_instance7: entity XilinxCoreLib.mult_gen_v6_0(behavioral)
      generic map (
        c_baat => c_baat,
        c_a_type => c_a_type,
        c_sync_enable => 1,
        c_mult_type => c_mult_type,
        c_b_type => c_b_type,
        c_use_luts => 1,
        c_b_width => c_b_width,
        c_stack_adders => 1,
        c_has_rfd => c_has_nd,
        c_has_q => c_has_q,
        c_has_load_done => 0,
        c_has_o => c_has_o,
        c_has_a_signed => 0,
        c_has_b => c_has_b,
        c_has_sclr => c_has_q,
        c_mem_init_prefix => "mem",
        c_b_value => c_b_value,
        c_has_loadb => c_has_loadb,
        c_mem_type => c_mem_type,
        c_out_width => c_output_width,
        c_a_width =>c_a_width,
        c_b_constant => c_b_constant,
        c_reg_a_b_inputs => c_reg_inputs,
        c_has_nd => c_has_nd,
        c_output_hold => c_output_hold,
        c_has_ce => c_has_q,
        c_has_swapb => 0,
        c_has_aclr => 0,
        c_sqm_type => 0,
        c_pipeline => c_pipelined,
        c_enable_rlocs => c_enable_rlocs,
        bram_addr_width => bram_addr_width,
        c_has_rdy => c_has_nd
      )
      port map (
      o => tmp_p,
      a => tmp_a
      );
  end generate;
-- synopsys translate_on
  latency_gt_0: if (extra_registers > 0) and
                    not ((c_b_value_low = 0) and (c_b_value_hi = 0))
  generate
    reg: synth_reg
      generic map (
        width => p_width,
        latency => extra_registers
      )
      port map (
        i => conv_p,
        ce => internal_ce,
        clr => internal_clr,
        clk => clk,
        o => p
      );
  end generate;
  latency0: if ((latency = 0) or (extra_registers = 0)) and
                not((c_b_value_low = 0) and (c_b_value_hi = 0))
  generate
    p <= conv_p;
  end generate latency0;
  zero_constant: if (c_b_value_low = 0)and (c_b_value_hi = 0)
  generate
    p <= integer_to_std_logic_vector(0,p_width,p_arith);
  end generate zero_constant;
end architecture behavior;
