# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do coba_tbw.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity coba_addsub
# -- Compiling architecture behavior of coba_addsub
# -- Loading entity synth_addsub
# WARNING[1]: coba_files.vhd(1448): No default binding for component: "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53". (No entity named "adder_subtracter_spartan2_6_0_565e6fc4f8af6f53" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# -- Compiling entity coba
# -- Compiling architecture structural of coba
# -- Loading entity coba_addsub
# -- Loading entity xlsl2slv
# -- Compiling entity coba_clock_driver
# -- Compiling architecture structural of coba_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity coba_clk_wrapper
# -- Compiling architecture structural of coba_clk_wrapper
# -- Loading entity coba_clock_driver
# -- Loading entity coba
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity coba_tbw
# -- Compiling architecture testbench_arch of coba_tbw
# -- Loading entity coba_clk_wrapper
# -- Compiling configuration coba_clk_wrapper_cfg
# -- Loading entity coba_tbw
# -- Loading architecture testbench_arch of coba_tbw
# vsim -lib work -t 1ps coba_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.coba_tbw(testbench_arch)
# Loading work.coba_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.coba_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.coba(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.coba_addsub(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 1378 statements or 3 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# .wave
# .structure
# .signals
# ** Failure: Simulation successful (not a failure).  No problems detected. 
#    Time: 810 ns  Iteration: 0  Process: /coba_tbw/line__69 File: coba_tbw.vhw
# Break at coba_tbw.vhw line 166
# Simulation Breakpoint: Break at coba_tbw.vhw line 166
# MACRO ./coba_tbw.fdo PAUSED at line 15
run
run -all
# ** Error: Error at time=20ns gateway_out1=0000000100110011, Expected = 0000000110000100 
#    Time: 830 ns  Iteration: 0  Instance: /coba_tbw
# ** Error: Error at time=120ns gateway_out1=0000000110000100, Expected = 0000000101010110 
#    Time: 930 ns  Iteration: 0  Instance: /coba_tbw
# ** Error: Error at time=220ns gateway_out1=0000000101010110, Expected = 0000000111110010 
#    Time: 1030 ns  Iteration: 0  Instance: /coba_tbw
# ** Error: Error at time=320ns gateway_out1=0000000111110010, Expected = 0000000111011000 
#    Time: 1130 ns  Iteration: 0  Instance: /coba_tbw
# ** Error: Error at time=420ns gateway_out1=0000000111011000, Expected = 0000000111001011 
#    Time: 1230 ns  Iteration: 0  Instance: /coba_tbw
# ** Error: Error at time=520ns gateway_out1=0000000111001011, Expected = 0000000111001010 
#    Time: 1330 ns  Iteration: 0  Instance: /coba_tbw
# ** Error: Error at time=620ns gateway_out1=0000000111001010, Expected = 0000000100010111 
#    Time: 1430 ns  Iteration: 0  Instance: /coba_tbw
# ** Error: Error at time=720ns gateway_out1=0000000100010111, Expected = 0000000100110011 
#    Time: 1530 ns  Iteration: 0  Instance: /coba_tbw
# ** Failure: Errors found during simulation
#    Time: 1620 ns  Iteration: 0  Process: /coba_tbw/line__69 File: coba_tbw.vhw
# Break at coba_tbw.vhw line 177
# WARNING: No extended dataflow License exists
# highlight: Cannot find net /clock_pkg/int_clk
run
destroy .signals
destroy .structure
destroy .wave
