source {C:/xilinx_62i/data/projnav/scripts/VsimStopServer.tcl}
initIPC 1200
-- Auto Generated by Project Navigator to simulate
-- HDL Bencher Annotated Test Bench
--
vlib work
onbreak {resume}
onerror {quit -code 99 -force}
onElabError {resume}
vlog  counter.v
vcom -93 -explicit  count_1_tbw.ant
vlog  "C:/xilinx_62i/verilog/src/glbl.v"
vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver  -lib work count_1_tbw glbl
run -all
quit -force
