Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_pkgs.vhd in Library work.
Compiling vhdl file C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <pid_sg_full_001_editki_addsub1> (Architecture <behavior>) compiled.
Entity <pid_sg_full_001_editki_cmult3> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <pid_sg_full_001_editki> (Architecture <structural>) compiled.
Entity <pid_sg_full_001_editki_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_clk_wrapper.vhd in Library work.
Entity <pid_sg_full_001_editki_clk_wrapper> (Architecture <structural>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <pid_sg_full_001_editki_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <pid_sg_full_001_editki_clk_wrapper> analyzed. Unit <pid_sg_full_001_editki_clk_wrapper> generated.

Analyzing Entity <pid_sg_full_001_editki_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 3574: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <pid_sg_full_001_editki_clock_driver> analyzed. Unit <pid_sg_full_001_editki_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <pid_sg_full_001_editki> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2599: Unconnected input port 'c_in' of component 'pid_sg_full_001_editki_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2599: Unconnected output port 'c_out' of component 'pid_sg_full_001_editki_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2654: Unconnected input port 'c_in' of component 'pid_sg_full_001_editki_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2654: Unconnected output port 'c_out' of component 'pid_sg_full_001_editki_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2709: Unconnected input port 'c_in' of component 'pid_sg_full_001_editki_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2709: Unconnected output port 'c_out' of component 'pid_sg_full_001_editki_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2764: Unconnected input port 'c_in' of component 'pid_sg_full_001_editki_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2764: Unconnected output port 'c_out' of component 'pid_sg_full_001_editki_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2819: Unconnected input port 'c_in' of component 'pid_sg_full_001_editki_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2819: Unconnected output port 'c_out' of component 'pid_sg_full_001_editki_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2874: Unconnected input port 'c_in' of component 'pid_sg_full_001_editki_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2874: Unconnected output port 'c_out' of component 'pid_sg_full_001_editki_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2929: Unconnected input port 'core_ce' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2929: Unconnected input port 'core_clr' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 2929: Unconnected input port 'core_clk' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 3064: Unconnected input port 'core_ce' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 3064: Unconnected input port 'core_clr' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 3064: Unconnected input port 'core_clk' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 3121: Unconnected input port 'core_ce' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 3121: Unconnected input port 'core_clr' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 3121: Unconnected input port 'core_clk' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 3178: Unconnected input port 'core_ce' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 3178: Unconnected input port 'core_clr' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd line 3178: Unconnected input port 'core_clk' of component 'pid_sg_full_001_editki_cmult3' is tied to default value.
Entity <pid_sg_full_001_editki> analyzed. Unit <pid_sg_full_001_editki> generated.

Analyzing generic Entity <pid_sg_full_001_editki_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_438ebd1a25415d4b"
	a_width = 16
	a_bin_pt = 4
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 12
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 1
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 33
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 33
	c_b_width = 33
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 33
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid_sg_full_001_editki_addsub1> analyzed. Unit <pid_sg_full_001_editki_addsub1> generated.

Analyzing generic Entity <pid_sg_full_001_editki_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_db876aab0a40a0ba"
	a_width = 16
	a_bin_pt = 8
	a_arith = 1
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 4
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 21
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 21
	c_b_width = 21
	c_a_type = 1
	c_b_type = 1
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 21
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid_sg_full_001_editki_addsub1> analyzed. Unit <pid_sg_full_001_editki_addsub10> generated.

Analyzing generic Entity <pid_sg_full_001_editki_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 4
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 4
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid_sg_full_001_editki_addsub1> analyzed. Unit <pid_sg_full_001_editki_addsub11> generated.

Analyzing generic Entity <pid_sg_full_001_editki_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_7cca55ed6e8c313f"
	a_width = 18
	a_bin_pt = 8
	a_arith = 1
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 15
	b_arith = 2
	s_width = 19
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 33
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 33
	c_b_width = 33
	c_a_type = 1
	c_b_type = 1
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 33
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid_sg_full_001_editki_addsub1> analyzed. Unit <pid_sg_full_001_editki_addsub12> generated.

Analyzing generic Entity <pid_sg_full_001_editki_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_199c1e18e4579dff"
	a_width = 35
	a_bin_pt = 16
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 34
	b_bin_pt = 18
	b_arith = 2
	s_width = 18
	s_bin_pt = 8
	s_arith = 1
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 38
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 38
	c_b_width = 38
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 38
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid_sg_full_001_editki_addsub1> analyzed. Unit <pid_sg_full_001_editki_addsub13> generated.

Analyzing generic Entity <pid_sg_full_001_editki_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_bfeb857b6aedd324"
	a_width = 19
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 20
	b_bin_pt = 8
	b_arith = 2
	s_width = 20
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 21
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 21
	c_b_width = 21
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 21
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid_sg_full_001_editki_addsub1> analyzed. Unit <pid_sg_full_001_editki_addsub14> generated.

Analyzing generic Entity <pid_sg_full_001_editki_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_c898a6c13135c6d0"
	a_width = 16
	a_bin_pt = 4
	a_arith = 2
	b_width = 4
	b_bin_pt = 8
	b_arith = 2
	p_width = 32
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 10
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 8
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 512
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid_sg_full_001_editki_cmult3> analyzed. Unit <pid_sg_full_001_editki_cmult3> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 4
	d_arith = 2
	q_width = 16
	q_bin_pt = 4
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 20
	d_bin_pt = 8
	d_arith = 2
	q_width = 20
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay5> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 20
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg9> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 20
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e10> generated.

Analyzing generic Entity <pid_sg_full_001_editki_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_7d52cda8234e03c2"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 8
	b_arith = 2
	p_width = 35
	p_bin_pt = 16
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 16
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 8
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 49920
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 35
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid_sg_full_001_editki_cmult3> analyzed. Unit <pid_sg_full_001_editki_cmult36> generated.

Analyzing generic Entity <pid_sg_full_001_editki_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_3bd317e4907e929e"
	a_width = 16
	a_bin_pt = 4
	a_arith = 2
	b_width = 4
	b_bin_pt = 14
	b_arith = 2
	p_width = 34
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 8
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 14
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 164
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 34
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid_sg_full_001_editki_cmult3> analyzed. Unit <pid_sg_full_001_editki_cmult37> generated.

Analyzing generic Entity <pid_sg_full_001_editki_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_6f13cc9ee672d655"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 7
	b_arith = 2
	p_width = 32
	p_bin_pt = 15
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 10
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 7
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 559
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid_sg_full_001_editki_cmult3> analyzed. Unit <pid_sg_full_001_editki_cmult38> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


Reading constraint file .\pid_sg_full_001_editki_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e10>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
Unit <srl17e10> synthesized.


Synthesizing Unit <synth_reg9>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg9> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_cmult38>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <pid_sg_full_001_editki_cmult38> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_cmult37>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <pid_sg_full_001_editki_cmult37> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_cmult36>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <pid_sg_full_001_editki_cmult36> synthesized.


Synthesizing Unit <xldelay5>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
Unit <xldelay5> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_cmult3>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <pid_sg_full_001_editki_cmult3> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_addsub14>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<20>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid_sg_full_001_editki_addsub14> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_addsub13>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<37:28>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<9:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid_sg_full_001_editki_addsub13> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_addsub12>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<32:26>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<6:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid_sg_full_001_editki_addsub12> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_addsub11>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16:12>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid_sg_full_001_editki_addsub11> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_addsub10>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<20:17>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid_sg_full_001_editki_addsub10> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_addsub1>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<32:20>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<3:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid_sg_full_001_editki_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <pid_sg_full_001_editki>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
Unit <pid_sg_full_001_editki> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_clock_driver>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <pid_sg_full_001_editki_clock_driver> synthesized.


Synthesizing Unit <pid_sg_full_001_editki_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <pid_sg_full_001_editki_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <pid_sg_full_001_editki_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_438ebd1a25415d4b.edn" "adder_subtracter_spartan2_6_0_438ebd1a25415d4b.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_438ebd1a25415d4b.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_db876aab0a40a0ba.edn" "adder_subtracter_spartan2_6_0_db876aab0a40a0ba.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_db876aab0a40a0ba.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_86c498140491d6df.edn" "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_7cca55ed6e8c313f.edn" "adder_subtracter_spartan2_6_0_7cca55ed6e8c313f.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_7cca55ed6e8c313f.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_199c1e18e4579dff.edn" "adder_subtracter_spartan2_6_0_199c1e18e4579dff.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_199c1e18e4579dff.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_bfeb857b6aedd324.edn" "adder_subtracter_spartan2_6_0_bfeb857b6aedd324.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_bfeb857b6aedd324.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_c898a6c13135c6d0.edn" "multiplier_spartan2_6_0_c898a6c13135c6d0.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_c898a6c13135c6d0.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_7d52cda8234e03c2.edn" "multiplier_spartan2_6_0_7d52cda8234e03c2.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_7d52cda8234e03c2.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_3bd317e4907e929e.edn" "multiplier_spartan2_6_0_3bd317e4907e929e.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_3bd317e4907e929e.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_6f13cc9ee672d655.edn" "multiplier_spartan2_6_0_6f13cc9ee672d655.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_6f13cc9ee672d655.ngo"...
Loading core <adder_subtracter_spartan2_6_0_438ebd1a25415d4b> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_db876aab0a40a0ba> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_7cca55ed6e8c313f> for timing and area information for instance <core_instance6>.
Loading core <adder_subtracter_spartan2_6_0_199c1e18e4579dff> for timing and area information for instance <core_instance8>.
Loading core <adder_subtracter_spartan2_6_0_bfeb857b6aedd324> for timing and area information for instance <core_instance10>.
Loading core <multiplier_spartan2_6_0_c898a6c13135c6d0> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_7d52cda8234e03c2> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_3bd317e4907e929e> for timing and area information for instance <core_instance4>.
Loading core <multiplier_spartan2_6_0_6f13cc9ee672d655> for timing and area information for instance <core_instance6>.

Optimizing unit <pid_sg_full_001_editki_clk_wrapper> ...

Optimizing unit <srl17e10> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\pid_sg_full_001_editki_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block pid_sg_full_001_editki_clk_wrapper, actual ratio is 34.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     262  out of    768    34%  
 Number of Slice Flip Flops:            52  out of   1536     3%  
 Number of 4 input LUTs:               433  out of   1536    28%  
 Number of bonded IOBs:                 36  out of    144    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 52    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 29.099ns (Maximum Frequency: 34.365MHz)
   Minimum input arrival time before clock: 25.365ns
   Maximum output required time after clock: 34.264ns
   Maximum combinational path delay: 30.530ns

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
c:\matlab6p5\work\xpid_sg_full_001_editki/_ngo -i -p xc2s50-pq208-6
pid_sg_full_001_editki_clk_wrapper.ngc pid_sg_full_001_editki_clk_wrapper.ngd 

Reading NGO file
"C:/MATLAB6p5/work/xpid_sg_full_001_editKi/pid_sg_full_001_editki_clk_wrapper.ng
c" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_438ebd1a25415d4b.edn"
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_43
8ebd1a25415d4b.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid_sg_full_001_editki/_ngo/adder_subtracter_spartan2_6_0_43
8ebd1a25415d4b.ngo"...
Loading design module
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_43
8ebd1a25415d4b.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_db876aab0a40a0ba.edn"
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_db
876aab0a40a0ba.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid_sg_full_001_editki/_ngo/adder_subtracter_spartan2_6_0_db
876aab0a40a0ba.ngo"...
Loading design module
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_db
876aab0a40a0ba.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_86c498140491d6df.edn"
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_86
c498140491d6df.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid_sg_full_001_editki/_ngo/adder_subtracter_spartan2_6_0_86
c498140491d6df.ngo"...
Loading design module
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_86
c498140491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_7cca55ed6e8c313f.edn"
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_7c
ca55ed6e8c313f.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid_sg_full_001_editki/_ngo/adder_subtracter_spartan2_6_0_7c
ca55ed6e8c313f.ngo"...
Loading design module
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_7c
ca55ed6e8c313f.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_199c1e18e4579dff.edn"
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_19
9c1e18e4579dff.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid_sg_full_001_editki/_ngo/adder_subtracter_spartan2_6_0_19
9c1e18e4579dff.ngo"...
Loading design module
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_19
9c1e18e4579dff.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_bfeb857b6aedd324.edn"
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_bf
eb857b6aedd324.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid_sg_full_001_editki/_ngo/adder_subtracter_spartan2_6_0_bf
eb857b6aedd324.ngo"...
Loading design module
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\adder_subtracter_spartan2_6_0_bf
eb857b6aedd324.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_c898a6c13135c6d0.edn"
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\multiplier_spartan2_6_0_c898a6c1
3135c6d0.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid_sg_full_001_editki/_ngo/multiplier_spartan2_6_0_c898a6c1
3135c6d0.ngo"...
Loading design module
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\multiplier_spartan2_6_0_c898a6c1
3135c6d0.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_7d52cda8234e03c2.edn"
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\multiplier_spartan2_6_0_7d52cda8
234e03c2.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid_sg_full_001_editki/_ngo/multiplier_spartan2_6_0_7d52cda8
234e03c2.ngo"...
Loading design module
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\multiplier_spartan2_6_0_7d52cda8
234e03c2.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_3bd317e4907e929e.edn"
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\multiplier_spartan2_6_0_3bd317e4
907e929e.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid_sg_full_001_editki/_ngo/multiplier_spartan2_6_0_3bd317e4
907e929e.ngo"...
Loading design module
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\multiplier_spartan2_6_0_3bd317e4
907e929e.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_6f13cc9ee672d655.edn"
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\multiplier_spartan2_6_0_6f13cc9e
e672d655.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid_sg_full_001_editki/_ngo/multiplier_spartan2_6_0_6f13cc9e
e672d655.ngo"...
Loading design module
"c:\matlab6p5\work\xpid_sg_full_001_editki\_ngo\multiplier_spartan2_6_0_6f13cc9e
e672d655.ngo"...
mult_gen_v6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(20)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(21)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(22)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(23)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(24)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(25)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(26)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(27)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(28)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(29)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(30)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(31)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub1_core_instance0/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub2_core_instance2/S(17)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub2_core_instance2/S(18)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub2_core_instance2/S(19)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub2_core_instance2/S(20)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub3_core_instance4/S(12)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub3_core_instance4/S(13)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub3_core_instance4/S(14)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub3_core_instance4/S(15)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub3_core_instance4/S(16)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(26)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(27)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(28)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(29)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(30)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(31)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub4_core_instance6/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(0)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(1)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(2)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(3)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(4)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(5)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(6)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(7)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(8)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(9)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(28)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(29)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(30)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(31)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(32)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(33)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(34)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(35)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(36)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub5_core_instance8/S(37)' has no load
WARNING:NgdBuild:454 - logical net
   'pid_sg_full_001_editki_top_addsub6_core_instance10/S(20)' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  61

Total memory usage is 39788 kilobytes

Writing NGD file "pid_sg_full_001_editki_clk_wrapper.ngd" ...

Writing NGDBUILD log file "pid_sg_full_001_editki_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        32 out of  1,536    2%
  Number of 4 input LUTs:           322 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         180 out of    768   23%
    Number of Slices containing only related logic:    180 out of    180  100%
    Number of Slices containing unrelated logic:         0 out of    180    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:       322 out of  1,536   20%
   Number of bonded IOBs:            36 out of    140   25%
      IOB Flip Flops:                              12
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            8
Total equivalent gate count for design:  3,580
Additional JTAG gate count for IOBs:  1,776
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "pid_sg_full_001_editki_clk_wrapper_map.mrp" for details.
Completed process "Map".

Mapping Module pid_sg_full_001_editki_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o pid_sg_full_001_editki_clk_wrapper_map.ncd pid_sg_full_001_editki_clk_wrapper.ngd pid_sg_full_001_editki_clk_wrapper.pcf
Mapping Module pid_sg_full_001_editki_clk_wrapper: DONE



Started process "Place & Route".





Constraints file: pid_sg_full_001_editki_clk_wrapper.pcf

Loading device database for application Par from file
"pid_sg_full_001_editki_clk_wrapper_map.ncd".
   "pid_sg_full_001_editki_clk_wrapper" is an NCD, version 2.38, device xc2s50,
package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            36 out of 140    25%
      Number of LOCed External IOBs    0 out of 36      0%

   Number of SLICEs                  180 out of 768    23%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 3 secs 


Phase 1.1
Phase 1.1 (Checksum:989930) REAL time: 3 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.8
.....
.
Phase 5.8 (Checksum:9d0e3f) REAL time: 4 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 4 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs 

Writing design to file pid_sg_full_001_editki_clk_wrapper.ncd.

Total REAL time to Placer completion: 5 secs 
Total CPU time to Placer completion: 3 secs 


Phase 1: 891 unrouted;       REAL time: 6 secs 

Phase 2: 863 unrouted;       REAL time: 6 secs 

Phase 3: 123 unrouted;       REAL time: 7 secs 

Phase 4: 123 unrouted; (0)      REAL time: 7 secs 

Phase 5: 123 unrouted; (0)      REAL time: 7 secs 

Phase 6: 123 unrouted; (0)      REAL time: 7 secs 

Phase 7: 0 unrouted; (0)      REAL time: 7 secs 

Total REAL time to Router completion: 8 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   28   |  0.078     |  0.463      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_022824d9 = PERIOD TIMEGRP "clk_022 | 100.000ns  | 27.888ns   | 13   
  824d9"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 12 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  55 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file pid_sg_full_001_editki_clk_wrapper.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sun Mar 27 22:29:56 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module pid_sg_full_001_editki_clk_wrapper . . .
PAR command line: par -w -intstyle ise -ol std -t 1 pid_sg_full_001_editki_clk_wrapper_map.ncd pid_sg_full_001_editki_clk_wrapper.ncd pid_sg_full_001_editki_clk_wrapper.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



