library verilog;
use verilog.vl_types.all;
entity seg7_driver is
    port(
        clk_200hz       : in     vl_logic;
        reset           : in     vl_logic;
        dig0            : in     vl_logic_vector(7 downto 0);
        dig1            : in     vl_logic_vector(7 downto 0);
        dig2            : in     vl_logic_vector(7 downto 0);
        anode0          : out    vl_logic;
        anode1          : out    vl_logic;
        anode2          : out    vl_logic;
        anode3          : out    vl_logic;
        digit           : out    vl_logic_vector(7 downto 0)
    );
end seg7_driver;
