library ieee;
use ieee.std_logic_1164.all;

--******************************************************************************
--**** ENTITY exmem_c
--**** Deskripsi: Entity ini menguraikan EXMEM stage control pipeline
--****            register. Semua nilai akan dituliskan ke register ini pada
--****            clock positif.
--******************************************************************************
ENTITY exmem_c IS
    PORT(clk                                : IN STD_LOGIC;
         wbIn                               : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
         exmemIn                            : IN STD_LOGIC;
         memstageIn                         : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
         wb                                 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
         exmem                              : OUT STD_LOGIC;
         memstageOut                        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END ENTITY exmem_c;

ARCHITECTURE exmemc_behav OF exmem_c IS
BEGIN
    name : PROCESS(clk) IS
        VARIABLE regValue : STD_LOGIC_VECTOR(5 DOWNTO 0);
    BEGIN
        
        -- On the postive clock edge write the values to the register.
        IF(clk='1') THEN
            regValue(5 DOWNTO 0) := wbIn & exmemIn & memstageIn(1 DOWNTO 0);
        END IF;
        
        wb <= regValue(5 downto 3);             -- Control lines for WB stage
        exmem <= regValue(2);                   -- Ouput enable
        memstageOut <= regValue(1 downto 0);    -- Memory Stage Control Lines
        
    END PROCESS name;
END ARCHITECTURE exmemc_behav;
