# Xilinx CORE Generator 6.2i
# User = WinXp
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in C:\MATLAB6p5\work\isniamy\xpid_data2\temp\coregen_tmp\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=C:\MATLAB6p5\work\isniamy\xpid_data2\temp\coregen_tmp
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Spartan2
# outputoption=DesignFlow
# overwritefiles=True
# simvendor=ModelSim
# expandedprojectpath=C:\MATLAB6p5\work\isniamy\xpid_data2\temp\coregen_tmp

SETPROJECT ./
Set current Project to C:\MATLAB6p5\work\isniamy\xpid_data2\temp\coregen_tmp
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = true
CSET latency = 0
CSET operation = subtract
CSET output_options = non_registered
CSET output_width = 35
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 35
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 35
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_3c5aefdfc1b01b25
GENERATE
Preparing to elaborate core...
Elaborating the module...
Generating the core .EDN implementation netlist...
 

SETPROJECT ./
Set current Project to C:\MATLAB6p5\work\isniamy\xpid_data2\temp\coregen_tmp
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = false
CSET latency = 0
CSET operation = add
CSET output_options = non_registered
CSET output_width = 25
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 25
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 25
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_5f14a66727c3a329
GENERATE
Preparing to elaborate core...
Elaborating the module...
Generating the core .EDN implementation netlist...
 

SETPROJECT ./
Set current Project to C:\MATLAB6p5\work\isniamy\xpid_data2\temp\coregen_tmp
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = true
CSET latency = 0
CSET operation = add
CSET output_options = non_registered
CSET output_width = 50
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 50
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 50
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_a29cdc21716c36c2
GENERATE
Preparing to elaborate core...
Elaborating the module...
Generating the core .EDN implementation netlist...
 

SETPROJECT ./
Set current Project to C:\MATLAB6p5\work\isniamy\xpid_data2\temp\coregen_tmp
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET asynchronous_clear = false
CSET clk_cycles_per_input = 1
CSET clock_enable = false
CSET create_rpm = true
CSET memory_type = Distributed_Memory
CSET multiplier_type = Parallel
CSET nd = false
CSET output_hold_register = false
CSET output_options = Non_Registered
CSET output_width = 34
CSET pipelined = Minimum
CSET port_a_data = Signed
CSET port_a_width = 16
CSET port_b_constant = true
CSET port_b_constant_value = 26
CSET port_b_data = Unsigned
CSET port_b_width = 5
CSET rdy = false
CSET register_input = false
CSET reloadable = false
CSET rfd = false
CSET style = Rectangular_Shape
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_036246fc9fb44e5b
GENERATE
Preparing to elaborate core...
Elaborating the module...
Generating the core .EDN implementation netlist...
 

SETPROJECT ./
Set current Project to C:\MATLAB6p5\work\isniamy\xpid_data2\temp\coregen_tmp
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET asynchronous_clear = false
CSET clk_cycles_per_input = 1
CSET clock_enable = false
CSET create_rpm = true
CSET memory_type = Distributed_Memory
CSET multiplier_type = Parallel
CSET nd = false
CSET output_hold_register = false
CSET output_options = Non_Registered
CSET output_width = 41
CSET pipelined = Minimum
CSET port_a_data = Signed
CSET port_a_width = 25
CSET port_b_constant = true
CSET port_b_constant_value = 780
CSET port_b_data = Unsigned
CSET port_b_width = 10
CSET rdy = false
CSET register_input = false
CSET reloadable = false
CSET rfd = false
CSET style = Rectangular_Shape
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_267a17cb29b4917a
GENERATE
Preparing to elaborate core...
Elaborating the module...
Generating the core .EDN implementation netlist...
 

SETPROJECT ./
Set current Project to C:\MATLAB6p5\work\isniamy\xpid_data2\temp\coregen_tmp
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET asynchronous_clear = false
CSET clk_cycles_per_input = 1
CSET clock_enable = false
CSET create_rpm = true
CSET memory_type = Distributed_Memory
CSET multiplier_type = Parallel
CSET nd = false
CSET output_hold_register = false
CSET output_options = Non_Registered
CSET output_width = 34
CSET pipelined = Minimum
CSET port_a_data = Signed
CSET port_a_width = 16
CSET port_b_constant = true
CSET port_b_constant_value = 512
CSET port_b_data = Unsigned
CSET port_b_width = 10
CSET rdy = false
CSET register_input = false
CSET reloadable = false
CSET rfd = false
CSET style = Rectangular_Shape
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_dd3f2ed519f74c1b
GENERATE
Preparing to elaborate core...
Elaborating the module...
Generating the core .EDN implementation netlist...
 

SETPROJECT ./
Set current Project to C:\MATLAB6p5\work\isniamy\xpid_data2\temp\coregen_tmp
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET asynchronous_clear = false
CSET clk_cycles_per_input = 1
CSET clock_enable = false
CSET create_rpm = true
CSET memory_type = Distributed_Memory
CSET multiplier_type = Parallel
CSET nd = false
CSET output_hold_register = false
CSET output_options = Non_Registered
CSET output_width = 40
CSET pipelined = Minimum
CSET port_a_data = Signed
CSET port_a_width = 24
CSET port_b_constant = true
CSET port_b_constant_value = 4475
CSET port_b_data = Unsigned
CSET port_b_width = 13
CSET rdy = false
CSET register_input = false
CSET reloadable = false
CSET rfd = false
CSET style = Rectangular_Shape
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_de781c7a0a82b6cf
GENERATE
Preparing to elaborate core...
Elaborating the module...
Generating the core .EDN implementation netlist...
 
