Project Navigator Auto-Make Log File
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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xtest/test_pkgs.vhd in Library work.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do test_tbw.ado 
listening on address 127.0.0.1 port 1200
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity test_addsub1
# -- Compiling architecture behavior of test_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: test_files.vhd(1507): No default binding for component: "adder_subtracter_spartan2_6_0_438ebd1a25415d4b". (No entity named "adder_subtracter_spartan2_6_0_438ebd1a25415d4b" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: test_files.vhd(1570): No default binding for component: "adder_subtracter_spartan2_6_0_31a2d7d587639c2f". (No entity named "adder_subtracter_spartan2_6_0_31a2d7d587639c2f" was found)
# WARNING[1]: test_files.vhd(1633): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# WARNING[1]: test_files.vhd(1696): No default binding for component: "adder_subtracter_spartan2_6_0_59d46904916909df". (No entity named "adder_subtracter_spartan2_6_0_59d46904916909df" was found)
# WARNING[1]: test_files.vhd(1759): No default binding for component: "adder_subtracter_spartan2_6_0_199c1e18e4579dff". (No entity named "adder_subtracter_spartan2_6_0_199c1e18e4579dff" was found)
# WARNING[1]: test_files.vhd(1822): No default binding for component: "adder_subtracter_spartan2_6_0_bfeb857b6aedd324". (No entity named "adder_subtracter_spartan2_6_0_bfeb857b6aedd324" was found)
# -- Compiling entity test_cmult3
# -- Compiling architecture behavior of test_cmult3
# WARNING[1]: test_files.vhd(2148): No default binding for component: "multiplier_spartan2_6_0_c898a6c13135c6d0". (No entity named "multiplier_spartan2_6_0_c898a6c13135c6d0" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: test_files.vhd(2201): No default binding for component: "multiplier_spartan2_6_0_7d52cda8234e03c2". (No entity named "multiplier_spartan2_6_0_7d52cda8234e03c2" was found)
# WARNING[1]: test_files.vhd(2254): No default binding for component: "multiplier_spartan2_6_0_13a3d468139afdbd". (No entity named "multiplier_spartan2_6_0_13a3d468139afdbd" was found)
# WARNING[1]: test_files.vhd(2307): No default binding for component: "multiplier_spartan2_6_0_6f13cc9ee672d655". (No entity named "multiplier_spartan2_6_0_6f13cc9ee672d655" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity test
# -- Compiling architecture structural of test
# -- Loading entity test_addsub1
# -- Loading entity test_cmult3
# -- Loading entity xldelay
# -- Loading entity xlsl2slv
# -- Compiling entity test_clock_driver
# -- Compiling architecture structural of test_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity test_clk_wrapper
# -- Compiling architecture structural of test_clk_wrapper
# -- Loading entity test_clock_driver
# -- Loading entity test
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity test_tbw
# -- Compiling architecture testbench_arch of test_tbw
# -- Loading entity test_clk_wrapper
# -- Compiling configuration test_clk_wrapper_cfg
# -- Loading entity test_tbw
# -- Loading architecture testbench_arch of test_tbw
# vsim -lib work -t 1ps test_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.test_tbw(testbench_arch)
# Loading work.test_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.test_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.test(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.test_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.test_cmult3(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 6938 statements or 27 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 810 ns  Iteration: 0  Process: /test_tbw/line__81 File: test_tbw.ant
# Break at test_tbw.ant line 119
# Stopped at test_tbw.ant line 119 


Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xtest/test_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/xtest/test_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <test_addsub1> (Architecture <behavior>) compiled.
Entity <test_cmult3> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <test> (Architecture <structural>) compiled.
Entity <test_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file C:/MATLAB6p5/work/xtest/test_clk_wrapper.vhd in Library work.
Architecture structural of Entity test_clk_wrapper is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <test_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest/test_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <test_clk_wrapper> analyzed. Unit <test_clk_wrapper> generated.

Analyzing Entity <test_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest/test_files.vhd line 3574: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <test_clock_driver> analyzed. Unit <test_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <test> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2599: Unconnected input port 'c_in' of component 'test_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2599: Unconnected output port 'c_out' of component 'test_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2654: Unconnected input port 'c_in' of component 'test_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2654: Unconnected output port 'c_out' of component 'test_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2709: Unconnected input port 'c_in' of component 'test_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2709: Unconnected output port 'c_out' of component 'test_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2764: Unconnected input port 'c_in' of component 'test_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2764: Unconnected output port 'c_out' of component 'test_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2819: Unconnected input port 'c_in' of component 'test_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2819: Unconnected output port 'c_out' of component 'test_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2874: Unconnected input port 'c_in' of component 'test_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2874: Unconnected output port 'c_out' of component 'test_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2929: Unconnected input port 'core_ce' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2929: Unconnected input port 'core_clr' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 2929: Unconnected input port 'core_clk' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 3064: Unconnected input port 'core_ce' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 3064: Unconnected input port 'core_clr' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 3064: Unconnected input port 'core_clk' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 3121: Unconnected input port 'core_ce' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 3121: Unconnected input port 'core_clr' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 3121: Unconnected input port 'core_clk' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 3178: Unconnected input port 'core_ce' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 3178: Unconnected input port 'core_clr' of component 'test_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest/test_files.vhd line 3178: Unconnected input port 'core_clk' of component 'test_cmult3' is tied to default value.
Entity <test> analyzed. Unit <test> generated.

Analyzing generic Entity <test_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_438ebd1a25415d4b"
	a_width = 16
	a_bin_pt = 4
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 12
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 33
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 33
	c_b_width = 33
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 33
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test_addsub1> analyzed. Unit <test_addsub1> generated.

Analyzing generic Entity <test_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_31a2d7d587639c2f"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 4
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 21
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 21
	c_b_width = 21
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 21
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test_addsub1> analyzed. Unit <test_addsub10> generated.

Analyzing generic Entity <test_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 4
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 4
	b_arith = 2
	s_width = 16
	s_bin_pt = 4
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test_addsub1> analyzed. Unit <test_addsub11> generated.

Analyzing generic Entity <test_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_59d46904916909df"
	a_width = 18
	a_bin_pt = 10
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 11
	b_arith = 2
	s_width = 19
	s_bin_pt = 11
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 33
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 33
	c_b_width = 33
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 33
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test_addsub1> analyzed. Unit <test_addsub12> generated.

Analyzing generic Entity <test_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_199c1e18e4579dff"
	a_width = 35
	a_bin_pt = 16
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 34
	b_bin_pt = 18
	b_arith = 2
	s_width = 18
	s_bin_pt = 10
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 38
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 38
	c_b_width = 38
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 38
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test_addsub1> analyzed. Unit <test_addsub13> generated.

Analyzing generic Entity <test_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_bfeb857b6aedd324"
	a_width = 19
	a_bin_pt = 11
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 20
	b_bin_pt = 12
	b_arith = 2
	s_width = 20
	s_bin_pt = 12
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 21
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 21
	c_b_width = 21
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 21
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test_addsub1> analyzed. Unit <test_addsub14> generated.

Analyzing generic Entity <test_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_c898a6c13135c6d0"
	a_width = 16
	a_bin_pt = 4
	a_arith = 2
	b_width = 4
	b_bin_pt = 8
	b_arith = 2
	p_width = 32
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 10
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 8
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 512
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test_cmult3> analyzed. Unit <test_cmult3> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 4
	d_arith = 2
	q_width = 16
	q_bin_pt = 4
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 20
	d_bin_pt = 12
	d_arith = 2
	q_width = 20
	q_bin_pt = 12
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay5> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 20
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg9> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 20
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e10> generated.

Analyzing generic Entity <test_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_7d52cda8234e03c2"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 8
	b_arith = 2
	p_width = 35
	p_bin_pt = 16
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 16
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 8
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 49920
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 35
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test_cmult3> analyzed. Unit <test_cmult36> generated.

Analyzing generic Entity <test_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_13a3d468139afdbd"
	a_width = 16
	a_bin_pt = 4
	a_arith = 2
	b_width = 4
	b_bin_pt = 14
	b_arith = 2
	p_width = 34
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 2
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 14
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 2
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 34
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test_cmult3> analyzed. Unit <test_cmult37> generated.

Analyzing generic Entity <test_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_6f13cc9ee672d655"
	a_width = 16
	a_bin_pt = 4
	a_arith = 2
	b_width = 4
	b_bin_pt = 7
	b_arith = 2
	p_width = 32
	p_bin_pt = 11
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 10
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 7
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 559
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test_cmult3> analyzed. Unit <test_cmult38> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


Reading constraint file .\test_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e10>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
Unit <srl17e10> synthesized.


Synthesizing Unit <synth_reg9>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg9> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <test_cmult38>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test_cmult38> synthesized.


Synthesizing Unit <test_cmult37>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test_cmult37> synthesized.


Synthesizing Unit <test_cmult36>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test_cmult36> synthesized.


Synthesizing Unit <xldelay5>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
Unit <xldelay5> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <test_cmult3>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test_cmult3> synthesized.


Synthesizing Unit <test_addsub14>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<20>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test_addsub14> synthesized.


Synthesizing Unit <test_addsub13>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<37:26>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test_addsub13> synthesized.


Synthesizing Unit <test_addsub12>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<32:19>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test_addsub12> synthesized.


Synthesizing Unit <test_addsub11>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test_addsub11> synthesized.


Synthesizing Unit <test_addsub10>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<20:17>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test_addsub10> synthesized.


Synthesizing Unit <test_addsub1>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<32:20>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<3:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <test>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
Unit <test> synthesized.


Synthesizing Unit <test_clock_driver>.
    Related source file is C:/MATLAB6p5/work/xtest/test_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <test_clock_driver> synthesized.


Synthesizing Unit <test_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/xtest/test_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <test_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <test_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_438ebd1a25415d4b.edn" "adder_subtracter_spartan2_6_0_438ebd1a25415d4b.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_438ebd1a25415d4b.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_31a2d7d587639c2f.edn" "adder_subtracter_spartan2_6_0_31a2d7d587639c2f.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_31a2d7d587639c2f.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_86c498140491d6df.edn" "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_59d46904916909df.edn" "adder_subtracter_spartan2_6_0_59d46904916909df.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_59d46904916909df.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_199c1e18e4579dff.edn" "adder_subtracter_spartan2_6_0_199c1e18e4579dff.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_199c1e18e4579dff.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_bfeb857b6aedd324.edn" "adder_subtracter_spartan2_6_0_bfeb857b6aedd324.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_bfeb857b6aedd324.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_c898a6c13135c6d0.edn" "multiplier_spartan2_6_0_c898a6c13135c6d0.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_c898a6c13135c6d0.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_7d52cda8234e03c2.edn" "multiplier_spartan2_6_0_7d52cda8234e03c2.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_7d52cda8234e03c2.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_13a3d468139afdbd.edn" "multiplier_spartan2_6_0_13a3d468139afdbd.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_13a3d468139afdbd.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_6f13cc9ee672d655.edn" "multiplier_spartan2_6_0_6f13cc9ee672d655.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_6f13cc9ee672d655.ngo"...
Loading core <adder_subtracter_spartan2_6_0_438ebd1a25415d4b> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_31a2d7d587639c2f> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_59d46904916909df> for timing and area information for instance <core_instance6>.
Loading core <adder_subtracter_spartan2_6_0_199c1e18e4579dff> for timing and area information for instance <core_instance8>.
Loading core <adder_subtracter_spartan2_6_0_bfeb857b6aedd324> for timing and area information for instance <core_instance10>.
Loading core <multiplier_spartan2_6_0_c898a6c13135c6d0> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_7d52cda8234e03c2> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_13a3d468139afdbd> for timing and area information for instance <core_instance4>.
Loading core <multiplier_spartan2_6_0_6f13cc9ee672d655> for timing and area information for instance <core_instance6>.

Optimizing unit <test_clk_wrapper> ...

Optimizing unit <srl17e10> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\test_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block test_clk_wrapper, actual ratio is 29.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     226  out of    768    29%  
 Number of Slice Flip Flops:            52  out of   1536     3%  
 Number of 4 input LUTs:               368  out of   1536    23%  
 Number of bonded IOBs:                 36  out of    144    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 52    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 26.863ns (Maximum Frequency: 37.226MHz)
   Minimum input arrival time before clock: 22.499ns
   Maximum output required time after clock: 32.028ns
   Maximum combinational path delay: 27.664ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\matlab6p5\work\xtest/_ngo -i -p
xc2s50-pq208-6 test_clk_wrapper.ngc test_clk_wrapper.ngd 

Reading NGO file "C:/MATLAB6p5/work/xtest/test_clk_wrapper.ngc" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_438ebd1a25415d4b.edn"
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_438ebd1a25415d4b.ngo
"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xtest/_ngo/adder_subtracter_spartan2_6_0_438ebd1a25415d4b.ngo
"...
Loading design module
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_438ebd1a25415d4b.ngo
"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_31a2d7d587639c2f.edn"
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_31a2d7d587639c2f.ngo
"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xtest/_ngo/adder_subtracter_spartan2_6_0_31a2d7d587639c2f.ngo
"...
Loading design module
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_31a2d7d587639c2f.ngo
"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_86c498140491d6df.edn"
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ngo
"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xtest/_ngo/adder_subtracter_spartan2_6_0_86c498140491d6df.ngo
"...
Loading design module
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ngo
"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_59d46904916909df.edn"
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_59d46904916909df.ngo
"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xtest/_ngo/adder_subtracter_spartan2_6_0_59d46904916909df.ngo
"...
Loading design module
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_59d46904916909df.ngo
"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_199c1e18e4579dff.edn"
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_199c1e18e4579dff.ngo
"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xtest/_ngo/adder_subtracter_spartan2_6_0_199c1e18e4579dff.ngo
"...
Loading design module
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_199c1e18e4579dff.ngo
"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_bfeb857b6aedd324.edn"
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_bfeb857b6aedd324.ngo
"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xtest/_ngo/adder_subtracter_spartan2_6_0_bfeb857b6aedd324.ngo
"...
Loading design module
"c:\matlab6p5\work\xtest\_ngo\adder_subtracter_spartan2_6_0_bfeb857b6aedd324.ngo
"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_c898a6c13135c6d0.edn"
"c:\matlab6p5\work\xtest\_ngo\multiplier_spartan2_6_0_c898a6c13135c6d0.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xtest/_ngo/multiplier_spartan2_6_0_c898a6c13135c6d0.ngo"...
Loading design module
"c:\matlab6p5\work\xtest\_ngo\multiplier_spartan2_6_0_c898a6c13135c6d0.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_7d52cda8234e03c2.edn"
"c:\matlab6p5\work\xtest\_ngo\multiplier_spartan2_6_0_7d52cda8234e03c2.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xtest/_ngo/multiplier_spartan2_6_0_7d52cda8234e03c2.ngo"...
Loading design module
"c:\matlab6p5\work\xtest\_ngo\multiplier_spartan2_6_0_7d52cda8234e03c2.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_13a3d468139afdbd.edn"
"c:\matlab6p5\work\xtest\_ngo\multiplier_spartan2_6_0_13a3d468139afdbd.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xtest/_ngo/multiplier_spartan2_6_0_13a3d468139afdbd.ngo"...
Loading design module
"c:\matlab6p5\work\xtest\_ngo\multiplier_spartan2_6_0_13a3d468139afdbd.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_6f13cc9ee672d655.edn"
"c:\matlab6p5\work\xtest\_ngo\multiplier_spartan2_6_0_6f13cc9ee672d655.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xtest/_ngo/multiplier_spartan2_6_0_6f13cc9ee672d655.ngo"...
Loading design module
"c:\matlab6p5\work\xtest\_ngo\multiplier_spartan2_6_0_6f13cc9ee672d655.ngo"...
mult_gen_v6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(20)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(21)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(22)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(23)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(24)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(25)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(26)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(27)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(28)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(29)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(30)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(31)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub1_core_instance0/S(32)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub2_core_instance2/S(17)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub2_core_instance2/S(18)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub2_core_instance2/S(19)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub2_core_instance2/S(20)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub3_core_instance4/S(16)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(19)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(20)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(21)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(22)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(23)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(24)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(25)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(26)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(27)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(28)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(29)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(30)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(31)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub4_core_instance6/S(32)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(26)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(27)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(28)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(29)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(30)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(31)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(32)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(33)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(34)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(35)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(36)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub5_core_instance8/S(37)' has
   no load
WARNING:NgdBuild:454 - logical net 'test_top_addsub6_core_instance10/S(20)' has
   no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  57

Total memory usage is 39788 kilobytes

Writing NGD file "test_clk_wrapper.ngd" ...

Writing NGDBUILD log file "test_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        32 out of  1,536    2%
  Number of 4 input LUTs:           237 out of  1,536   15%
Logic Distribution:
    Number of occupied Slices:                         135 out of    768   17%
    Number of Slices containing only related logic:    135 out of    135  100%
    Number of Slices containing unrelated logic:         0 out of    135    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:       237 out of  1,536   15%
   Number of bonded IOBs:            36 out of    140   25%
      IOB Flip Flops:                              16
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            7
Total equivalent gate count for design:  2,769
Additional JTAG gate count for IOBs:  1,776
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "test_clk_wrapper_map.mrp" for details.
Completed process "Map".

Mapping Module test_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o test_clk_wrapper_map.ncd test_clk_wrapper.ngd test_clk_wrapper.pcf
Mapping Module test_clk_wrapper: DONE



Started process "Place & Route".





Constraints file: test_clk_wrapper.pcf

Loading device database for application Par from file
"test_clk_wrapper_map.ncd".
   "test_clk_wrapper" is an NCD, version 2.38, device xc2s50, package pq208,
speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            36 out of 140    25%
      Number of LOCed External IOBs    0 out of 36      0%

   Number of SLICEs                  135 out of 768    17%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 3 secs 


Phase 1.1
Phase 1.1 (Checksum:9898fb) REAL time: 3 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.8
.....
.
Phase 5.8 (Checksum:9cd0b9) REAL time: 4 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 4 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs 

Writing design to file test_clk_wrapper.ncd.

Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 3 secs 


Phase 1: 702 unrouted;       REAL time: 5 secs 

Phase 2: 669 unrouted;       REAL time: 5 secs 

Phase 3: 124 unrouted;       REAL time: 5 secs 

Phase 4: 124 unrouted; (0)      REAL time: 6 secs 

Phase 5: 124 unrouted; (0)      REAL time: 6 secs 

Phase 6: 124 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   33   |  0.078     |  0.463      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_6a911e03 = PERIOD TIMEGRP "clk_6a9 | 100.000ns  | 23.897ns   | 13   
  11e03"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 9 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file test_clk_wrapper.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Wed Mar 30 19:36:23 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module test_clk_wrapper . . .
PAR command line: par -w -intstyle ise -ol std -t 1 test_clk_wrapper_map.ncd test_clk_wrapper.ncd test_clk_wrapper.pcf
PAR completed successfully



Started process "Generate Post-Place & Route Simulation Model".

Completed process "Generate Post-Place & Route Simulation Model".


Compiling vhdl file C:/MATLAB6p5/work/xtest/test_clk_wrapper.vhd in Library
work.
Entity <test_clk_wrapper> (Architecture <structural>) compiled.



Project Navigator Auto-Make Log File
-------------------------------------

Compiling vhdl file C:/MATLAB6p5/work/xtest/test_clk_wrapper.vhd in Library
work.
Entity <test_clk_wrapper> (Architecture <structural>) compiled.


