-- C:\MATLAB6P5\WORK\ISNIAMY\XSPARTAN2
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Fri Aug 12 17:13:16 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY top_tb IS
END top_tb;

ARCHITECTURE testbench_arch OF top_tb IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\matlab6p5\work\isniamy\xspartan2\top_tb.ano";
	COMPONENT top_spartan2
		PORT (
			clk : In  std_logic;
			in_x_0 : In  std_logic_vector (15 DOWNTO 0);
			pb : In  std_logic;
			reset : In  std_logic;
			anode0 : Out  std_logic;
			anode1 : Out  std_logic;
			anode2 : Out  std_logic;
			anode3 : Out  std_logic;
			chatod : Out  std_logic_vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL clk : std_logic;
	SIGNAL in_x_0 : std_logic_vector (15 DOWNTO 0);
	SIGNAL pb : std_logic;
	SIGNAL reset : std_logic;
	SIGNAL anode0 : std_logic;
	SIGNAL anode1 : std_logic;
	SIGNAL anode2 : std_logic;
	SIGNAL anode3 : std_logic;
	SIGNAL chatod : std_logic_vector (7 DOWNTO 0);

BEGIN
	UUT : top_spartan2
	PORT MAP (
		clk => clk,
		in_x_0 => in_x_0,
		pb => pb,
		reset => reset,
		anode0 => anode0,
		anode1 => anode1,
		anode2 => anode2,
		anode3 => anode3,
		chatod => chatod
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_anode0(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",anode0,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, anode0);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_anode1(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",anode1,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, anode1);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_anode2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",anode2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, anode2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_anode3(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",anode3,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, anode3);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_chatod(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",chatod,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, chatod);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clk <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_anode0(TX_TIME);
		ANNOTATE_anode1(TX_TIME);
		ANNOTATE_anode2(TX_TIME);
		ANNOTATE_anode3(TX_TIME);
		ANNOTATE_chatod(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clk <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		in_x_0 <= transport std_logic_vector'("1010101010101010"); --AAAA
		pb <= transport '1';
		reset <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		in_x_0 <= transport std_logic_vector'("0000010100000101"); --505
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		in_x_0 <= transport std_logic_vector'("0001000100010001"); --1111
		-- --------------------
		WAIT FOR 110 ns; -- Time=310 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION top_spartan2_cfg OF top_tb IS
	FOR testbench_arch
	END FOR;
END top_spartan2_cfg;
