-- C:\MATLAB6P5\WORK\ISNIAMY\XLOGIC2
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed May 18 16:57:15 2005
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.CONV_PKG.ALL;
USE WORK.CLOCK_PKG.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY logic2_tbw IS
END logic2_tbw;

ARCHITECTURE testbench_arch OF logic2_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT logic2_clk_wrapper
		PORT (
			gateway_in : In  std_logic;
			gateway_in1 : In  std_logic;
			gateway_in2 : In  std_logic;
			gateway_in3 : In  std_logic;
			gateway_out : Out  std_logic;
			gateway_out1 : Out  std_logic
		);
	END COMPONENT;

	SIGNAL gateway_in : std_logic;
	SIGNAL gateway_in1 : std_logic;
	SIGNAL gateway_in2 : std_logic;
	SIGNAL gateway_in3 : std_logic;
	SIGNAL gateway_out : std_logic;
	SIGNAL gateway_out1 : std_logic;

BEGIN
	UUT : logic2_clk_wrapper
	PORT MAP (
		gateway_in => gateway_in,
		gateway_in1 => gateway_in1,
		gateway_in2 => gateway_in2,
		gateway_in3 => gateway_in3,
		gateway_out => gateway_out,
		gateway_out1 => gateway_out1
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_gateway_out(
			next_gateway_out : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (gateway_out /= next_gateway_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ms gateway_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, gateway_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_gateway_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_gateway_out1(
			next_gateway_out1 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (gateway_out1 /= next_gateway_out1) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ms gateway_out1="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, gateway_out1);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_gateway_out1);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		gateway_in <= transport '0';
		gateway_in1 <= transport '0';
		gateway_in2 <= transport '0';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=50 ms
		CHECK_gateway_out('1',50);
		CHECK_gateway_out1('0',50);
		-- --------------------
		WAIT FOR 50 ms; -- Time=100 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 50 ms; -- Time=150 ms
		CHECK_gateway_out('1',150);
		CHECK_gateway_out1('0',150);
		-- --------------------
		WAIT FOR 50 ms; -- Time=200 ms
		gateway_in2 <= transport '1';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=250 ms
		CHECK_gateway_out('1',250);
		CHECK_gateway_out1('0',250);
		-- --------------------
		WAIT FOR 50 ms; -- Time=300 ms
		gateway_in1 <= transport '0';
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 50 ms; -- Time=350 ms
		CHECK_gateway_out('1',350);
		CHECK_gateway_out1('0',350);
		-- --------------------
		WAIT FOR 50 ms; -- Time=400 ms
		gateway_in1 <= transport '1';
		gateway_in2 <= transport '0';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=450 ms
		CHECK_gateway_out('1',450);
		CHECK_gateway_out1('0',450);
		-- --------------------
		WAIT FOR 50 ms; -- Time=500 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 50 ms; -- Time=550 ms
		CHECK_gateway_out('0',550);
		CHECK_gateway_out1('1',550);
		-- --------------------
		WAIT FOR 50 ms; -- Time=600 ms
		gateway_in2 <= transport '1';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=650 ms
		CHECK_gateway_out('1',650);
		CHECK_gateway_out1('0',650);
		-- --------------------
		WAIT FOR 50 ms; -- Time=700 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 50 ms; -- Time=750 ms
		CHECK_gateway_out('1',750);
		CHECK_gateway_out1('0',750);
		-- --------------------
		WAIT FOR 50 ms; -- Time=800 ms
		gateway_in <= transport '1';
		gateway_in1 <= transport '0';
		gateway_in2 <= transport '0';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=850 ms
		CHECK_gateway_out('1',850);
		CHECK_gateway_out1('0',850);
		-- --------------------
		WAIT FOR 50 ms; -- Time=900 ms
		gateway_in <= transport '1';
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 50 ms; -- Time=950 ms
		CHECK_gateway_out('0',950);
		CHECK_gateway_out1('1',950);
		-- --------------------
		WAIT FOR 50 ms; -- Time=1000 ms
		gateway_in <= transport '1';
		gateway_in2 <= transport '1';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=1050 ms
		CHECK_gateway_out('1',1050);
		CHECK_gateway_out1('0',1050);
		-- --------------------
		WAIT FOR 50 ms; -- Time=1100 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 50 ms; -- Time=1150 ms
		CHECK_gateway_out('1',1150);
		CHECK_gateway_out1('0',1150);
		-- --------------------
		WAIT FOR 50 ms; -- Time=1200 ms
		gateway_in1 <= transport '1';
		gateway_in2 <= transport '0';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=1250 ms
		CHECK_gateway_out('1',1250);
		CHECK_gateway_out1('0',1250);
		-- --------------------
		WAIT FOR 50 ms; -- Time=1300 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 50 ms; -- Time=1350 ms
		CHECK_gateway_out('1',1350);
		CHECK_gateway_out1('1',1350);
		-- --------------------
		WAIT FOR 50 ms; -- Time=1400 ms
		gateway_in2 <= transport '1';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=1450 ms
		CHECK_gateway_out('1',1450);
		CHECK_gateway_out1('0',1450);
		-- --------------------
		WAIT FOR 50 ms; -- Time=1500 ms
		gateway_in3 <= transport '1';
		-- --------------------
		WAIT FOR 50 ms; -- Time=1550 ms
		CHECK_gateway_out('1',1550);
		CHECK_gateway_out1('0',1550);
		-- --------------------
		WAIT FOR 50 ms; -- Time=1600 ms
		gateway_in <= transport '0';
		gateway_in1 <= transport '0';
		gateway_in2 <= transport '0';
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=1650 ms
		CHECK_gateway_out('1',1650);
		CHECK_gateway_out1('0',1650);
		-- --------------------
		WAIT FOR 100 ms; -- Time=1750 ms
		CHECK_gateway_out('1',1750);
		CHECK_gateway_out1('0',1750);
		-- --------------------
		WAIT FOR 50 ms; -- Time=1800 ms
		gateway_in3 <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=1850 ms
		CHECK_gateway_out('1',1850);
		CHECK_gateway_out1('0',1850);
		-- --------------------
		WAIT FOR 100 ms; -- Time=1950 ms
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION logic2_clk_wrapper_cfg OF logic2_tbw IS
	FOR testbench_arch
	END FOR;
END logic2_clk_wrapper_cfg;
