V1 69
FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd 2005/05/30.15:02:04
PH work/CONV_PKG        FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd \
      PB ieee/STD_LOGIC_1164 PH ieee/NUMERIC_STD
PB work/CONV_PKG        FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd \
      PH work/CONV_PKG
PH work/CLOCK_PKG       FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd \
      PB ieee/STD_LOGIC_1164
FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_clk_wrapper.vhd 2005/05/30.15:01:42
FL c:/matlab6p5/work/isniamy/xsimple1/simple1_clk_wrapper.vhd 2005/05/30.15:01:42
EN work/SIMPLE1_CLK_WRAPPER \
      FL c:/matlab6p5/work/isniamy/xsimple1/simple1_clk_wrapper.vhd \
      PB ieee/STD_LOGIC_1164 PB work/CONV_PKG PH work/CLOCK_PKG
AR work/SIMPLE1_CLK_WRAPPER/STRUCTURAL \
      FL c:/matlab6p5/work/isniamy/xsimple1/simple1_clk_wrapper.vhd \
      EN work/SIMPLE1_CLK_WRAPPER CP SIMPLE1_CLOCK_DRIVER CP SIMPLE1 \
      CP XLCLKPROBE
FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd 2005/05/30.15:02:06
EN work/SRL17E          FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB work/CONV_PKG
AR work/SRL17E/STRUCTURAL FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/SRL17E    CP SRL16E         CP FDE
EN work/SYNTH_REG       FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB work/CONV_PKG
AR work/SYNTH_REG/STRUCTURAL \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd EN work/SYNTH_REG \
      CP SRL17E
EN work/SYNTH_REG_REG   FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB work/CONV_PKG
AR work/SYNTH_REG_REG/BEHAV \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/SYNTH_REG_REG
EN work/SINGLE_REG_W_INIT FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB work/CONV_PKG
AR work/SINGLE_REG_W_INIT/STRUCTURAL \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/SINGLE_REG_W_INIT CP FDRE   CP FDSE
EN work/SYNTH_REG_W_INIT FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB work/CONV_PKG
AR work/SYNTH_REG_W_INIT/STRUCTURAL \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/SYNTH_REG_W_INIT CP SINGLE_REG_W_INIT
EN work/XLCLKPROBE      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB work/CONV_PKG PH work/CLOCK_PKG
AR work/XLCLKPROBE/BEHAVIOR \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd EN work/XLCLKPROBE
EN work/XLCLOCKDRIVER   FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PH ieee/NUMERIC_STD PB work/CONV_PKG
AR work/XLCLOCKDRIVER/BEHAVIOR \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/XLCLOCKDRIVER CP SYNTH_REG_W_INIT CP BUFG
EN work/XLCLOCKGENERATOR FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164
AR work/XLCLOCKGENERATOR/STRUCTURAL \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/XLCLOCKGENERATOR CP DCM     CP BUFGMUX        CP FDRE           CP BUFG
EN work/XLSL2SLV        FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB work/CONV_PKG
AR work/XLSL2SLV/BEHAVIOR FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/XLSL2SLV
EN work/XLSLV2SL        FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB work/CONV_PKG
AR work/XLSLV2SL/BEHAVIOR FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/XLSLV2SL
EN work/SYNTH_ADDSUB    FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PH ieee/NUMERIC_STD PB work/CONV_PKG
AR work/SYNTH_ADDSUB/BEHAVIOR \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/SYNTH_ADDSUB CP SYNTH_REG
EN work/SIMPLE1_ADDSUB1 FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB work/CONV_PKG
AR work/SIMPLE1_ADDSUB1/BEHAVIOR \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/SIMPLE1_ADDSUB1 CP SYNTH_ADDSUB \
      CP ADDER_SUBTRACTER_SPARTAN2_6_0_86C498140491D6DF \
      CP ADDER_SUBTRACTER_SPARTAN2_6_0_9B2656D23C19DEAF \
      CP ADDER_SUBTRACTER_SPARTAN2_6_0_8C3A892E3C6C3ED0 \
      CP ADDER_SUBTRACTER_SPARTAN2_6_0_47D1C1F0A7991DA9 CP SYNTH_REG
EN work/SIMPLE1_KD      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB work/CONV_PKG
AR work/SIMPLE1_KD/BEHAVIOR \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd EN work/SIMPLE1_KD \
      CP MULTIPLIER_SPARTAN2_6_0_FE654CF32DC31D3A \
      CP MULTIPLIER_SPARTAN2_6_0_E880A1B4A8AE9201 \
      CP MULTIPLIER_SPARTAN2_6_0_22D1B55EB2467AAC CP SYNTH_REG
EN work/XLDELAY         FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB work/CONV_PKG
AR work/XLDELAY/BEHAVIOR FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/XLDELAY   CP SYNTH_REG      CP SYNTH_REG_REG
EN work/SIMPLE1         FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB work/CONV_PKG PH work/CLOCK_PKG
AR work/SIMPLE1/STRUCTURAL \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd EN work/SIMPLE1 \
      CP WORK/SIMPLE1_ADDSUB1 CP WORK/XLDELAY CP WORK/SIMPLE1_KD CP WORK/XLSL2SLV
EN work/SIMPLE1_CLOCK_DRIVER \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      PB ieee/STD_LOGIC_1164 PB work/CONV_PKG PH work/CLOCK_PKG
AR work/SIMPLE1_CLOCK_DRIVER/STRUCTURAL \
      FL C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd \
      EN work/SIMPLE1_CLOCK_DRIVER CP XLCLOCKDRIVER
