# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do test_tbw.tdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Compiling entity test_clk_wrapper
# -- Compiling architecture structure of test_clk_wrapper
# -- Loading entity x_mux2
# -- Loading entity x_xor2
# -- Loading entity x_lut4
# -- Loading entity x_buf
# -- Loading entity x_zero
# -- Loading entity x_one
# -- Loading entity x_ff
# -- Loading entity x_tri
# -- Loading entity x_inv
# -- Loading entity x_ckbuf
# -- Loading package vital_timing
# -- Loading entity x_roc
# -- Loading entity x_toc
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity test_tbw
# -- Compiling architecture testbench_arch of test_tbw
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package vpackage
# -- Loading entity test_clk_wrapper
# -- Compiling configuration test_clk_wrapper_cfg
# -- Loading entity test_tbw
# -- Loading architecture testbench_arch of test_tbw
# vsim -lib work -sdfmax /UUT=test_clk_wrapper_timesim.sdf -t 1ps test_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../vital2000.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.vcomponents
# Loading C:/Modeltech_xe_starter/win32xoem/../vital2000.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.vpackage(body)
# Loading work.test_tbw(testbench_arch)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading work.test_clk_wrapper(structure)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_mux2(x_mux2_v)
# Loading test_clk_wrapper_timesim.sdf
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_xor2(x_xor2_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_lut4(x_lut4_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_buf(x_buf_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_zero(x_zero_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_one(x_one_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_ff(x_ff_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_tri(x_tri_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_inv(x_inv_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_ckbuf(x_ckbuf_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_toc(x_toc_v)
# WARNING: Design size of 5363 statements or 0 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Region: /test_tbw  File: test_tbw.timesim_vhw
# .wave
# .structure
# .signals
# ** Error: Error at time=20ns gateway_out=XXXXXXXXXXXXXXXXXXX0, Expected = 11111111101110011010 
#    Time: 20 ns  Iteration: 0  Instance: /test_tbw
# ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.133 ns; At : 111.775 ns
#    Time: 111775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u212
# ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.031 ns; At : 111.775 ns
#    Time: 111775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u27
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.039 ns; At : 111.775 ns
#    Time: 111775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u210
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.074 ns; At : 111.775 ns
#    Time: 111775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u28
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.333 ns; At : 111.775 ns
#    Time: 111775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u26
# ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.122 ns; At : 111.775 ns
#    Time: 111775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u213
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.059 ns; At : 111.775 ns
#    Time: 111775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u211
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.052 ns; At : 111.775 ns
#    Time: 111775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u214
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.022 ns; At : 111.775 ns
#    Time: 111775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u29
# ** Error: Error at time=120ns gateway_out=01001011111101000000, Expected = 11111111011100111000 
#    Time: 120 ns  Iteration: 0  Instance: /test_tbw
# ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.148 ns; At : 211.775 ns
#    Time: 211775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u25
# ** Warning: /X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.478 ns; Observed := 0.159 ns; At : 211.775 ns
#    Time: 211775 ps  Iteration: 1  Instance: /test_tbw/uut/test_top_delay1_synth_reg_srl_inst_last_srl17e_u24
# ** Error: Error at time=220ns gateway_out=0000XXXXXXXXXX011110, Expected = 11111111001011010110 
#    Time: 220 ns  Iteration: 0  Instance: /test_tbw
# ** Error: Error at time=320ns gateway_out=01XXXXXXXXXXXXXX1100, Expected = 11111110111001110100 
#    Time: 320 ns  Iteration: 0  Instance: /test_tbw
# ** Error: Error at time=420ns gateway_out=0XXXXXXXXXXXXXXX1010, Expected = 11111110101000010010 
#    Time: 420 ns  Iteration: 0  Instance: /test_tbw
# ** Error: Error at time=520ns gateway_out=XXXXXXXXXXXXXXXX1000, Expected = 11111110010110110000 
#    Time: 520 ns  Iteration: 0  Instance: /test_tbw
# ** Error: Error at time=620ns gateway_out=XXXXXXXXXXXXXXXX0110, Expected = 11111110000101001110 
#    Time: 620 ns  Iteration: 0  Instance: /test_tbw
# ** Error: Error at time=720ns gateway_out=XXXXXXXXXXXXXXXX0100, Expected = 11111101110011101100 
#    Time: 720 ns  Iteration: 0  Instance: /test_tbw
# ** Failure: Errors found during simulation
#    Time: 810 ns  Iteration: 0  Process: /test_tbw/line__66 File: test_tbw.timesim_vhw
# Break at test_tbw.timesim_vhw line 165
# Simulation Breakpoint: Break at test_tbw.timesim_vhw line 165
# MACRO ./test_tbw.tdo PAUSED at line 14
destroy .wave
destroy .signals
destroy .structure
