#:C39    
#Xilinx FPGA Editor Command Log File
#Editor Version:
#:V   NT M2.1 1.0
#Design Path Name:
#:N   simple1_clk_wrapper.ncd
#Current Working Directory:
#:D   C:\MATLAB6p5\work\isniamy\xsimple1
#Part Type:
#:P  Xilinx xc2s50 pq208 -6
#Date/Time:
#:T   Thu Jun 09 14:14:40 2005
#------------------------------
	#1
setattr main edit-mode no-logic-changes
	#2
setattr main disable_draw on
	#3
setattr layer switch_boxes view on
	#4
setattr main disable_draw off
	#Hint: change the visibility of more than one layer at a time by clicking on the apply button, clicking two or more layer buttons, and then clicking on the apply button again.
	#5
setattr main disable_draw on
	#6
setattr layer macros view on
	#7
setattr main disable_draw off
	#8
setattr main disable_draw on
	#9
setattr layer text view on
	#10
setattr main disable_draw off
	#11
setattr main disable_draw on
	#12
setattr layer pips view on
	#13
setattr main disable_draw off
	#14
setattr main disable_draw on
	#15
setattr layer pinwires view on
	#16
setattr main disable_draw off
	#17
unselect -all
	#18
select macro "simple1_top_kp_core_instance4/multiplier_spartan2_6_0_22d1b55eb2467aac/top_level/cc_mult/m3/r1"
	#19
unselect -all
	#20
select site "CLB_R10C13.S0"
	#site "CLB_R10C13.S0",  type = SLICE
	#21
unselect -all
	#22
select site "CLB_R10C13.S0"
	#site "CLB_R10C13.S0",  type = SLICE
	#23
unselect -all
	#24
select macro "simple1_top_addsub2_core_instance2/hset"
	#25
unselect -all
	#26
select site "CLB_R10C13.S0"
	#site "CLB_R10C13.S0",  type = SLICE
	#27
unselect -all
	#28
select macro "simple1_top_addsub2_core_instance2/hset"
	#29
unselect -all
	#30
select macro "simple1_top_addsub2_core_instance2/hset"
	#31
unselect -all
	#32
select site "CLB_R10C13.S0"
	#site "CLB_R10C13.S0",  type = SLICE
	#33
unselect -all
	#34
select macro "simple1_top_addsub2_core_instance2/hset"
	#35
unselect -all
	#36
select site "CLB_R10C13.S0"
	#site "CLB_R10C13.S0",  type = SLICE
	#37
unselect -all
	#38
select macro "simple1_top_addsub2_core_instance2/hset"
	#39
unselect -all
	#40
select macro "simple1_top_addsub2_core_instance2/hset"
	#41
unselect -all
	#42
select comp "simple1_top_s_x_0(12)"
	#comp "simple1_top_s_x_0(12)" in macro "simple1_top_addsub2_core_instance2/hset",  site "CLB_R10C13.S1",  type = SLICE
	#43
post block
	#<FFY>.
	#<G>; D=(A1@A2).
	#<RAMCONFIG>.
	#<G>; D=(A1@A2).
	#<G>; D=(A1@A2).
	#<G>.
	#<G>.
	#<G>; D=(A1@A2).
	#<G>; D=(A1@A2).
	#<G>; D=(A1@A2).
	#<G>; D=(A1@A2).
	#<G>; D=(A1@A2).
	#<G>; D=(A1@A2).
	#<G>; D=(A1@A2).
	#<G>; D=(A1@A2).
	#<G>; D=(A1@A2).
