// C:\MATLAB6P5\WORK\ISNIAMY\XSPARTAN2
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Thu Aug 11 11:39:19 2005
// 
// Notes:
// 1) This test fixture has been automatically generated from
//   your Test Bench Waveform
// 2) To use this as a user modifiable test fixture do the following:
//   - Save it as a file with a .tf extension (i.e. File->Save As...)
//   - Add it to your project as a testbench source (i.e. Project->Add Source...)
// 

`timescale 1ns/1ns

module spartan2_;
	reg ce;
	reg clk;
	reg [15:0] in_x_0;
	wire [23:0] out_x_0;

	spartan2_clk_wrapper UUT (
		.ce(ce),
		.clk(clk),
		.in_x_0(in_x_0),
		.out_x_0(out_x_0)
	);



always
begin 			//clock process
	clk = 1'b0;
	#10
	clk = 1'b1;
	#10
	#40
	clk = 1'b0;
	#40
	clk = 1'b0;
end

initial
begin

	// --------------------
	ce = 1'b1;
	in_x_0 = 16'b0000001100000000; //300
	// --------------------
	#100 // Time=100 ns
	in_x_0 = 16'b0000010000000000; //400
	// --------------------
	#110 // Time=210 ns
	// --------------------


end


endmodule
