JDF G
// Created by Project Navigator ver 1.0
PROJECT tambah_clk_wrapper.npl
DESIGN tambah_clk_wrapper
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE tambah_pkgs.vhd
SOURCE tambah_files.vhd
SOURCE tambah_clk_wrapper.vhd
STIMULUS plus1_tbw.tbw
[STATUS-ALL]
tambah_clk_wrapper.ncdFile=WARNINGS,1116130416
tambah_clk_wrapper.ngcFile=WARNINGS,1116130386
tambah_clk_wrapper.stxFile=WARNINGS,1116128138
[STRATEGY-LIST]
Normal=True
