Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xpid3sg/pid3sg_pkgs.vhd in Library work.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xpid3sg/pid3sg_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <pid3sg_addsub1> (Architecture <behavior>) compiled.
Entity <pid3sg_cmult3> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <pid3sg> (Architecture <structural>) compiled.
Entity <pid3sg_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file C:/MATLAB6p5/work/xpid3sg/pid3sg_clk_wrapper.vhd in Library work.
Entity <pid3sg_clk_wrapper> (Architecture <structural>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <pid3sg_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid3sg/pid3sg_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <pid3sg_clk_wrapper> analyzed. Unit <pid3sg_clk_wrapper> generated.

Analyzing Entity <pid3sg_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 3574: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <pid3sg_clock_driver> analyzed. Unit <pid3sg_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <pid3sg> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2599: Unconnected input port 'c_in' of component 'pid3sg_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2599: Unconnected output port 'c_out' of component 'pid3sg_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2654: Unconnected input port 'c_in' of component 'pid3sg_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2654: Unconnected output port 'c_out' of component 'pid3sg_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2709: Unconnected input port 'c_in' of component 'pid3sg_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2709: Unconnected output port 'c_out' of component 'pid3sg_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2764: Unconnected input port 'c_in' of component 'pid3sg_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2764: Unconnected output port 'c_out' of component 'pid3sg_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2819: Unconnected input port 'c_in' of component 'pid3sg_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2819: Unconnected output port 'c_out' of component 'pid3sg_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2874: Unconnected input port 'c_in' of component 'pid3sg_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2874: Unconnected output port 'c_out' of component 'pid3sg_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2929: Unconnected input port 'core_ce' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2929: Unconnected input port 'core_clr' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 2929: Unconnected input port 'core_clk' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 3064: Unconnected input port 'core_ce' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 3064: Unconnected input port 'core_clr' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 3064: Unconnected input port 'core_clk' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 3121: Unconnected input port 'core_ce' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 3121: Unconnected input port 'core_clr' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 3121: Unconnected input port 'core_clk' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 3178: Unconnected input port 'core_ce' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 3178: Unconnected input port 'core_clr' of component 'pid3sg_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd line 3178: Unconnected input port 'core_clk' of component 'pid3sg_cmult3' is tied to default value.
Entity <pid3sg> analyzed. Unit <pid3sg> generated.

Analyzing generic Entity <pid3sg_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_c9cda3f921770426"
	a_width = 20
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 38
	b_bin_pt = 14
	b_arith = 2
	s_width = 39
	s_bin_pt = 14
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 39
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 39
	c_b_width = 39
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 39
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid3sg_addsub1> analyzed. Unit <pid3sg_addsub1> generated.

Analyzing generic Entity <pid3sg_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 39
	a_bin_pt = 14
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 20
	b_bin_pt = 8
	b_arith = 2
	s_width = 40
	s_bin_pt = 14
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid3sg_addsub1> analyzed. Unit <pid3sg_addsub10> generated.

Analyzing generic Entity <pid3sg_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf"
	a_width = 20
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 20
	b_bin_pt = 8
	b_arith = 2
	s_width = 21
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 21
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 21
	c_b_width = 21
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 21
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid3sg_addsub1> analyzed. Unit <pid3sg_addsub11> generated.

Analyzing generic Entity <pid3sg_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_5c367c18f02e1774"
	a_width = 67
	a_bin_pt = 26
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 37
	b_bin_pt = 18
	b_arith = 2
	s_width = 68
	s_bin_pt = 26
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 68
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 68
	c_b_width = 68
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 68
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid3sg_addsub1> analyzed. Unit <pid3sg_addsub12> generated.

Analyzing generic Entity <pid3sg_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_7f6afff41f5f7a54"
	a_width = 56
	a_bin_pt = 16
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 38
	b_bin_pt = 26
	b_arith = 2
	s_width = 67
	s_bin_pt = 26
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 67
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 67
	c_b_width = 67
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 67
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid3sg_addsub1> analyzed. Unit <pid3sg_addsub13> generated.

Analyzing generic Entity <pid3sg_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_c14c50981235b92f"
	a_width = 68
	a_bin_pt = 26
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 16
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 69
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 69
	c_b_width = 69
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 69
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid3sg_addsub1> analyzed. Unit <pid3sg_addsub14> generated.

Analyzing generic Entity <pid3sg_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_d65c3216ed700608"
	a_width = 20
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 6
	b_arith = 2
	p_width = 38
	p_bin_pt = 14
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 20
	c_b_width = 8
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 20
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 6
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 128
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 38
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid3sg_cmult3> analyzed. Unit <pid3sg_cmult3> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 20
	d_bin_pt = 8
	d_arith = 2
	q_width = 20
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 20
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 20
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 16
	d_arith = 2
	q_width = 24
	q_bin_pt = 16
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay5> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg9> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e10> generated.

Analyzing generic Entity <pid3sg_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_1b58cf9c5190cfad"
	a_width = 40
	a_bin_pt = 14
	a_arith = 2
	b_width = 4
	b_bin_pt = 2
	b_arith = 2
	p_width = 56
	p_bin_pt = 16
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 40
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 40
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 2
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7800
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 56
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid3sg_cmult3> analyzed. Unit <pid3sg_cmult36> generated.

Analyzing generic Entity <pid3sg_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_eb0d20c59a93ecea"
	a_width = 20
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 18
	b_arith = 2
	p_width = 38
	p_bin_pt = 26
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 20
	c_b_width = 2
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 20
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 18
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 38
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid3sg_cmult3> analyzed. Unit <pid3sg_cmult37> generated.

Analyzing generic Entity <pid3sg_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_7808bd7aeb700524"
	a_width = 21
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 37
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 21
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 21
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 37
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <pid3sg_cmult3> analyzed. Unit <pid3sg_cmult38> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


Reading constraint file .\pid3sg_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e10>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
Unit <srl17e10> synthesized.


Synthesizing Unit <synth_reg9>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg9> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <pid3sg_cmult38>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <pid3sg_cmult38> synthesized.


Synthesizing Unit <pid3sg_cmult37>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <pid3sg_cmult37> synthesized.


Synthesizing Unit <pid3sg_cmult36>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <pid3sg_cmult36> synthesized.


Synthesizing Unit <xldelay5>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
Unit <xldelay5> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <pid3sg_cmult3>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <pid3sg_cmult3> synthesized.


Synthesizing Unit <pid3sg_addsub14>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<68:34>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<9:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid3sg_addsub14> synthesized.


Synthesizing Unit <pid3sg_addsub13>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid3sg_addsub13> synthesized.


Synthesizing Unit <pid3sg_addsub12>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid3sg_addsub12> synthesized.


Synthesizing Unit <pid3sg_addsub11>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid3sg_addsub11> synthesized.


Synthesizing Unit <pid3sg_addsub10>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid3sg_addsub10> synthesized.


Synthesizing Unit <pid3sg_addsub1>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <pid3sg_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <pid3sg>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
Unit <pid3sg> synthesized.


Synthesizing Unit <pid3sg_clock_driver>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <pid3sg_clock_driver> synthesized.


Synthesizing Unit <pid3sg_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/xpid3sg/pid3sg_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <pid3sg_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <pid3sg_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_c9cda3f921770426.edn" "adder_subtracter_spartan2_6_0_c9cda3f921770426.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_c9cda3f921770426.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.edn" "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.edn" "adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_5c367c18f02e1774.edn" "adder_subtracter_spartan2_6_0_5c367c18f02e1774.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_5c367c18f02e1774.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_7f6afff41f5f7a54.edn" "adder_subtracter_spartan2_6_0_7f6afff41f5f7a54.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_7f6afff41f5f7a54.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_c14c50981235b92f.edn" "adder_subtracter_spartan2_6_0_c14c50981235b92f.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_c14c50981235b92f.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_d65c3216ed700608.edn" "multiplier_spartan2_6_0_d65c3216ed700608.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_d65c3216ed700608.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_1b58cf9c5190cfad.edn" "multiplier_spartan2_6_0_1b58cf9c5190cfad.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_1b58cf9c5190cfad.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_eb0d20c59a93ecea.edn" "multiplier_spartan2_6_0_eb0d20c59a93ecea.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_eb0d20c59a93ecea.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_7808bd7aeb700524.edn" "multiplier_spartan2_6_0_7808bd7aeb700524.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_7808bd7aeb700524.ngo"...
Loading core <adder_subtracter_spartan2_6_0_c9cda3f921770426> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_5c367c18f02e1774> for timing and area information for instance <core_instance6>.
Loading core <adder_subtracter_spartan2_6_0_7f6afff41f5f7a54> for timing and area information for instance <core_instance8>.
Loading core <adder_subtracter_spartan2_6_0_c14c50981235b92f> for timing and area information for instance <core_instance10>.
Loading core <multiplier_spartan2_6_0_d65c3216ed700608> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_1b58cf9c5190cfad> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_eb0d20c59a93ecea> for timing and area information for instance <core_instance4>.
Loading core <multiplier_spartan2_6_0_7808bd7aeb700524> for timing and area information for instance <core_instance6>.

Optimizing unit <pid3sg_clk_wrapper> ...

Optimizing unit <srl17e> ...

Optimizing unit <srl17e10> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\pid3sg_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block pid3sg_clk_wrapper, actual ratio is 61.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     476  out of    768    61%  
 Number of Slice Flip Flops:            64  out of   1536     4%  
 Number of 4 input LUTs:               830  out of   1536    54%  
 Number of bonded IOBs:                 44  out of    144    30%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 64    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 29.656ns (Maximum Frequency: 33.720MHz)
   Minimum input arrival time before clock: 25.760ns
   Maximum output required time after clock: 34.821ns
   Maximum combinational path delay: 30.925ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\matlab6p5\work\xpid3sg/_ngo -i -p
xc2s50-pq208-6 pid3sg_clk_wrapper.ngc pid3sg_clk_wrapper.ngd 

Reading NGO file "C:/MATLAB6p5/work/xpid3sg/pid3sg_clk_wrapper.ngc" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_c9cda3f921770426.edn"
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_c9cda3f921770426.n
go"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid3sg/_ngo/adder_subtracter_spartan2_6_0_c9cda3f921770426.n
go"...
Loading design module
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_c9cda3f921770426.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_9b2656d23c19deaf.edn"
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid3sg/_ngo/adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
Loading design module
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.edn"
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.n
go"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid3sg/_ngo/adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.n
go"...
Loading design module
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_1b58cf9c5190cfad.edn"
"c:\matlab6p5\work\xpid3sg\_ngo\multiplier_spartan2_6_0_1b58cf9c5190cfad.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid3sg/_ngo/multiplier_spartan2_6_0_1b58cf9c5190cfad.ngo"...
Loading design module
"c:\matlab6p5\work\xpid3sg\_ngo\multiplier_spartan2_6_0_1b58cf9c5190cfad.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_5c367c18f02e1774.edn"
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_5c367c18f02e1774.n
go"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid3sg/_ngo/adder_subtracter_spartan2_6_0_5c367c18f02e1774.n
go"...
Loading design module
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_5c367c18f02e1774.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_7f6afff41f5f7a54.edn"
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_7f6afff41f5f7a54.n
go"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid3sg/_ngo/adder_subtracter_spartan2_6_0_7f6afff41f5f7a54.n
go"...
Loading design module
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_7f6afff41f5f7a54.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_c14c50981235b92f.edn"
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_c14c50981235b92f.n
go"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid3sg/_ngo/adder_subtracter_spartan2_6_0_c14c50981235b92f.n
go"...
Loading design module
"c:\matlab6p5\work\xpid3sg\_ngo\adder_subtracter_spartan2_6_0_c14c50981235b92f.n
go"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_d65c3216ed700608.edn"
"c:\matlab6p5\work\xpid3sg\_ngo\multiplier_spartan2_6_0_d65c3216ed700608.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid3sg/_ngo/multiplier_spartan2_6_0_d65c3216ed700608.ngo"...
Loading design module
"c:\matlab6p5\work\xpid3sg\_ngo\multiplier_spartan2_6_0_d65c3216ed700608.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_7808bd7aeb700524.edn"
"c:\matlab6p5\work\xpid3sg\_ngo\multiplier_spartan2_6_0_7808bd7aeb700524.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid3sg/_ngo/multiplier_spartan2_6_0_7808bd7aeb700524.ngo"...
Loading design module
"c:\matlab6p5\work\xpid3sg\_ngo\multiplier_spartan2_6_0_7808bd7aeb700524.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_eb0d20c59a93ecea.edn"
"c:\matlab6p5\work\xpid3sg\_ngo\multiplier_spartan2_6_0_eb0d20c59a93ecea.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/xpid3sg/_ngo/multiplier_spartan2_6_0_eb0d20c59a93ecea.ngo"...
Loading design module
"c:\matlab6p5\work\xpid3sg\_ngo\multiplier_spartan2_6_0_eb0d20c59a93ecea.ngo"...
mult_gen_v6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(0)' has
   no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(1)' has
   no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(2)' has
   no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(3)' has
   no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(4)' has
   no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(5)' has
   no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(6)' has
   no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(7)' has
   no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(8)' has
   no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(9)' has
   no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(34)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(35)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(36)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(37)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(38)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(39)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(40)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(41)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(42)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(43)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(44)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(45)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(46)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(47)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(48)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(49)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(50)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(51)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(52)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(53)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(54)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(55)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(56)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(57)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(58)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(59)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(60)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(61)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(62)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(63)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(64)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(65)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(66)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(67)'
   has no load
WARNING:NgdBuild:454 - logical net 'pid3sg_top_addsub6_core_instance10/S(68)'
   has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  45

Total memory usage is 41836 kilobytes

Writing NGD file "pid3sg_clk_wrapper.ngd" ...

Writing NGDBUILD log file "pid3sg_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
ERROR:Pack:12 - The RLOC value of R33C0.S1 on component pid3sg_top_s_x_2(0) in
   RPM pid3sg_top_addsub4_core_instance6/hset creates a macro that is too large
   for the device.  Use a bigger device.
ERROR:Pack:12 - The RLOC value of R33C0.S1 on component pid3sg_top_s_x_3(0) in
   RPM pid3sg_top_addsub5_core_instance8/hset creates a macro that is too large
   for the device.  Use a bigger device.
Problem encountered generating the NCD.

Mapping completed.
See MAP report file "pid3sg_clk_wrapper_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   2
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module pid3sg_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o pid3sg_clk_wrapper_map.ncd pid3sg_clk_wrapper.ngd pid3sg_clk_wrapper.pcf
Mapping Module pid3sg_clk_wrapper: failed


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