library ieee;
use ieee.std_logic_1164.all;

entity selector is
   port(a,b : in std_logic_vector(15 downto 0);
        sel : IN STD_LOGIC;
        y : out std_logic_vector(15 downto 0));
end selector;

architecture selector_behav of selector is
begin
   y <= a when(sel = '0') else
        b when(sel = '1');
end selector_behav;

