Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.53 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.53 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: top_spartan22.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top_spartan22.prj
Input Format                       : mixed
Synthesis Constraint File          : .\spartan2_clk_wrapper.xcf
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top_spartan22
Output Format                      : NGC
Target Device                      : xc2s50-6-pq208

---- Source Options
Top Module Name                    : top_spartan22
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : YES
Hierarchy Separator                : _
Bus Delimiter                      : ()
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top_spartan22.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan22.vhf in Library work.
Entity <top_spartan22> (Architecture <BEHAVIORAL>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "debounser.v"
Module <debounser> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_spartan22.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_spartan22> (Architecture <BEHAVIORAL>).
Entity <top_spartan22> analyzed. Unit <top_spartan22> generated.

Analyzing Entity <spartan2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd line 109: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <spartan2_clk_wrapper> analyzed. Unit <spartan2_clk_wrapper> generated.

Analyzing Entity <spartan2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <spartan2_clock_driver> analyzed. Unit <spartan2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <spartan2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2370: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2425: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2480: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected input port 'c_in' of component 'spartan2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2535: Unconnected output port 'c_out' of component 'spartan2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'spartan2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'spartan2_kd' is tied to default value.
Entity <spartan2> analyzed. Unit <spartan2> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub1> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub10> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 8
	b_arith = 2
	s_width = 24
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 2
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub11> generated.

Analyzing generic Entity <spartan2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_addsub1> analyzed. Unit <spartan2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 8
	d_arith = 2
	q_width = 24
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5cb3e9894aa707ba"
	a_width = 24
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 24
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 24
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd4> generated.

Analyzing generic Entity <spartan2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spartan2_kd> analyzed. Unit <spartan2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <debounser>.
Module <debounser> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\spartan2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <spartan2_kd5>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd5> synthesized.


Synthesizing Unit <spartan2_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd4> synthesized.


Synthesizing Unit <spartan2_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <spartan2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <spartan2_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub12> synthesized.


Synthesizing Unit <spartan2_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 362.
Unit <spartan2_addsub11> synthesized.


Synthesizing Unit <spartan2_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub10> synthesized.


Synthesizing Unit <spartan2_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <spartan2_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <spartan2>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
Unit <spartan2> synthesized.


Synthesizing Unit <spartan2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <spartan2_clock_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <debounser>.
    Related source file is debounser.v.
    Found 1-bit register for signal <choice1>.
    Found 1-bit register for signal <choice2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <debounser> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_154>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <spartan2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <spartan2_clk_wrapper> synthesized.


Synthesizing Unit <top_spartan22>.
    Related source file is C:/MATLAB6p5/work/isniamy/xspartan2/top_spartan22.vhf.
Unit <top_spartan22> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <spartan2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_5cb3e9894aa707ba.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_5cb3e9894aa707ba> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_spartan22> ...

Optimizing unit <spartan2_addsub11> ...

Optimizing unit <srl17e7> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\spartan2_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block top_spartan22, actual ratio is 36.
FlipFlop XLXI_2_anode0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_2_anode2 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top_spartan22.ngr
Top Level Output File Name         : top_spartan22
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 31

Macro Statistics :
# Registers                        : 8
#      1-bit register              : 6
#      18-bit register             : 1
#      2-bit register              : 1
# Adders/Subtractors               : 1
#      18-bit adder                : 1

Cell Usage :
# BELS                             : 1215
#      BUF                         : 105
#      GND                         : 8
#      LUT1                        : 1
#      LUT1_L                      : 18
#      LUT2                        : 6
#      LUT3                        : 31
#      LUT4                        : 446
#      MUXCY                       : 294
#      VCC                         : 3
#      XORCY                       : 303
# FlipFlops/Latches                : 69
#      FD                          : 1
#      FDC                         : 22
#      FDE                         : 40
#      FDP                         : 5
#      FDR                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 30
#      IBUF                        : 18
#      OBUF                        : 12
# Others                           : 1
#      TIMESPEC                    : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     280  out of    768    36%  
 Number of Slice Flip Flops:            69  out of   1536     4%  
 Number of 4 input LUTs:               502  out of   1536    32%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 20    |
XLXN_1(XLXI_3_choice31:O)          | NONE(*)(XLXI_1_spartan2_top_delay1_synth_reg_srl_inst_last_srl17e_u222)| 40    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 9     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.302ns (Maximum Frequency: 107.504MHz)
   Minimum input arrival time before clock: 10.838ns
   Maximum output required time after clock: 34.365ns
   Maximum combinational path delay: 35.901ns
-------------------------------------------------------------------------

Timing constraint: TS_clk_8917ce66 = PERIOD TIMEGRP "clk_8917ce66" 100 nS HIGH 50 nS
-------------------------------------------------------------------------
Slack:                  94.871ns
  Source:               XLXI_4_clock_cnt_0 (FF)
  Destination:          XLXI_4_clock_cnt_17 (FF)
  Data Path Delay:      5.129ns (Levels of Logic = 19)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 100.000ns

  Data Path: XLXI_4_clock_cnt_0 (FF) to XLXI_4_clock_cnt_17 (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   1.085   1.035  XLXI_4_clock_cnt_0 (XLXI_4_clock_cnt_0)
     LUT1_L:I0->LO         2   0.549   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_lut2_01 (XLXI_4_clock_cnt_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.659   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_0 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_1 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_2 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_3 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_4 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_5 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_6 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_7 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_8 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_9 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_10 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_11 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_12 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_13 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_14 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_14)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_15 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_15)
     MUXCY:CI->O           0   0.042   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_cy_16 (XLXI_4_clock_cnt_Madd__n0000_inst_cy_16)
     XORCY:CI->O           1   0.420   0.000  XLXI_4_clock_cnt_Madd__n0000_inst_sum_17 (XLXI_4_clock_cnt__n0000(17))
     FDC:D                     0.709          XLXI_4_clock_cnt_17
    ----------------------------------------
    Total                      5.129ns (4.094ns logic, 1.035ns route)
                                       (79.8% logic, 20.2% route)

=========================================================================
CPU : 14.22 / 15.25 s | Elapsed : 14.00 / 15.00 s
 
--> 

Total memory usage is 73484 kilobytes


