V1 8
FL c:/matlab6p5/work/xpid_sg_full_001_uji_pengendali/pid_sg_full_001_uji_pengendali_clk_wrapper.vhd 2005/03/30.13:08:45
EN work/PID_SG_FULL_001_UJI_PENGENDALI_CLK_WRAPPER \
      FL c:/matlab6p5/work/xpid_sg_full_001_uji_pengendali/pid_sg_full_001_uji_pengendali_clk_wrapper.vhd \
      PB ieee/STD_LOGIC_1164 PH work/CONV_PKG PH work/CLOCK_PKG
AR work/PID_SG_FULL_001_UJI_PENGENDALI_CLK_WRAPPER/STRUCTURAL \
      FL c:/matlab6p5/work/xpid_sg_full_001_uji_pengendali/pid_sg_full_001_uji_pengendali_clk_wrapper.vhd \
      EN work/PID_SG_FULL_001_UJI_PENGENDALI_CLK_WRAPPER \
      CP PID_SG_FULL_001_UJI_PENGENDALI_CLOCK_DRIVER \
      CP PID_SG_FULL_001_UJI_PENGENDALI CP XLCLKPROBE
