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-- System Generator version 6.2 vhdl source file.
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library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;

entity coba_dcm_wrapper is 
  port (
    clk: in std_logic;
    gateway_in: in std_logic_vector(7 downto 0);
    gateway_in1: in std_logic_vector(7 downto 0);
    rst: in std_logic;
    gateway_out1: out std_logic_vector(15 downto 0)
  );
end coba_dcm_wrapper;

architecture structural of coba_dcm_wrapper is
  component coba_clk_wrapper
    port (
      ce: in std_logic := '1';
      clk: in std_logic;
      gateway_in: in std_logic_vector(7 downto 0);
      gateway_in1: in std_logic_vector(7 downto 0);
      gateway_out1: out std_logic_vector(15 downto 0)
    );
  end component;
  component xlclockgenerator
    generic (
      ensure_clks_stable: boolean := false
    );
    port (
      clk: in std_logic;
      rst: in std_logic;
      clk0: out std_logic
    );
  end component;

  signal clk_0: std_logic;
  signal clk_src: std_logic;
  signal gateway_in1_x_0: std_logic_vector(7 downto 0);
  signal gateway_in_x_0: std_logic_vector(7 downto 0);
  signal gateway_out1_x_0: std_logic_vector(15 downto 0);
  signal rst_x_0: std_logic;

begin
  clk_src <= clk;
  gateway_in_x_0 <= gateway_in;
  gateway_in1_x_0 <= gateway_in1;
  rst_x_0 <= rst;
  gateway_out1 <= gateway_out1_x_0;

  coba_clock_generator: xlclockgenerator
    generic map (
      ensure_clks_stable => false
    )
    port map (
      clk => clk_src,
      rst => rst_x_0,
      clk0 => clk_0
    );
  coba_clock_wrapper: coba_clk_wrapper
    port map (
      clk => clk_0,
      gateway_in => gateway_in_x_0,
      gateway_in1 => gateway_in1_x_0,
      gateway_out1 => gateway_out1_x_0
    );
end structural;
