Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd in Library work.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv1_tbw.ado 
listening on address 127.0.0.1 port 1200
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv1_tbw
# -- Compiling architecture testbench_arch of tv1_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv1_tbw
# -- Loading architecture testbench_arch of tv1_tbw
# vsim -lib work -t 1ps tv1_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv1_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5502 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 101 ms  Iteration: 0  Process: /tv1_tbw/line__81 File: tv1_tbw.ant
# Break at tv1_tbw.ant line 123
# Stopped at tv1_tbw.ant line 123 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv1_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv1_tbw
# -- Compiling architecture testbench_arch of tv1_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv1_tbw
# -- Loading architecture testbench_arch of tv1_tbw
# vsim -lib work -t 1ps tv1_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv1_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv1_tbw/line__81 File: tv1_tbw.ant
# Break at tv1_tbw.ant line 126
# Stopped at tv1_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv2_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv2_tbw
# -- Compiling architecture testbench_arch of tv2_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv2_tbw
# -- Loading architecture testbench_arch of tv2_tbw
# vsim -lib work -t 1ps tv2_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv2_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5505 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv2_tbw/line__81 File: tv2_tbw.ant
# Break at tv2_tbw.ant line 127
# Stopped at tv2_tbw.ant line 127 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv3_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv3_tbw
# -- Compiling architecture testbench_arch of tv3_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv3_tbw
# -- Loading architecture testbench_arch of tv3_tbw
# vsim -lib work -t 1ps tv3_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv3_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv3_tbw/line__81 File: tv3_tbw.ant
# Break at tv3_tbw.ant line 126
# Stopped at tv3_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv4_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv4_tbw
# -- Compiling architecture testbench_arch of tv4_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv4_tbw
# -- Loading architecture testbench_arch of tv4_tbw
# vsim -lib work -t 1ps tv4_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv4_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5505 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv4_tbw/line__81 File: tv4_tbw.ant
# Break at tv4_tbw.ant line 127
# Stopped at tv4_tbw.ant line 127 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv5_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv5_tbw
# -- Compiling architecture testbench_arch of tv5_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv5_tbw
# -- Loading architecture testbench_arch of tv5_tbw
# vsim -lib work -t 1ps tv5_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv5_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5505 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv5_tbw/line__81 File: tv5_tbw.ant
# Break at tv5_tbw.ant line 127
# Stopped at tv5_tbw.ant line 127 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv6_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv6_tbw
# -- Compiling architecture testbench_arch of tv6_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv6_tbw
# -- Loading architecture testbench_arch of tv6_tbw
# vsim -lib work -t 1ps tv6_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv6_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv6_tbw/line__81 File: tv6_tbw.ant
# Break at tv6_tbw.ant line 126
# Stopped at tv6_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv7_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv7_tbw
# -- Compiling architecture testbench_arch of tv7_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv7_tbw
# -- Loading architecture testbench_arch of tv7_tbw
# vsim -lib work -t 1ps tv7_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv7_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv7_tbw/line__81 File: tv7_tbw.ant
# Break at tv7_tbw.ant line 126
# Stopped at tv7_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv8_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv8_tbw
# -- Compiling architecture testbench_arch of tv8_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv8_tbw
# -- Loading architecture testbench_arch of tv8_tbw
# vsim -lib work -t 1ps tv8_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv8_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv8_tbw/line__81 File: tv8_tbw.ant
# Break at tv8_tbw.ant line 126
# Stopped at tv8_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv9_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv9_tbw
# -- Compiling architecture testbench_arch of tv9_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv9_tbw
# -- Loading architecture testbench_arch of tv9_tbw
# vsim -lib work -t 1ps tv9_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv9_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv9_tbw/line__81 File: tv9_tbw.ant
# Break at tv9_tbw.ant line 126
# Stopped at tv9_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv10_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv10_tbw
# -- Compiling architecture testbench_arch of tv10_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv10_tbw
# -- Loading architecture testbench_arch of tv10_tbw
# vsim -lib work -t 1ps tv10_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv10_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv10_tbw/line__81 File: tv10_tbw.ant
# Break at tv10_tbw.ant line 126
# Stopped at tv10_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv11_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv11_tbw
# -- Compiling architecture testbench_arch of tv11_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv11_tbw
# -- Loading architecture testbench_arch of tv11_tbw
# vsim -lib work -t 1ps tv11_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv11_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv11_tbw/line__81 File: tv11_tbw.ant
# Break at tv11_tbw.ant line 126
# Stopped at tv11_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv12_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv12_tbw
# -- Compiling architecture testbench_arch of tv12_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv12_tbw
# -- Loading architecture testbench_arch of tv12_tbw
# vsim -lib work -t 1ps tv12_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv12_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5499 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 81 ms  Iteration: 0  Process: /tv12_tbw/line__81 File: tv12_tbw.ant
# Break at tv12_tbw.ant line 118
# Stopped at tv12_tbw.ant line 118 


Project Navigator Auto-Make Log File
-------------------------------------



Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv12_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv12_tbw
# -- Compiling architecture testbench_arch of tv12_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv12_tbw
# -- Loading architecture testbench_arch of tv12_tbw
# vsim -lib work -t 1ps tv12_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv12_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5499 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 81 ms  Iteration: 0  Process: /tv12_tbw/line__81 File: tv12_tbw.ant
# Break at tv12_tbw.ant line 118
# Stopped at tv12_tbw.ant line 118 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv12_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv12_tbw
# -- Compiling architecture testbench_arch of tv12_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv12_tbw
# -- Loading architecture testbench_arch of tv12_tbw
# vsim -lib work -t 1ps tv12_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv12_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5499 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 81 ms  Iteration: 0  Process: /tv12_tbw/line__81 File: tv12_tbw.ant
# Break at tv12_tbw.ant line 118
# Stopped at tv12_tbw.ant line 118 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv12_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv12_tbw
# -- Compiling architecture testbench_arch of tv12_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv12_tbw
# -- Loading architecture testbench_arch of tv12_tbw
# vsim -lib work -t 1ps tv12_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv12_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5499 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 81 ms  Iteration: 0  Process: /tv12_tbw/line__81 File: tv12_tbw.ant
# Break at tv12_tbw.ant line 118
# Stopped at tv12_tbw.ant line 118 


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <simple1_addsub1> (Architecture <behavior>) compiled.
Entity <simple1_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <simple1> (Architecture <structural>) compiled.
Entity <simple1_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_clk_wrapper.vhd in Library work.
Architecture structural of Entity simple1_clk_wrapper is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <simple1_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <simple1_clk_wrapper> analyzed. Unit <simple1_clk_wrapper> generated.

Analyzing Entity <simple1_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <simple1_clock_driver> analyzed. Unit <simple1_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


Reading constraint file .\simple1_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <simple1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <simple1_clock_driver>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <simple1_clock_driver> synthesized.


Synthesizing Unit <simple1_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <simple1_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <simple1_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_86c498140491d6df.edn" "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.edn" "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.edn" "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.edn" "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_fe654cf32dc31d3a.edn" "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_e880a1b4a8ae9201.edn" "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_22d1b55eb2467aac.edn" "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <simple1_clk_wrapper> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\simple1_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block simple1_clk_wrapper, actual ratio is 30.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     235  out of    768    30%  
 Number of Slice Flip Flops:            32  out of   1536     2%  
 Number of 4 input LUTs:               399  out of   1536    25%  
 Number of bonded IOBs:                 40  out of    144    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 32    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.045ns (Maximum Frequency: 198.216MHz)
   Minimum input arrival time before clock: 6.581ns
   Maximum output required time after clock: 24.810ns
   Maximum combinational path delay: 26.346ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\matlab6p5\work\isniamy\xsimple1/_ngo
-i -p xc2s50-pq208-6 simple1_clk_wrapper.ngc simple1_clk_wrapper.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xsimple1/simple1_clk_wrapper.ngc"
...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_86c498140491d6df.edn"
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_86c498140
491d6df.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/isniamy/xsimple1/_ngo/adder_subtracter_spartan2_6_0_86c498140
491d6df.ngo"...
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_86c498140
491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_9b2656d23c19deaf.edn"
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_9b2656d23
c19deaf.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/isniamy/xsimple1/_ngo/adder_subtracter_spartan2_6_0_9b2656d23
c19deaf.ngo"...
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_9b2656d23
c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.edn"
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3
c6c3ed0.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/isniamy/xsimple1/_ngo/adder_subtracter_spartan2_6_0_8c3a892e3
c6c3ed0.ngo"...
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3
c6c3ed0.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.edn"
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a
7991da9.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/isniamy/xsimple1/_ngo/adder_subtracter_spartan2_6_0_47d1c1f0a
7991da9.ngo"...
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a
7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_fe654cf32dc31d3a.edn"
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3
a.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/isniamy/xsimple1/_ngo/multiplier_spartan2_6_0_fe654cf32dc31d3
a.ngo"...
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3
a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_e880a1b4a8ae9201.edn"
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae920
1.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/isniamy/xsimple1/_ngo/multiplier_spartan2_6_0_e880a1b4a8ae920
1.ngo"...
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae920
1.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_22d1b55eb2467aac.edn"
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aa
c.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/matlab6p5/work/isniamy/xsimple1/_ngo/multiplier_spartan2_6_0_22d1b55eb2467aa
c.ngo"...
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aa
c.ngo"...
mult_gen_v6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub3_core_instance4/S(16)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(0)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(1)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(2)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(3)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(4)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(5)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(6)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(7)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(32)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(33)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(34)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(35)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(36)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(37)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(38)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(39)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(40)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(41)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(42)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(43)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(44)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(45)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(46)'
   has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 39868 kilobytes

Writing NGD file "simple1_clk_wrapper.ngd" ...

Writing NGDBUILD log file "simple1_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        16 out of  1,536    1%
  Number of 4 input LUTs:           298 out of  1,536   19%
Logic Distribution:
    Number of occupied Slices:                         155 out of    768   20%
    Number of Slices containing only related logic:    155 out of    155  100%
    Number of Slices containing unrelated logic:         0 out of    155    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          301 out of  1,536   19%
      Number used as logic:                       298
      Number used as a route-thru:                  3
   Number of bonded IOBs:            40 out of    140   28%
      IOB Flip Flops:                              16
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,109
Additional JTAG gate count for IOBs:  1,968
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "simple1_clk_wrapper_map.mrp" for details.
Completed process "Map".

Mapping Module simple1_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o simple1_clk_wrapper_map.ncd simple1_clk_wrapper.ngd simple1_clk_wrapper.pcf
Mapping Module simple1_clk_wrapper: DONE



Started process "Place & Route".





Constraints file: simple1_clk_wrapper.pcf

Loading device database for application Par from file
"simple1_clk_wrapper_map.ncd".
   "simple1_clk_wrapper" is an NCD, version 2.38, device xc2s50, package pq208,
speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            40 out of 140    28%
      Number of LOCed External IOBs    0 out of 40      0%

   Number of SLICEs                  155 out of 768    20%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:9898eb) REAL time: 3 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.8
.......
.
Phase 5.8 (Checksum:9cbe44) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file simple1_clk_wrapper.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 867 unrouted;       REAL time: 3 secs 

Phase 2: 843 unrouted;       REAL time: 3 secs 

Phase 3: 188 unrouted;       REAL time: 3 secs 

Phase 4: 188 unrouted; (0)      REAL time: 3 secs 

Phase 5: 188 unrouted; (0)      REAL time: 3 secs 

Phase 6: 188 unrouted; (0)      REAL time: 3 secs 

Phase 7: 0 unrouted; (0)      REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   24   |  0.089     |  0.463      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_9bdee101 = PERIOD TIMEGRP "clk_9bd | 100.000ns  | 4.641ns    | 8    
  ee101"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  53 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file simple1_clk_wrapper.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue May 31 16:49:05 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module simple1_clk_wrapper . . .
PAR command line: par -w -intstyle ise -ol std -t 1 simple1_clk_wrapper_map.ncd simple1_clk_wrapper.ncd simple1_clk_wrapper.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv7_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv7_tbw
# -- Compiling architecture testbench_arch of tv7_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv7_tbw
# -- Loading architecture testbench_arch of tv7_tbw
# vsim -lib work -t 1ps tv7_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv7_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv7_tbw/line__81 File: tv7_tbw.ant
# Break at tv7_tbw.ant line 126
# Stopped at tv7_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv8_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv8_tbw
# -- Compiling architecture testbench_arch of tv8_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv8_tbw
# -- Loading architecture testbench_arch of tv8_tbw
# vsim -lib work -t 1ps tv8_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv8_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv8_tbw/line__81 File: tv8_tbw.ant
# Break at tv8_tbw.ant line 126
# Stopped at tv8_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv9_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv9_tbw
# -- Compiling architecture testbench_arch of tv9_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv9_tbw
# -- Loading architecture testbench_arch of tv9_tbw
# vsim -lib work -t 1ps tv9_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv9_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv9_tbw/line__81 File: tv9_tbw.ant
# Break at tv9_tbw.ant line 126
# Stopped at tv9_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv10_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv10_tbw
# -- Compiling architecture testbench_arch of tv10_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv10_tbw
# -- Loading architecture testbench_arch of tv10_tbw
# vsim -lib work -t 1ps tv10_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv10_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv10_tbw/line__81 File: tv10_tbw.ant
# Break at tv10_tbw.ant line 126
# Stopped at tv10_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv10_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv10_tbw
# -- Compiling architecture testbench_arch of tv10_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv10_tbw
# -- Loading architecture testbench_arch of tv10_tbw
# vsim -lib work -t 1ps tv10_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv10_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv10_tbw/line__81 File: tv10_tbw.ant
# Break at tv10_tbw.ant line 126
# Stopped at tv10_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv11_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv11_tbw
# -- Compiling architecture testbench_arch of tv11_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv11_tbw
# -- Loading architecture testbench_arch of tv11_tbw
# vsim -lib work -t 1ps tv11_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv11_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv11_tbw/line__81 File: tv11_tbw.ant
# Break at tv11_tbw.ant line 126
# Stopped at tv11_tbw.ant line 126 


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Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv12_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv12_tbw
# -- Compiling architecture testbench_arch of tv12_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv12_tbw
# -- Loading architecture testbench_arch of tv12_tbw
# vsim -lib work -t 1ps tv12_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv12_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5499 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 81 ms  Iteration: 0  Process: /tv12_tbw/line__81 File: tv12_tbw.ant
# Break at tv12_tbw.ant line 118
# Stopped at tv12_tbw.ant line 118 


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Started process "Asynchronous Delay Report".


Loading device database for application reportgen from file
"simple1_clk_wrapper.ncd".
   "simple1_clk_wrapper" is an NCD, version 2.38, device xc2s50, package pq208,
speed -6
Loading device for application reportgen from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.

Generating Delay Report: simple1_clk_wrapper.dly


reportgen done!
Completed process "Asynchronous Delay Report".



Project Navigator Auto-Make Log File
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Started process "Guide Results Report".

ERROR: Property "PAR Guide Design File (.ncd)" is not set. Please specify the file you want to guide Place & Route with
       in the "PAR Guide Design File (.ncd)" Place & Route property before running this process.
Process "Guide Results Report" did not complete.



Project Navigator Auto-Make Log File
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Started process "Guide Results Report".

ERROR: Property "PAR Guide Design File (.ncd)" is not set. Please specify the file you want to guide Place & Route with
       in the "PAR Guide Design File (.ncd)" Place & Route property before running this process.
Process "Guide Results Report" did not complete.



Project Navigator Auto-Make Log File
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Started process "Guide Results Report".

ERROR: Property "PAR Guide Design File (.ncd)" is not set. Please specify the file you want to guide Place & Route with
       in the "PAR Guide Design File (.ncd)" Place & Route property before running this process.
Process "Guide Results Report" did not complete.



Project Navigator Auto-Make Log File
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Started process "Guide Results Report".

ERROR: Property "PAR Guide Design File (.ncd)" is not set. Please specify the file you want to guide Place & Route with
       in the "PAR Guide Design File (.ncd)" Place & Route property before running this process.
Process "Guide Results Report" did not complete.



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Started process "Back-annotate Pin Locations".

Completed process "Back-annotate Pin Locations".



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Started process "Back-annotate Pin Locations".

Completed process "Back-annotate Pin Locations".



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Started process "Programming File Generation Report".

Completed process "Programming File Generation Report".



Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <synth_reg_w_init> (Architecture <structural>).
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 8
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.


Reading constraint file .\simple1_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <synth_reg_w_init> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <synth_reg_w_init> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\simple1_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block synth_reg_w_init, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                       5  out of    768     0%  
 Number of Slice Flip Flops:             8  out of   1536     0%  
 Number of bonded IOBs:                 18  out of    144    12%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: 3.507ns
   Maximum output required time after clock: 6.788ns
   Maximum combinational path delay: No path found
WARNING:Xst:1415 - No path found for this constraint.

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\matlab6p5\work\isniamy\xsimple1/_ngo
-i -p xc2s50-pq208-6 synth_reg_w_init.ngc synth_reg_w_init.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xsimple1/synth_reg_w_init.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36736 kilobytes

Writing NGD file "synth_reg_w_init.ngd" ...

Writing NGDBUILD log file "synth_reg_w_init.bld"...

NGDBUILD done.
Completed process "Translate".



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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.


Reading constraint file .\simple1_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <simple1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <simple1> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <simple1> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\simple1_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 9.80 / 10.91 s | Elapsed : 10.00 / 11.00 s
 
--> 

Total memory usage is 70408 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd in
Library work.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd in
Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <simple1_addsub1> (Architecture <behavior>) compiled.
Entity <simple1_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <simple1> (Architecture <structural>) compiled.
Entity <simple1_clock_driver> (Architecture <structural>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.


Reading constraint file .\simple1_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <simple1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <simple1> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <simple1> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\simple1_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 10.30 / 11.94 s | Elapsed : 10.00 / 11.00 s
 
--> 

Total memory usage is 70408 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Guide Results Report".

ERROR: Property "PAR Guide Design File (.ncd)" is not set. Please specify the file you want to guide Place & Route with
       in the "PAR Guide Design File (.ncd)" Place & Route property before running this process.
Process "Guide Results Report" did not complete.



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\matlab6p5\work\isniamy\xsimple1/_ngo
-uc simple1_clk_wrapper.ucf -p xc2s50-pq208-6 simple1_clk_wrapper.ngc
simple1_clk_wrapper.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xsimple1/simple1_clk_wrapper.ngc"
...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_86c498140
491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_9b2656d23
c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3
c6c3ed0.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a
7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3
a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae920
1.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aa
c.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "simple1_clk_wrapper.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub3_core_instance4/S(16)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(0)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(1)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(2)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(3)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(4)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(5)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(6)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(7)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(32)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(33)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(34)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(35)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(36)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(37)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(38)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(39)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(40)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(41)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(42)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(43)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(44)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(45)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(46)'
   has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 40832 kilobytes

Writing NGD file "simple1_clk_wrapper.ngd" ...

Writing NGDBUILD log file "simple1_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        16 out of  1,536    1%
  Number of 4 input LUTs:           298 out of  1,536   19%
Logic Distribution:
    Number of occupied Slices:                         155 out of    768   20%
    Number of Slices containing only related logic:    155 out of    155  100%
    Number of Slices containing unrelated logic:         0 out of    155    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          301 out of  1,536   19%
      Number used as logic:                       298
      Number used as a route-thru:                  3
   Number of bonded IOBs:            40 out of    140   28%
      IOB Flip Flops:                              16
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,109
Additional JTAG gate count for IOBs:  1,968
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "simple1_clk_wrapper_map.mrp" for details.
Completed process "Map".

Mapping Module simple1_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o simple1_clk_wrapper_map.ncd simple1_clk_wrapper.ngd simple1_clk_wrapper.pcf
Mapping Module simple1_clk_wrapper: DONE



Started process "Place & Route".





Constraints file: simple1_clk_wrapper.pcf

Loading device database for application Par from file
"simple1_clk_wrapper_map.ncd".
   "simple1_clk_wrapper" is an NCD, version 2.38, device xc2s50, package pq208,
speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            40 out of 140    28%
      Number of LOCed External IOBs    0 out of 40      0%

   Number of SLICEs                  155 out of 768    20%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:9898eb) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.......
.
Phase 5.8 (Checksum:9cbe44) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file simple1_clk_wrapper.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 867 unrouted;       REAL time: 3 secs 

Phase 2: 843 unrouted;       REAL time: 3 secs 

Phase 3: 188 unrouted;       REAL time: 3 secs 

Phase 4: 188 unrouted; (0)      REAL time: 3 secs 

Phase 5: 188 unrouted; (0)      REAL time: 3 secs 

Phase 6: 188 unrouted; (0)      REAL time: 3 secs 

Phase 7: 0 unrouted; (0)      REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   24   |  0.089     |  0.463      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_9bdee101 = PERIOD TIMEGRP "clk_9bd | 100.000ns  | 4.641ns    | 8    
  ee101"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  53 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file simple1_clk_wrapper.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Thu Jun 09 14:14:36 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module simple1_clk_wrapper . . .
PAR command line: par -w -intstyle ise -ol std -t 1 simple1_clk_wrapper_map.ncd simple1_clk_wrapper.ncd simple1_clk_wrapper.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\matlab6p5\work\isniamy\xsimple1/_ngo
-uc simple1_clk_wrapper.ucf -p xc2s50-pq208-6 simple1_clk_wrapper.ngc
simple1_clk_wrapper.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xsimple1/simple1_clk_wrapper.ngc"
...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_86c498140
491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_9b2656d23
c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3
c6c3ed0.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a
7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3
a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae920
1.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aa
c.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "simple1_clk_wrapper.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub3_core_instance4/S(16)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(0)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(1)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(2)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(3)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(4)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(5)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(6)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(7)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(32)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(33)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(34)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(35)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(36)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(37)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(38)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(39)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(40)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(41)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(42)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(43)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(44)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(45)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(46)'
   has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 40832 kilobytes

Writing NGD file "simple1_clk_wrapper.ngd" ...

Writing NGDBUILD log file "simple1_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        16 out of  1,536    1%
  Number of 4 input LUTs:           298 out of  1,536   19%
Logic Distribution:
    Number of occupied Slices:                         155 out of    768   20%
    Number of Slices containing only related logic:    155 out of    155  100%
    Number of Slices containing unrelated logic:         0 out of    155    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          301 out of  1,536   19%
      Number used as logic:                       298
      Number used as a route-thru:                  3
   Number of bonded IOBs:            40 out of    140   28%
      IOB Flip Flops:                              16
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,109
Additional JTAG gate count for IOBs:  1,968
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "simple1_clk_wrapper_map.mrp" for details.
Completed process "Map".

Mapping Module simple1_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o simple1_clk_wrapper_map.ncd simple1_clk_wrapper.ngd simple1_clk_wrapper.pcf
Mapping Module simple1_clk_wrapper: DONE



Started process "Place & Route".





Constraints file: simple1_clk_wrapper.pcf

Loading device database for application Par from file
"simple1_clk_wrapper_map.ncd".
   "simple1_clk_wrapper" is an NCD, version 2.38, device xc2s50, package pq208,
speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            40 out of 140    28%
      Number of LOCed External IOBs    1 out of 40      2%

   Number of SLICEs                  155 out of 768    20%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:9898eb) REAL time: 3 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.8
.....
.
Phase 5.8 (Checksum:9c82cb) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file simple1_clk_wrapper.ncd.

Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 867 unrouted;       REAL time: 4 secs 

Phase 2: 843 unrouted;       REAL time: 4 secs 

Phase 3: 217 unrouted;       REAL time: 4 secs 

Phase 4: 217 unrouted; (0)      REAL time: 4 secs 

Phase 5: 217 unrouted; (0)      REAL time: 4 secs 

Phase 6: 217 unrouted; (0)      REAL time: 4 secs 

Phase 7: 0 unrouted; (0)      REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   24   |  0.114     |  0.466      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_9bdee101 = PERIOD TIMEGRP "clk_9bd | 100.000ns  | 4.641ns    | 8    
  ee101"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  53 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file simple1_clk_wrapper.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Thu Jun 23 14:03:42 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module simple1_clk_wrapper . . .
PAR command line: par -w -intstyle ise -ol std -t 1 simple1_clk_wrapper_map.ncd simple1_clk_wrapper.ncd simple1_clk_wrapper.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv1_1_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv1_1_tbw
# -- Compiling architecture testbench_arch of tv1_1_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv1_1_tbw
# -- Loading architecture testbench_arch of tv1_1_tbw
# vsim -lib work -t 1ps tv1_1_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv1_1_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5500 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 91 ms  Iteration: 0  Process: /tv1_1_tbw/line__81 File: tv1_1_tbw.ant
# Break at tv1_1_tbw.ant line 120
# Stopped at tv1_1_tbw.ant line 120 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv1_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv1_tbw
# -- Compiling architecture testbench_arch of tv1_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv1_tbw
# -- Loading architecture testbench_arch of tv1_tbw
# vsim -lib work -t 1ps tv1_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv1_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5514 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 161 ms  Iteration: 0  Process: /tv1_tbw/line__81 File: tv1_tbw.ant
# Break at tv1_tbw.ant line 141
# Stopped at tv1_tbw.ant line 141 


Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv1_tbw.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity simple1_addsub1
# -- Compiling architecture behavior of simple1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: simple1_files.vhd(1481): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: simple1_files.vhd(1544): No default binding for component: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf". (No entity named "adder_subtracter_spartan2_6_0_9b2656d23c19deaf" was found)
# WARNING[1]: simple1_files.vhd(1607): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: simple1_files.vhd(1670): No default binding for component: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9". (No entity named "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9" was found)
# -- Compiling entity simple1_kd
# -- Compiling architecture behavior of simple1_kd
# WARNING[1]: simple1_files.vhd(1984): No default binding for component: "multiplier_spartan2_6_0_fe654cf32dc31d3a". (No entity named "multiplier_spartan2_6_0_fe654cf32dc31d3a" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: simple1_files.vhd(2037): No default binding for component: "multiplier_spartan2_6_0_e880a1b4a8ae9201". (No entity named "multiplier_spartan2_6_0_e880a1b4a8ae9201" was found)
# WARNING[1]: simple1_files.vhd(2090): No default binding for component: "multiplier_spartan2_6_0_22d1b55eb2467aac". (No entity named "multiplier_spartan2_6_0_22d1b55eb2467aac" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity simple1
# -- Compiling architecture structural of simple1
# -- Loading entity simple1_addsub1
# -- Loading entity xldelay
# -- Loading entity simple1_kd
# -- Loading entity xlsl2slv
# -- Compiling entity simple1_clock_driver
# -- Compiling architecture structural of simple1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity simple1_clk_wrapper
# -- Compiling architecture structural of simple1_clk_wrapper
# -- Loading entity simple1_clock_driver
# -- Loading entity simple1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tv1_tbw
# -- Compiling architecture testbench_arch of tv1_tbw
# -- Loading entity simple1_clk_wrapper
# -- Compiling configuration simple1_clk_wrapper_cfg
# -- Loading entity tv1_tbw
# -- Loading architecture testbench_arch of tv1_tbw
# vsim -lib work -t 1ps tv1_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.tv1_tbw(testbench_arch)
# Loading work.simple1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.simple1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.simple1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.simple1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.simple1_kd(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 5504 statements or 19 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 111 ms  Iteration: 0  Process: /tv1_tbw/line__81 File: tv1_tbw.ant
# Break at tv1_tbw.ant line 126
# Stopped at tv1_tbw.ant line 126 


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\matlab6p5\work\isniamy\xsimple1/_ngo
-uc simple1_clk_wrapper.ucf -p xc2s50-pq208-6 simple1_clk_wrapper.ngc
simple1_clk_wrapper.ngd 

Reading NGO file "C:/MATLAB6p5/work/isniamy/xsimple1/simple1_clk_wrapper.ngc"
...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_86c498140
491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_9b2656d23
c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3
c6c3ed0.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a
7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3
a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae920
1.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\isniamy\xsimple1\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aa
c.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "simple1_clk_wrapper.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub3_core_instance4/S(16)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(0)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(1)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(2)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(3)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(4)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(5)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(6)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(7)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(32)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(33)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(34)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(35)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(36)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(37)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(38)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(39)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(40)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(41)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(42)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(43)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(44)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(45)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(46)'
   has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 40836 kilobytes

Writing NGD file "simple1_clk_wrapper.ngd" ...

Writing NGDBUILD log file "simple1_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".


