## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module test2_clk_wrapper
vcom -87 -explicit  test2_clk_wrapper_timesim.vhd
vcom -93 -explicit  test2_tbw.timesim_vhw
vsim -t 1ps -sdfmax /UUT=test2_clk_wrapper_timesim.sdf  -lib work test2_tbw
do test2_tbw.udo
view wave
add wave *
view structure
view signals
run -all
## End
