

block pid_sg_full_001_clk_wrapper {
  port ce: in "std_logic"  "" 
    attrs {
      "is_ce" => true
      "domain" => ""
      "type" => "logic"
      "width" => 1
      "period" => 1
      "rate_pair" => [
        1
        1
      ]
    }
  port clk: in "std_logic"  "" 
    attrs {
      "is_clk" => true
      "domain" => ""
      "type" => "logic"
      "width" => 1
      "period" => 1
      "rate_pair" => [
        1
        1
      ]
    }
  port gateway_in1: in "std_logic_vector(15 downto 0)"  "[15 : 0]" 
    attrs {
      "bin_pt" => 4
      "timing_constraint" => "none"
      "is_gateway_port" => true
      "simulink_name" => "pid_sg_full_001/Gateway In1"
      "type" => "Fix_16_4"
      "width" => 16
      "period" => 1
    }
  port gateway_out: out "std_logic_vector(19 downto 0)"  "[19 : 0]" 
    attrs {
      "bin_pt" => 8
      "timing_constraint" => "none"
      "is_gateway_port" => true
      "simulink_name" => "pid_sg_full_001/Gateway Out"
      "type" => "Fix_20_8"
      "width" => 20
      "period" => 1
    }


  clk <= clk_sysgen
  gateway_in1 <= gateway_in1_x_0
  gateway_out_x_0 <= gateway_out

  subblock clock_driver pid_sg_full_001_clock_driver {
    sysce => '1' : 'b1
    sysclk => clk_sysgen
    ce_sg => ce_sg
    clk_sg => clk_sg
  }
  subblock pid_sg_full_001_top pid_sg_full_001 {
    ce_sg => ce_sg
    clk_sg => clk_sg
    gateway_in1 => gateway_in1_x_0
    gateway_out => gateway_out_x_0
  }
  subblock xlclkprobe_x_0 xlclkprobe {
    ce => '1' : 'b1
    clk => clk_sysgen
    clr => '0' : 'b0
  }
}
  attrs {
    "reserved_names" => [    ]
    "hdl_arch_attributes" => [    ]
    "hdl_entity_attributes" => [    ]
  }


block pid_sg_full_001_clock_driver {
  port sysce: in "std_logic"  "" 
    attrs {
      "domain" => ""
      "width" => 1
      "period" => 1
      "type" => "logic"
      "is_ce" => true
    }
  port sysclk: in "std_logic"  "" 
    attrs {
      "ce_companion" => "sysce"
      "is_clk" => true
      "domain" => ""
      "type" => "logic"
      "width" => 1
      "period" => 1
    }
  port ce_sg: out "std_logic"  "" 
    attrs {
      "domain" => ""
      "width" => 1
      "rate_pair" => [
        1
        1
      ]
      "type" => "logic"
      "is_ce" => true
    }
  port clk_sg: out "std_logic"  "" 
    attrs {
      "domain" => ""
      "width" => 1
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
}
  attrs {
    "hdl_arch_attributes" => [    ]
    "hdl_entity_attributes" => [    ]
    "hdl_comp_attributes" => [    ]
    "is_clock_driver" => true
  }


block xlclockdriver {
  port sysce: in "std_logic"  "" 
    attrs {
      "width" => 1
    }
  port sysclk: in "std_logic"  "" 
    attrs {
      "width" => 1
    }
  port sysclr: in "std_logic"  "" 
    attrs {
      "width" => 1
    }
  port ce: out "std_logic"  "" 
    attrs {
      "width" => 1
      "type" => "logic"
      "is_ce" => true
    }
  port clk: out "std_logic"  "" 
    attrs {
      "width" => 1
      "ce_companion" => "ce"
      "is_clk" => true
      "type" => "logic"
    }
}
  attrs {
    "generics" => [
      [
        "period"
        "integer"
        "1"
      ]
      [
        "use_bufg"
        "boolean"
        "false"
      ]
    ]
    "hdl_comp_attributes" => [    ]
  }


block pid_sg_full_001 {
  port ce_sg: in "std_logic"  "" 
    attrs {
      "domain" => ""
      "width" => 1
      "rate_pair" => [
        1
        1
      ]
      "type" => "logic"
      "is_ce" => true
    }
  port clk_sg: in "std_logic"  "" 
    attrs {
      "domain" => ""
      "width" => 1
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port gateway_in1: in "std_logic_vector(15 downto 0)"  "[15 : 0]" 
    attrs {
      "bin_pt" => 4
      "timing_constraint" => "none"
      "is_gateway_port" => true
      "simulink_name" => "pid_sg_full_001/Gateway In1"
      "type" => "Fix_16_4"
      "width" => 16
      "period" => 1
    }
  port gateway_out: out "std_logic_vector(19 downto 0)"  "[19 : 0]" 
    attrs {
      "bin_pt" => 8
      "timing_constraint" => "none"
      "is_gateway_port" => true
      "simulink_name" => "pid_sg_full_001/Gateway Out"
      "type" => "Fix_20_8"
      "width" => 20
      "period" => 1
    }
}
  attrs {
    "simulink_name" => "pid_sg_full_001"
    "is_top_level" => true
    "hdl_comp_attributes" => [    ]
  }


block xlclkprobe {
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
    }
  port fakeoutforxst: out "std_logic"  "" 
    attrs {
      "width" => 1
    }
}
  attrs {
    "hdl_comp_attributes" => [    ]
  }

attrs {
  "hdl_kind" => "vhdl"
  "version" => "6.2"
  "system_clock_period" => 100
  "sysgen" => "C:/MATLAB6p5/toolbox/xilinx/sysgen"
  "design" => "pid_sg_full_001"
  "top_level" => "pid_sg_full_001"
  "matlab_perl_directory" => "C:/MATLAB6p5/sys/perl/win32/bin/"
  "matlab_java_directory" => "C:/MATLAB6p5/sys/java/jre/win32/jre/bin"
  "stop_time" => 30
  "config_script" => "C:/MATLAB6p5/work/xpid_sg_full_001/temp/pid_sg_full_001_config.m"
  "vhdl" => [  ]
  "xilinx" => "C:/Xilinx"
  "verilog" => [  ]
  "mdl_path" => "c:/documents and settings/isnique&amy/my documents/skripsi/flash 4mar05/pid_sg_full_001.mdl"
  "clock_wrapper" => "pid_sg_full_001_clk_wrapper"
  "clocks_gcd" => 0.01
  "design_file" => "C:/Matlab6p5/work/xpid_sg_full_001/temp/pid_sg_full_001.vhd"
  "verilog_header_comment" => [
    ""
    "// -----------------------------------------------------------------"
    "// System Generator version 6.2 verilog source file."
    "// "
    "// Copyright(C) 2005 by Xilinx, Inc.  All rights reserved.  This"
    "// text/file contains proprietary, confidential information of Xilinx,"
    "// Inc., is distributed under license from Xilinx, Inc., and may be used,"
    "// copied and/or disclosed only pursuant to the terms of a valid license"
    "// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use"
    "// this text/file solely for design, simulation, implementation and"
    "// creation of design files limited to Xilinx devices or technologies."
    "// Use with non-Xilinx devices or technologies is expressly prohibited"
    "// and immediately terminates your license unless covered by a separate"
    "// agreement."
    "// "
    "// Xilinx is providing this design, code, or information \"as is\" solely"
    "// for use in developing programs and solutions for Xilinx devices.  By"
    "// providing this design, code, or information as one possible"
    "// implementation of this feature, application or standard, Xilinx is"
    "// making no representation that this implementation is free from any"
    "// claims of infringement.  You are responsible for obtaining any rights"
    "// you may require for your implementation.  Xilinx expressly disclaims"
    "// any warranty whatsoever with respect to the adequacy of the"
    "// implementation, including but not limited to any warranties or"
    "// representations that this implementation is free from claims of"
    "// infringement, implied warranties of merchantability or fitness for a"
    "// particular purpose."
    "// "
    "// Xilinx products are not intended for use in life support appliances,"
    "// devices, or systems.  Use in such applications is expressly prohibited."
    "// "
    "// Any modifications that are made to source code are done at the user’s"
    "// sole risk and will be unsupported."
    "// "
    "// This copyright and support notice must be retained as part of this"
    "// text at all times.  (c) Copyright 1995-2005 Xilinx, Inc. "
    "// All rights reserved."
    "// -----------------------------------------------------------------"
    ""
  ]
  "vhdl_header_comment" => [
    ""
    "-- -----------------------------------------------------------------"
    "-- System Generator version 6.2 vhdl source file."
    "-- "
    "-- Copyright(C) 2005 by Xilinx, Inc.  All rights reserved.  This"
    "-- text/file contains proprietary, confidential information of Xilinx,"
    "-- Inc., is distributed under license from Xilinx, Inc., and may be used,"
    "-- copied and/or disclosed only pursuant to the terms of a valid license"
    "-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use"
    "-- this text/file solely for design, simulation, implementation and"
    "-- creation of design files limited to Xilinx devices or technologies."
    "-- Use with non-Xilinx devices or technologies is expressly prohibited"
    "-- and immediately terminates your license unless covered by a separate"
    "-- agreement."
    "-- "
    "-- Xilinx is providing this design, code, or information \"as is\" solely"
    "-- for use in developing programs and solutions for Xilinx devices.  By"
    "-- providing this design, code, or information as one possible"
    "-- implementation of this feature, application or standard, Xilinx is"
    "-- making no representation that this implementation is free from any"
    "-- claims of infringement.  You are responsible for obtaining any rights"
    "-- you may require for your implementation.  Xilinx expressly disclaims"
    "-- any warranty whatsoever with respect to the adequacy of the"
    "-- implementation, including but not limited to any warranties or"
    "-- representations that this implementation is free from claims of"
    "-- infringement, implied warranties of merchantability or fitness for a"
    "-- particular purpose."
    "-- "
    "-- Xilinx products are not intended for use in life support appliances,"
    "-- devices, or systems.  Use in such applications is expressly prohibited."
    "-- "
    "-- Any modifications that are made to source code are done at the user’s"
    "-- sole risk and will be unsupported."
    "-- "
    "-- This copyright and support notice must be retained as part of this"
    "-- text at all times.  (c) Copyright 1995-2005 Xilinx, Inc. "
    "-- All rights reserved."
    "-- -----------------------------------------------------------------"
    ""
  ]
  "device" => "xc2s50-6pq208"
  "start_time" => 0
  "clock_wrapper_file" => "pid_sg_full_001_clk_wrapper.vhd"
  "part_family" => "Spartan2"
  "coregen_part_family" => "Spartan2"
  "target_dir" => "C:/Matlab6p5/work/xpid_sg_full_001"
  "ise_version" => "6.2i"
  "hdl_files" => [
    "conv_pkg.vhd"
    "clock_pkg.vhd"
    "synth_reg.vhd"
    "synth_reg_w_init.vhd"
    "xlclkprobe.vhd"
    "xlclockdriver.vhd"
    "xlclockgenerator.vhd"
    "xlsl2slv.vhd"
    "xlslv2sl.vhd"
    "synth_addsub.vhd"
    "pid_sg_full_001_addsub1.vhd"
    "synth_addsub.vhd"
    "synth_addsub.vhd"
    "synth_addsub.vhd"
    "synth_addsub.vhd"
    "synth_addsub.vhd"
    "pid_sg_full_001_cmult3.vhd"
    "xldelay.vhd"
    "pid_sg_full_001.vhd"
    "pid_sg_full_001_clock_driver.vhd"
    "pid_sg_full_001_clk_wrapper.vhd"
  ]
  "synthesis_tool" => "XST"
}
