-- C:\MATLAB6P5\WORK\ISNIAMY\XTEST_PID
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Apr 21 16:26:38 2005
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.CONV_PKG.ALL;
USE WORK.CLOCK_PKG.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test_pid_tbw IS
END test_pid_tbw;

ARCHITECTURE testbench_arch OF test_pid_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT test_pid_clk_wrapper
		PORT (
			ce : In  std_logic;
			clk : In  std_logic;
			gateway_in1 : In  std_logic_vector (15 DOWNTO 0);
			gateway_out : Out  std_logic_vector (15 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL ce : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL gateway_in1 : std_logic_vector (15 DOWNTO 0);
	SIGNAL gateway_out : std_logic_vector (15 DOWNTO 0);

BEGIN
	UUT : test_pid_clk_wrapper
	PORT MAP (
		ce => ce,
		clk => clk,
		gateway_in1 => gateway_in1,
		gateway_out => gateway_out
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		clk <= transport '1';
		WAIT FOR 10 ns;
		WAIT FOR 40 ns;
		clk <= transport '0';
		WAIT FOR 40 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_gateway_out(
			next_gateway_out : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (gateway_out /= next_gateway_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns gateway_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, gateway_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_gateway_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		ce <= transport '1';
		gateway_in1 <= transport std_logic_vector'("0000000000010000"); --10
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		gateway_in1 <= transport std_logic_vector'("0000000000010001"); --11
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		gateway_in1 <= transport std_logic_vector'("0000000000010010"); --12
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		gateway_in1 <= transport std_logic_vector'("0000000000010011"); --13
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		gateway_in1 <= transport std_logic_vector'("0000000000010100"); --14
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		gateway_in1 <= transport std_logic_vector'("0000000000010101"); --15
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		gateway_in1 <= transport std_logic_vector'("0000000000010110"); --16
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		gateway_in1 <= transport std_logic_vector'("0000000000010111"); --17
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		gateway_in1 <= transport std_logic_vector'("0000000000011000"); --18
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		gateway_in1 <= transport std_logic_vector'("0000000000011001"); --19
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		gateway_in1 <= transport std_logic_vector'("0000000000011010"); --1A
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		gateway_in1 <= transport std_logic_vector'("0000000000011011"); --1B
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		gateway_in1 <= transport std_logic_vector'("0000000000011100"); --1C
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		gateway_in1 <= transport std_logic_vector'("0000000000011101"); --1D
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		gateway_in1 <= transport std_logic_vector'("0000000000011110"); --1E
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		gateway_in1 <= transport std_logic_vector'("0000000000011111"); --1F
		-- --------------------
		WAIT FOR 100 ns; -- Time=1600 ns
		gateway_in1 <= transport std_logic_vector'("0000000000100000"); --20
		-- --------------------
		WAIT FOR 100 ns; -- Time=1700 ns
		gateway_in1 <= transport std_logic_vector'("0000000000100001"); --21
		-- --------------------
		WAIT FOR 100 ns; -- Time=1800 ns
		gateway_in1 <= transport std_logic_vector'("0000000000100010"); --22
		-- --------------------
		WAIT FOR 100 ns; -- Time=1900 ns
		gateway_in1 <= transport std_logic_vector'("0000000000100011"); --23
		-- --------------------
		WAIT FOR 100 ns; -- Time=2000 ns
		gateway_in1 <= transport std_logic_vector'("0000000000100100"); --24
		-- --------------------
		WAIT FOR 100 ns; -- Time=2100 ns
		gateway_in1 <= transport std_logic_vector'("0000000000100101"); --25
		-- --------------------
		WAIT FOR 100 ns; -- Time=2200 ns
		gateway_in1 <= transport std_logic_vector'("0000000000100110"); --26
		-- --------------------
		WAIT FOR 100 ns; -- Time=2300 ns
		gateway_in1 <= transport std_logic_vector'("0000000000100111"); --27
		-- --------------------
		WAIT FOR 100 ns; -- Time=2400 ns
		gateway_in1 <= transport std_logic_vector'("0000000000101000"); --28
		-- --------------------
		WAIT FOR 100 ns; -- Time=2500 ns
		gateway_in1 <= transport std_logic_vector'("0000000000101001"); --29
		-- --------------------
		WAIT FOR 100 ns; -- Time=2600 ns
		gateway_in1 <= transport std_logic_vector'("0000000000101010"); --2A
		-- --------------------
		WAIT FOR 100 ns; -- Time=2700 ns
		gateway_in1 <= transport std_logic_vector'("0000000000101011"); --2B
		-- --------------------
		WAIT FOR 100 ns; -- Time=2800 ns
		gateway_in1 <= transport std_logic_vector'("0000000000101100"); --2C
		-- --------------------
		WAIT FOR 100 ns; -- Time=2900 ns
		gateway_in1 <= transport std_logic_vector'("0000000000101101"); --2D
		-- --------------------
		WAIT FOR 100 ns; -- Time=3000 ns
		gateway_in1 <= transport std_logic_vector'("0000000000101110"); --2E
		-- --------------------
		WAIT FOR 100 ns; -- Time=3100 ns
		gateway_in1 <= transport std_logic_vector'("0000000000101111"); --2F
		-- --------------------
		WAIT FOR 100 ns; -- Time=3200 ns
		gateway_in1 <= transport std_logic_vector'("0000000000110000"); --30
		-- --------------------
		WAIT FOR 100 ns; -- Time=3300 ns
		gateway_in1 <= transport std_logic_vector'("0000000000110001"); --31
		-- --------------------
		WAIT FOR 100 ns; -- Time=3400 ns
		gateway_in1 <= transport std_logic_vector'("0000000000110010"); --32
		-- --------------------
		WAIT FOR 100 ns; -- Time=3500 ns
		gateway_in1 <= transport std_logic_vector'("0000000000110011"); --33
		-- --------------------
		WAIT FOR 100 ns; -- Time=3600 ns
		gateway_in1 <= transport std_logic_vector'("0000000000110100"); --34
		-- --------------------
		WAIT FOR 100 ns; -- Time=3700 ns
		gateway_in1 <= transport std_logic_vector'("0000000000110101"); --35
		-- --------------------
		WAIT FOR 100 ns; -- Time=3800 ns
		gateway_in1 <= transport std_logic_vector'("0000000000110110"); --36
		-- --------------------
		WAIT FOR 100 ns; -- Time=3900 ns
		gateway_in1 <= transport std_logic_vector'("0000000000110111"); --37
		-- --------------------
		WAIT FOR 100 ns; -- Time=4000 ns
		gateway_in1 <= transport std_logic_vector'("0000000000111000"); --38
		-- --------------------
		WAIT FOR 100 ns; -- Time=4100 ns
		gateway_in1 <= transport std_logic_vector'("0000000000111001"); --39
		-- --------------------
		WAIT FOR 100 ns; -- Time=4200 ns
		gateway_in1 <= transport std_logic_vector'("0000000000111010"); --3A
		-- --------------------
		WAIT FOR 100 ns; -- Time=4300 ns
		gateway_in1 <= transport std_logic_vector'("0000000000111011"); --3B
		-- --------------------
		WAIT FOR 100 ns; -- Time=4400 ns
		gateway_in1 <= transport std_logic_vector'("0000000000111100"); --3C
		-- --------------------
		WAIT FOR 100 ns; -- Time=4500 ns
		gateway_in1 <= transport std_logic_vector'("0000000000111101"); --3D
		-- --------------------
		WAIT FOR 100 ns; -- Time=4600 ns
		gateway_in1 <= transport std_logic_vector'("0000000000111110"); --3E
		-- --------------------
		WAIT FOR 100 ns; -- Time=4700 ns
		gateway_in1 <= transport std_logic_vector'("0000000000111111"); --3F
		-- --------------------
		WAIT FOR 100 ns; -- Time=4800 ns
		gateway_in1 <= transport std_logic_vector'("0000000001000000"); --40
		-- --------------------
		WAIT FOR 100 ns; -- Time=4900 ns
		gateway_in1 <= transport std_logic_vector'("0000000001000001"); --41
		-- --------------------
		WAIT FOR 100 ns; -- Time=5000 ns
		ce <= transport '0';
		-- --------------------
		WAIT FOR 110 ns; -- Time=5110 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION test_pid_clk_wrapper_cfg OF test_pid_tbw IS
	FOR testbench_arch
	END FOR;
END test_pid_clk_wrapper_cfg;
