Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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CPU : 0.00 / 0.66 s | Elapsed : 0.00 / 0.00 s
 
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity spartan2_addsub1 is up to date.
Architecture behavior of Entity spartan2_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity spartan2 is up to date.
Architecture structural of Entity spartan2_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xspartan2/spartan2_clk_wrapper.vhd in Library work.
Architecture structural of Entity spartan2_clk_wrapper is up to date.
CPU : 0.30 / 0.95 s | Elapsed : 1.00 / 1.00 s
 
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Total memory usage is 47836 kilobytes


