

block add {
  port ce_sg: in "std_logic"  "" 
    attrs {
      "width" => 1
      "domain" => ""
      "rate_pair" => [
        1
        1
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk_sg: in "std_logic"  "" 
    attrs {
      "width" => 1
      "domain" => ""
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port gateway_in: in "std_logic_vector(7 downto 0)"  "[7 : 0]" 
    attrs {
      "bin_pt" => 4
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "UFix_8_4"
      "simulink_name" => "add/Gateway In"
      "width" => 8
      "period" => 1
    }
  port gateway_in1: in "std_logic_vector(7 downto 0)"  "[7 : 0]" 
    attrs {
      "bin_pt" => 4
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "UFix_8_4"
      "simulink_name" => "add/Gateway In1"
      "width" => 8
      "period" => 1
    }
  port gateway_out1: out "std_logic_vector(11 downto 0)"  "[11 : 0]" 
    attrs {
      "bin_pt" => 4
      "is_gateway_port" => true
      "timing_constraint" => "none"
      "type" => "UFix_12_4"
      "simulink_name" => "add/Gateway Out1"
      "width" => 12
      "period" => 1
    }


  ce_sg <= ce_sg_x_0
  clk_sg <= clk_sg_x_0
  gateway_in <= gateway_in_x_0
  gateway_in1 <= gateway_in1_x_0
  s <= gateway_out1

  subblock addsub add_addsub {
    a => gateway_in_x_0
    b => gateway_in1_x_0
    ce => ce_sg_x_0
    clk => clk_sg_x_0
    clr => '0' : 'b0
    en => dout
    rst => dout_x_0
    s => s
  }
  subblock x xlsl2slv {
    din => '1' : 'b1
    dout => dout
  }
  subblock x_x_0 xlsl2slv {
    din => '0' : 'b0
    dout => dout_x_0
  }
}
  attrs {
    "simulink_name" => "add"
    "is_top_level" => true
  }


block add_addsub {
  port a: in "std_logic_vector(a_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 4
      "must_be_hdl_vector" => true
      "type" => "UFix_8_4"
      "simulink_name" => "add/AddSub/a"
      "width" => 8
      "period" => 1
    }
  port b: in "std_logic_vector(b_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "2"
      "bin_pt" => 4
      "must_be_hdl_vector" => true
      "type" => "UFix_8_4"
      "simulink_name" => "add/AddSub/b"
      "width" => 8
      "period" => 1
    }
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "rate_pair" => [
        1
        1
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "type" => "logic"
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "4"
      "simulink_name" => "add/AddSub/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port rst: in "std_logic_vector(rst_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "3"
      "simulink_name" => "add/AddSub/rst"
      "period" => -1
      "width" => 1
      "dangling_value" => 0
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port s: out "std_logic_vector(s_width - 1 downto 0)"  "[11 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 4
      "must_be_hdl_vector" => true
      "type" => "UFix_12_4"
      "simulink_name" => "add/AddSub/s"
      "width" => 12
      "period" => 1
    }
}
  attrs {
    "simulink_name" => "add/AddSub"
    "generics" => [
      [
        "a_width"
        "integer"
        "8"
      ]
      [
        "a_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "a_bin_pt"
        "integer"
        "4"
      ]
      [
        "b_width"
        "integer"
        "8"
      ]
      [
        "b_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "b_bin_pt"
        "integer"
        "4"
      ]
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "rst_width"
        "integer"
        "1"
      ]
      [
        "rst_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "rst_bin_pt"
        "integer"
        "0"
      ]
      [
        "s_width"
        "integer"
        "12"
      ]
      [
        "s_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "s_bin_pt"
        "integer"
        "4"
      ]
      [
        "core_name0"
        "string"
        "\"adder_subtracter_spartan2_6_0_565e6fc4f8af6f53\""
      ]
      [
        "c_a_type"
        "integer"
        "1"
      ]
      [
        "c_a_width"
        "integer"
        "9"
      ]
      [
        "c_add_mode"
        "integer"
        "0"
      ]
      [
        "c_b_type"
        "integer"
        "1"
      ]
      [
        "c_b_width"
        "integer"
        "9"
      ]
      [
        "c_enable_rlocs"
        "integer"
        "1"
      ]
      [
        "c_has_b_in"
        "integer"
        "0"
      ]
      [
        "c_has_b_out"
        "integer"
        "0"
      ]
      [
        "c_has_c_in"
        "integer"
        "0"
      ]
      [
        "c_has_c_out"
        "integer"
        "0"
      ]
      [
        "c_has_ce"
        "integer"
        "1"
      ]
      [
        "c_has_q"
        "integer"
        "1"
      ]
      [
        "c_has_q_b_out"
        "integer"
        "0"
      ]
      [
        "c_has_q_c_out"
        "integer"
        "0"
      ]
      [
        "c_has_s"
        "integer"
        "0"
      ]
      [
        "c_has_sclr"
        "integer"
        "1"
      ]
      [
        "c_latency"
        "integer"
        "1"
      ]
      [
        "c_output_width"
        "integer"
        "9"
      ]
      [
        "core"
        "boolean"
        "true"
      ]
      [
        "extra_registers"
        "integer"
        "0"
      ]
      [
        "full_s_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "full_s_width"
        "integer"
        "9"
      ]
      [
        "latency"
        "integer"
        "1"
      ]
      [
        "mode"
        "integer"
        "1"
      ]
      [
        "overflow"
        "integer"
        "xlWrap"
      ]
      [
        "quantization"
        "integer"
        "xlTruncate"
      ]
    ]
  }


block xlsl2slv {
  port din: in "std_logic"  "" 
    attrs {
      "width" => 1
      "type" => "logic"
      "period" => -1
    }
  port dout: out "std_logic_vector(dout_width - 1 downto 0)"  "" 
    attrs {
      "width" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
      "period" => -1
    }
}
  attrs {
    "generics" => [
      [
        "dout_width"
        "integer"
        "1"
      ]
      [
        "dout_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "dout_bin_pt"
        "integer"
        "0"
      ]
    ]
  }

attrs {
  "matlab_java_directory" => "C:/MATLAB6p5/sys/java/jre/win32/jre/bin"
  "clocks_gcd" => 0.01
  "mdl_path" => "C:/MATLAB6p5/work/isniamy/add.mdl"
  "design_file" => "C:/MATLAB6p5/work/isniamy/xadd/temp/add.vhd"
  "config_script" => "C:/MATLAB6p5/work/isniamy/xadd/temp/add_config.m"
  "part_family" => "Spartan2"
  "device" => "xc2s50-6pq208"
  "coregen_part_family" => "Spartan2"
  "synthesis_tool" => "XST"
  "hdl_kind" => "vhdl"
  "start_time" => 0
  "xilinx" => "C:/xilinx_62i"
  "system_clock_period" => 100
  "target_dir" => "C:/MATLAB6p5/work/isniamy/xadd"
  "stop_time" => 10
  "matlab_perl_directory" => "C:/MATLAB6p5/sys/perl/win32/bin/"
  "version" => "6.2"
  "ise_version" => "6.2i"
  "top_level" => "add"
  "hdl_files" => [
    "conv_pkg.vhd"
    "clock_pkg.vhd"
    "synth_reg.vhd"
    "synth_reg_w_init.vhd"
    "xlclkprobe.vhd"
    "xlclockdriver.vhd"
    "xlclockgenerator.vhd"
    "xlsl2slv.vhd"
    "xlslv2sl.vhd"
    "synth_addsub.vhd"
    "add_addsub.vhd"
    "add.vhd"
  ]
  "design" => "add"
  "vhdl" => [  ]
  "verilog" => [  ]
  "sysgen" => "C:/MATLAB6p5/toolbox/xilinx/sysgen"
}
