Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

MAKASSAR-B3XVCS::  Sun Mar 27 21:11:46 2005


par.exe -w -intstyle ise -ol high -t 1 -n 3 pid_sg_full_001_clk_wrapper_map.ncd
mppr_result.dir pid_sg_full_001_clk_wrapper.pcf 


Constraints file: pid_sg_full_001_clk_wrapper.pcf

Loading device database for application Par from file
"C:/DOCUME~1/ISNIQU~1/LOCALS~1/Temp/xil_2192_4".
   "pid_sg_full_001_clk_wrapper" is an NCD, version 2.38, device xc2s50, package
pq208, speed -6
Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            36 out of 140    25%
      Number of LOCed External IOBs    0 out of 36      0%


   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   High (set by user)
Placer effort level (-pl):    High (set by user)
Placer cost table entry (-t): 2
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:989907) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
...........
.
...........
.
.
Phase 5.8 (Checksum:9edb61) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs 

Writing design to file mppr_result.dir/5_5_2.ncd.

Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 4 secs 


Phase 1: 980 unrouted;       REAL time: 5 secs 

Phase 2: 946 unrouted;       REAL time: 5 secs 

Phase 3: 232 unrouted;       REAL time: 5 secs 

Phase 4: 232 unrouted; (0)      REAL time: 5 secs 

Phase 5: 232 unrouted; (0)      REAL time: 5 secs 

Phase 6: 232 unrouted; (0)      REAL time: 5 secs 

Phase 7: 0 unrouted; (0)      REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   34   |  0.078     |  0.463      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 214


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.424
   The MAXIMUM PIN DELAY IS:                               4.607
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.602

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         333         407         203          26          11           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_63882cc5 = PERIOD TIMEGRP "clk_638 | 100.000ns  | 28.276ns   | 15   
  82cc5"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  56 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file mppr_result.dir/5_5_2.ncd.


PAR done.
