Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.06 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.06 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: simple1.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : simple1.prj
Input Format                       : mixed
Synthesis Constraint File          : .\simple1_clk_wrapper.xcf
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : simple1
Output Format                      : NGC
Target Device                      : xc2s50-6-pq208

---- Source Options
Top Module Name                    : simple1
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : YES
Hierarchy Separator                : _
Bus Delimiter                      : ()
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : simple1.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.


Reading constraint file .\simple1_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <simple1>.
    Related source file is C:/MATLAB6p5/work/isniamy/xsimple1/simple1_files.vhd.
Unit <simple1> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <simple1> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\simple1_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 10.30 / 11.94 s | Elapsed : 10.00 / 11.00 s
 
--> 

Total memory usage is 70408 kilobytes


