
function pid_data2_config(this_block)
  this_block.setTopLevelLanguage('VHDL');

  this_block.setEntityName('pid_data2');
  this_block.addSimulinkInport('gateway_in1');
  this_block.port('gateway_in1').useHDLVector(true);

  this_block.addSimulinkOutport('gateway_out');
  this_block.port('gateway_out').useHDLVector(true);
  this_block.port('gateway_out').setType('Fix_24_16');

  this_block.tagAsCombinational;

% -----------------------------
  % Do input type checking, and dynamic output type and 
  % generic setup here.
  if (this_block.inputTypesKnown)
    if (~ strcmp('Fix_16_8', this_block.port('gateway_in1').type))
      this_block.setError('Input data type for port "gateway_in1" must be "Fix_16_8".');
    end
  end

% -----------------------------

% -----------------------------
% Do input rate checking here.
  if (this_block.inputRatesKnown)
    if (this_block.port('gateway_in1').rate ~= 1)
      this_block.setError('Rate for port "gateway_in1" must be 1.');
    end
  end

% -----------------------------

% -----------------------------
% Set output rates here.
  this_block.port('gateway_out').setRate(1);


% -----------------------------
% Set up clocks and clock enables here.
  this_block.addClkCEPair('clk_sg', 'ce_sg', 1);


% -----------------------------
% Set up vhdl/verilog files here.
  this_block.addFile('xdcsp2/temp/conv_pkg.vhd');
  this_block.addFile('xdcsp2/temp/clock_pkg.vhd');
  this_block.addFile('xdcsp2/temp/synth_reg.vhd');
  this_block.addFile('xdcsp2/temp/synth_reg_w_init.vhd');
  this_block.addFile('xdcsp2/temp/xlclkprobe.vhd');
  this_block.addFile('xdcsp2/temp/xlclockdriver.vhd');
  this_block.addFile('xdcsp2/temp/xlclockgenerator.vhd');
  this_block.addFile('xdcsp2/temp/xlsl2slv.vhd');
  this_block.addFile('xdcsp2/temp/xlslv2sl.vhd');
  this_block.addFile('xdcsp2/temp/synth_addsub.vhd');
  this_block.addFile('xdcsp2/temp/pid_data2_addsub1.vhd');
  this_block.addFile('xdcsp2/temp/synth_addsub.vhd');
  this_block.addFile('xdcsp2/temp/synth_addsub.vhd');
  this_block.addFile('xdcsp2/temp/synth_addsub.vhd');
  this_block.addFile('xdcsp2/temp/synth_addsub.vhd');
  this_block.addFile('xdcsp2/temp/synth_addsub.vhd');
  this_block.addFile('xdcsp2/temp/pid_data2_cmult3.vhd');
  this_block.addFile('xdcsp2/temp/xldelay.vhd');
  this_block.addFile('xdcsp2/temp/pid_data2.vhd');


% -----------------------------
% Set up .edn, .mif, .coe, ... files here.
  this_block.addFile('xdcsp2/temp/adder_subtracter_spartan2_6_0_3c5aefdfc1b01b25.edn');
  this_block.addFile('xdcsp2/temp/adder_subtracter_spartan2_6_0_5f14a66727c3a329.edn');
  this_block.addFile('xdcsp2/temp/adder_subtracter_spartan2_6_0_86c498140491d6df.edn');
  this_block.addFile('xdcsp2/temp/adder_subtracter_spartan2_6_0_90518b17c7b8e21d.edn');
  this_block.addFile('xdcsp2/temp/adder_subtracter_spartan2_6_0_a29cdc21716c36c2.edn');
  this_block.addFile('xdcsp2/temp/adder_subtracter_spartan2_6_0_adf215fec985a9ef.edn');
  this_block.addFile('xdcsp2/temp/multiplier_spartan2_6_0_036246fc9fb44e5b.edn');
  this_block.addFile('xdcsp2/temp/multiplier_spartan2_6_0_267a17cb29b4917a.edn');
  this_block.addFile('xdcsp2/temp/multiplier_spartan2_6_0_dd3f2ed519f74c1b.edn');
  this_block.addFile('xdcsp2/temp/multiplier_spartan2_6_0_de781c7a0a82b6cf.edn');

