# XST (Creating Lso File) : 
clock_pkg.lso
# Check Syntax
clock_pkg.stx
# ProjNav -> New Source -> TBW
C:\MATLAB6p5\work\isniamy\xadd\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
add1_tbw.ado
add1_tbw.ano
# ModelSim : Generate Expected Simulation Results
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
add1_tbw.vhw
add1_tbw.ano
add1_tbw.tfw
# ModelSim : Simulate Behavioral VHDL Model
add1_tbw.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
add1_tbw.ado
add1_tbw.ano
# ProjNav -> New Source -> TBW
C:\MATLAB6p5\work\isniamy\xadd\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
add1_tbw.ado
add1_tbw.ano
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
add1_tbw.ado
add1_tbw.ano
# ModelSim : Generate Expected Simulation Results
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
add1_tbw.vhw
add1_tbw.ano
add1_tbw.tfw
# ModelSim : Simulate Behavioral VHDL Model
add1_tbw.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
add_clk_wrapper.lso
# xst flow : RunXST
add_clk_wrapper.syr
add_clk_wrapper.prj
add_clk_wrapper.sprj
add_clk_wrapper.ana
add_clk_wrapper.stx
add_clk_wrapper.cmd_log
add_clk_wrapper.ngc
add_clk_wrapper.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\matlab6p5\work\isniamy\xadd/_ngo
add_clk_wrapper.ngd
add_clk_wrapper_ngdbuild.nav
add_clk_wrapper.bld
.untf
add_clk_wrapper.cmd_log
# Implementation : Map
add_clk_wrapper_map.ncd
add_clk_wrapper.ngm
add_clk_wrapper.pcf
add_clk_wrapper.nc1
add_clk_wrapper.mrp
add_clk_wrapper_map.mrp
add_clk_wrapper.mdf
__projnav/map.log
add_clk_wrapper.cmd_log
MAP_NO_GUIDE_FILE_CPF "add_clk_wrapper"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
add_clk_wrapper.twr
add_clk_wrapper.twx
add_clk_wrapper.tsi
add_clk_wrapper.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
add_clk_wrapper.ncd
add_clk_wrapper.par
add_clk_wrapper.pad
add_clk_wrapper_pad.txt
add_clk_wrapper_pad.csv
add_clk_wrapper.pad_txt
add_clk_wrapper.dly
reportgen.log
add_clk_wrapper.xpi
add_clk_wrapper.grf
add_clk_wrapper.itr
add_clk_wrapper_last_par.ncd
__projnav/par.log
add_clk_wrapper.placed_ncd_tracker
add_clk_wrapper.routed_ncd_tracker
add_clk_wrapper.cmd_log
PAR_NO_GUIDE_FILE_CPF "add_clk_wrapper"
# Implmentation : View/Edit Placed Design (Floorplanner)
__projnav/parFloorPlanner.rsp
add_clk_wrapper.mfp
# Implementation : View/Edit Routed Design (FPGA Editor)
add_clk_wrapper_map_fpga_editor.log
add_clk_wrapper_fpga_editor.out
add_clk_wrapper_fpga_editor.log
__projnav/pfea_tcl.rsp
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
C:\MATLAB6p5\work\isniamy\xadd\__projnav\hb_cmds
# ProjNav -> New Source -> TBW
C:\MATLAB6p5\work\isniamy\xadd\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
add1_tbw.ado
add1_tbw.ano
# ModelSim : Generate Expected Simulation Results
