module seg7_driver (clk_200hz, reset, dig0, dig1, dig2, anode0, anode1, anode2, anode3, digit);


input clk_200hz,reset;
input [7:0] dig0, dig1, dig2;

output anode0, anode1, anode2, anode3;
output [7:0] digit;

reg [1:0] clk_int;
reg [7:0] digit;
reg anode0, anode1, anode2, anode3;

wire [7:0] dig3;
assign dig3 = 8'b11111111;

// timing anode
always @ (posedge clk_200hz or posedge reset)
begin
	if (reset)
		begin
		clk_int = 0;
		{anode0, anode1, anode2, anode3} = 4'b0111;
		end
	else
		begin
		clk_int = clk_int + 1;
		case (clk_int)
		2'b00: {anode0, anode1, anode2, anode3} = 4'b0111;
		2'b01: {anode0, anode1, anode2, anode3} = 4'b1011;
		2'b10: {anode0, anode1, anode2, anode3} = 4'b1101;
		3'b11: {anode0, anode1, anode2, anode3} = 4'b1110;
		default {anode0, anode1, anode2, anode3} = 4'b0111;
		endcase
		end
end

always @ (anode0 or anode1 or anode2 or anode3 or
          dig0 or dig1 or dig2 or dig3)
	if (anode0 == 1'b0)
			digit <= ~dig0;
	else if (anode1 == 1'b0)
			digit <= ~dig1;
	else if (anode2 == 1'b0)
			digit <= ~dig2;
	else
			digit <= ~dig3;

endmodule




