-- Xilinx Vhdl netlist produced by netgen application (version G.28)
-- Command       : -intstyle ise -s 6 -pcf test2_clk_wrapper.pcf -ngm test2_clk_wrapper.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim test2_clk_wrapper.ncd test2_clk_wrapper_timesim.vhd 
-- Input file    : test2_clk_wrapper.ncd
-- Output file   : test2_clk_wrapper_timesim.vhd
-- Design name   : test2_clk_wrapper
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : 2s50pq208-6 (PRODUCTION 1.27 2003-12-13)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity test2_clk_wrapper is
  port (
    ce : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    gateway_out : out STD_LOGIC_VECTOR ( 19 downto 0 ); 
    gateway_in1 : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end test2_clk_wrapper;

architecture Structure of test2_clk_wrapper is
  signal test2_top_addsub5_core_instance8_N100 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N110 : STD_LOGIC; 
  signal gateway_in1_15_IBUF : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N20 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N30 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N120 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N130 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N90 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N10 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N80 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N70 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N60 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N50 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N150 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N40 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N140 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N253 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N252 : STD_LOGIC; 
  signal gateway_in1_3_IBUF : STD_LOGIC; 
  signal gateway_in1_4_IBUF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N249 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N248 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N255 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N254 : STD_LOGIC; 
  signal gateway_in1_1_IBUF : STD_LOGIC; 
  signal gateway_in1_2_IBUF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N251 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N250 : STD_LOGIC; 
  signal gateway_in1_0_IBUF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N257 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N256 : STD_LOGIC; 
  signal gateway_in1_13_IBUF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N258 : STD_LOGIC; 
  signal gateway_in1_14_IBUF : STD_LOGIC; 
  signal gateway_in1_11_IBUF : STD_LOGIC; 
  signal gateway_in1_12_IBUF : STD_LOGIC; 
  signal gateway_in1_9_IBUF : STD_LOGIC; 
  signal gateway_in1_10_IBUF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N243 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N242 : STD_LOGIC; 
  signal gateway_in1_7_IBUF : STD_LOGIC; 
  signal gateway_in1_8_IBUF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N245 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N244 : STD_LOGIC; 
  signal gateway_in1_5_IBUF : STD_LOGIC; 
  signal gateway_in1_6_IBUF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N247 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N246 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N40 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N50 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N110 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N120 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N30 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N100 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N20 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N90 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N10 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N80 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N70 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N60 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N230 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N229 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N216 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N215 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N232 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N231 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N218 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N217 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N234 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N233 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N220 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N219 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N236 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N235 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N222 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N221 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N237 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N224 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N223 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N226 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N225 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N228 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N227 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N214 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7211 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7221 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N923 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1991 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N922 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1990 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1700 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1701 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2122 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2121 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1992 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6205 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1989 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1988 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N957 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N956 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5408 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1568 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1567 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7281 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N945 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N925 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N924 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7271 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N947 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N946 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6255 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2111 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5458 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N915 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1690 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1689 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N917 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N916 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7261 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N949 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N948 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1691 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1561 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1560 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2112 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1982 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1981 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6245 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2113 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5448 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1692 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N919 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N918 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7251 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N951 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N950 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1693 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1563 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1562 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2114 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1984 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1983 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6235 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2115 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1980 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5438 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1694 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1559 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N921 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N920 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7241 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N953 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N952 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1695 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1564 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1565 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2116 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1985 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1986 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6225 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2117 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5428 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1696 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7231 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N955 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N954 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1697 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1566 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2118 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1987 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6215 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2119 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5418 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1698 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1699 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2120 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N60 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N70 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N50 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N40 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N30 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N20 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N10 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N60 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N70 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N110 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N50 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N100 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N40 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N90 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N30 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N80 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N20 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N10 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N10 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N20 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N80 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N70 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N60 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N50 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N40 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N30 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6167 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1171 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2092 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2091 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1173 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1172 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2093 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1978 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1979 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6157 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2094 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1175 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1174 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7746 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1206 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1205 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1225 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1224 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2095 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1980 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1981 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2349 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2350 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6147 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2096 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1977 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1177 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1176 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7736 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1208 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1207 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2097 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1982 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1983 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2351 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2352 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6137 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2098 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1179 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1178 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7726 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1210 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1209 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6830 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2467 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2348 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2466 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2099 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1984 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2468 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2353 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2354 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6127 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2100 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7716 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2355 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6820 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2469 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2101 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2470 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2356 : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal gateway_out_10_OBUF : STD_LOGIC; 
  signal gateway_out_11_OBUF : STD_LOGIC; 
  signal gateway_out_12_OBUF : STD_LOGIC; 
  signal gateway_out_13_OBUF : STD_LOGIC; 
  signal gateway_out_14_OBUF : STD_LOGIC; 
  signal gateway_out_15_OBUF : STD_LOGIC; 
  signal gateway_out_16_OBUF : STD_LOGIC; 
  signal gateway_out_17_OBUF : STD_LOGIC; 
  signal gateway_out_1_OBUF : STD_LOGIC; 
  signal gateway_out_18_OBUF : STD_LOGIC; 
  signal gateway_out_2_OBUF : STD_LOGIC; 
  signal gateway_out_19_OBUF : STD_LOGIC; 
  signal gateway_out_3_OBUF : STD_LOGIC; 
  signal gateway_out_4_OBUF : STD_LOGIC; 
  signal gateway_out_5_OBUF : STD_LOGIC; 
  signal gateway_out_6_OBUF : STD_LOGIC; 
  signal gateway_out_7_OBUF : STD_LOGIC; 
  signal gateway_out_8_OBUF : STD_LOGIC; 
  signal gateway_out_9_OBUF : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N15 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N25 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N35 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N45 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N55 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N65 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N75 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N85 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N95 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_1 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N102 : STD_LOGIC; 
  signal test2_top_s_x_3_6_XORF : STD_LOGIC; 
  signal test2_top_s_x_3_6_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_3_6_XORG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N107 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N105 : STD_LOGIC; 
  signal test2_top_s_x_3_6_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N22 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N30_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N27 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N25 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N30_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N30_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N122 : STD_LOGIC; 
  signal test2_top_s_x_3_10_XORF : STD_LOGIC; 
  signal test2_top_s_x_3_10_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_3_10_XORG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N127 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N125 : STD_LOGIC; 
  signal test2_top_s_x_3_10_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N92 : STD_LOGIC; 
  signal test2_top_s_x_3_4_XORF : STD_LOGIC; 
  signal test2_top_s_x_3_4_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_3_4_XORG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N97 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N95 : STD_LOGIC; 
  signal test2_top_s_x_3_4_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N12 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N20_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N17 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N15 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N20_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N20_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N112 : STD_LOGIC; 
  signal test2_top_s_x_3_8_XORF : STD_LOGIC; 
  signal test2_top_s_x_3_8_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_3_8_XORG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N117 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N115 : STD_LOGIC; 
  signal test2_top_s_x_3_8_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N10_FROM : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N10_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N7 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N5 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N10_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N82 : STD_LOGIC; 
  signal test2_top_s_x_3_2_XORF : STD_LOGIC; 
  signal test2_top_s_x_3_2_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_3_2_XORG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N87 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N85 : STD_LOGIC; 
  signal test2_top_s_x_3_2_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N72 : STD_LOGIC; 
  signal test2_top_s_x_3_0_XORF : STD_LOGIC; 
  signal test2_top_s_x_3_0_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_3_0_XORG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N77 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N75 : STD_LOGIC; 
  signal test2_top_s_x_3_0_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N62 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N70_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N67 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N65 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N70_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N70_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N52 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N60_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N57 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N55 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N60_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N60_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N152 : STD_LOGIC; 
  signal test2_top_s_x_3_16_XORF : STD_LOGIC; 
  signal test2_top_s_x_3_16_XORG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N157 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N155 : STD_LOGIC; 
  signal test2_top_s_x_3_16_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N42 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N50_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N47 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N45 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N50_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N50_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N142 : STD_LOGIC; 
  signal test2_top_s_x_3_14_XORF : STD_LOGIC; 
  signal test2_top_s_x_3_14_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_3_14_XORG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N147 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N145 : STD_LOGIC; 
  signal test2_top_s_x_3_14_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N32 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N40_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N37 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N35 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N40_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N40_CYINIT : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N132 : STD_LOGIC; 
  signal test2_top_s_x_3_12_XORF : STD_LOGIC; 
  signal test2_top_s_x_3_12_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_3_12_XORG : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N137 : STD_LOGIC; 
  signal test2_top_addsub5_core_instance8_N135 : STD_LOGIC; 
  signal test2_top_s_x_3_12_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N42 : STD_LOGIC; 
  signal test2_top_s_x_2_1_XORF : STD_LOGIC; 
  signal test2_top_s_x_2_1_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_2_1_XORG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N47 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N45 : STD_LOGIC; 
  signal test2_top_s_x_2_1_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N112 : STD_LOGIC; 
  signal test2_top_s_x_2_15_XORF : STD_LOGIC; 
  signal test2_top_s_x_2_15_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_2_15_XORG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N117 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N115 : STD_LOGIC; 
  signal test2_top_s_x_2_15_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N32 : STD_LOGIC; 
  signal test2_top_s_x_2_0_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_2_0_XORG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N37 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N35 : STD_LOGIC; 
  signal test2_top_s_x_2_0_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N102 : STD_LOGIC; 
  signal test2_top_s_x_2_13_XORF : STD_LOGIC; 
  signal test2_top_s_x_2_13_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_2_13_XORG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N107 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N105 : STD_LOGIC; 
  signal test2_top_s_x_2_13_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N22 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N30_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N27 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N25 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N30_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N30_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N92 : STD_LOGIC; 
  signal test2_top_s_x_2_11_XORF : STD_LOGIC; 
  signal test2_top_s_x_2_11_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_2_11_XORG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N97 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N95 : STD_LOGIC; 
  signal test2_top_s_x_2_11_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N12 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N20_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N17 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N15 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N20_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N20_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N82 : STD_LOGIC; 
  signal test2_top_s_x_2_9_XORF : STD_LOGIC; 
  signal test2_top_s_x_2_9_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_2_9_XORG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N87 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N85 : STD_LOGIC; 
  signal test2_top_s_x_2_9_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N2 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N10_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N7 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N5 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N10_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N72 : STD_LOGIC; 
  signal test2_top_s_x_2_7_XORF : STD_LOGIC; 
  signal test2_top_s_x_2_7_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_2_7_XORG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N77 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N75 : STD_LOGIC; 
  signal test2_top_s_x_2_7_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N62 : STD_LOGIC; 
  signal test2_top_s_x_2_5_XORF : STD_LOGIC; 
  signal test2_top_s_x_2_5_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_2_5_XORG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N67 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N65 : STD_LOGIC; 
  signal test2_top_s_x_2_5_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N52 : STD_LOGIC; 
  signal test2_top_s_x_2_3_XORF : STD_LOGIC; 
  signal test2_top_s_x_2_3_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_2_3_XORG : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N57 : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N55 : STD_LOGIC; 
  signal test2_top_s_x_2_3_CYINIT : STD_LOGIC; 
  signal test2_top_addsub4_core_instance6_N122 : STD_LOGIC; 
  signal test2_top_s_x_2_17_XORF : STD_LOGIC; 
  signal test2_top_s_x_2_17_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7213 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N228_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N228_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N228_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7218 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7216 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N228_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1700_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1700_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N237_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N237_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2122_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2122_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1992_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1992_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6197 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N957_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N957_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N957_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6202 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6200 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N957_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N957_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5400 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N234_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N234_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N234_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5405 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5403 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N234_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N234_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7283 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N214_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N214_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7203 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N230_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N230_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N230_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7208 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7206 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N230_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N230_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7273 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N216_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N216_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N216_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N216_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7278 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7276 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N216_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6257 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N945_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N945_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5460 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N917_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N917_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N917_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N917_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5465 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5463 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N917_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7263 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N218_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N218_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N218_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N218_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7268 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7266 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N218_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1690_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1690_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1561_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1561_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2112_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2112_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1982_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1982_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6247 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N947_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N947_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N947_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N947_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6252 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6250 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N947_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5450 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N919_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N919_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N919_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N919_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5455 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5453 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N919_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7253 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N220_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N220_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N220_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7258 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7256 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N220_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1693_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1693_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1563_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1563_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2114_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2114_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1984_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1984_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6237 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N949_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N949_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N949_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6242 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6240 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N949_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5440 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N921_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N921_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N921_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5445 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5443 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N921_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7243 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N222_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N222_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N222_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7248 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7246 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N222_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1695_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1695_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1564_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1564_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2115_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2115_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1985_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1985_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6227 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N951_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N951_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N951_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6232 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6230 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N951_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5430 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N923_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N923_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N923_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5435 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5433 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N923_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7233 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N224_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N224_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N224_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7238 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7236 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N224_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1696_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1696_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1566_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1566_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2117_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2117_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1987_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1987_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6217 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N953_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N953_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N953_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6222 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6220 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N953_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5420 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N925_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N925_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N925_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5425 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5423 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N925_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7223 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N226_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N226_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N226_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7228 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N7226 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N226_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1698_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1698_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1568_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1568_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2119_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N2119_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1989_FROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1989_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6207 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N955_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N955_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N955_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6212 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N6210 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N955_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5410 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N232_XORF : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N232_CYMUXG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N232_XORG : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5415 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N5413 : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N232_CYINIT : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1689_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1980_GROM : STD_LOGIC; 
  signal test2_top_kp_core_instance6_N1559_GROM : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N62 : STD_LOGIC; 
  signal test2_top_s_x_1_12_XORF : STD_LOGIC; 
  signal test2_top_s_x_1_12_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_1_12_XORG : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N67 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N65 : STD_LOGIC; 
  signal test2_top_s_x_1_12_CYINIT : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N52 : STD_LOGIC; 
  signal test2_top_s_x_1_10_XORF : STD_LOGIC; 
  signal test2_top_s_x_1_10_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_1_10_XORG : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N57 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N55 : STD_LOGIC; 
  signal test2_top_s_x_1_10_CYINIT : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N42 : STD_LOGIC; 
  signal test2_top_s_x_1_8_XORF : STD_LOGIC; 
  signal test2_top_s_x_1_8_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_1_8_XORG : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N47 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N45 : STD_LOGIC; 
  signal test2_top_s_x_1_8_CYINIT : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N32 : STD_LOGIC; 
  signal test2_top_s_x_1_6_XORF : STD_LOGIC; 
  signal test2_top_s_x_1_6_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_1_6_XORG : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N37 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N35 : STD_LOGIC; 
  signal test2_top_s_x_1_6_CYINIT : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N22 : STD_LOGIC; 
  signal test2_top_s_x_1_4_XORF : STD_LOGIC; 
  signal test2_top_s_x_1_4_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_1_4_XORG : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N27 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N25 : STD_LOGIC; 
  signal test2_top_s_x_1_4_CYINIT : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N12 : STD_LOGIC; 
  signal test2_top_s_x_1_2_XORF : STD_LOGIC; 
  signal test2_top_s_x_1_2_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_1_2_XORG : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N17 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N15 : STD_LOGIC; 
  signal test2_top_s_x_1_2_CYINIT : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N2 : STD_LOGIC; 
  signal test2_top_s_x_1_0_XORF : STD_LOGIC; 
  signal test2_top_s_x_1_0_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_1_0_XORG : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N7 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N5 : STD_LOGIC; 
  signal test2_top_s_x_1_0_CYINIT : STD_LOGIC; 
  signal test2_top_s_x_1_0_LOGIC_ONE : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N72 : STD_LOGIC; 
  signal test2_top_s_x_1_14_XORF : STD_LOGIC; 
  signal test2_top_s_x_1_14_XORG : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N77 : STD_LOGIC; 
  signal test2_top_addsub3_core_instance4_N75 : STD_LOGIC; 
  signal test2_top_s_x_1_14_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N62 : STD_LOGIC; 
  signal test2_top_s_4_XORF : STD_LOGIC; 
  signal test2_top_s_4_CYMUXG : STD_LOGIC; 
  signal test2_top_s_4_XORG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N67 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N65 : STD_LOGIC; 
  signal test2_top_s_4_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N112 : STD_LOGIC; 
  signal test2_top_s_14_XORF : STD_LOGIC; 
  signal test2_top_s_14_XORG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N117 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N115 : STD_LOGIC; 
  signal test2_top_s_14_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N52 : STD_LOGIC; 
  signal test2_top_s_2_XORF : STD_LOGIC; 
  signal test2_top_s_2_CYMUXG : STD_LOGIC; 
  signal test2_top_s_2_XORG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N57 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N55 : STD_LOGIC; 
  signal test2_top_s_2_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N102 : STD_LOGIC; 
  signal test2_top_s_12_XORF : STD_LOGIC; 
  signal test2_top_s_12_CYMUXG : STD_LOGIC; 
  signal test2_top_s_12_XORG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N107 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N105 : STD_LOGIC; 
  signal test2_top_s_12_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N42 : STD_LOGIC; 
  signal test2_top_s_0_XORF : STD_LOGIC; 
  signal test2_top_s_0_CYMUXG : STD_LOGIC; 
  signal test2_top_s_0_XORG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N47 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N45 : STD_LOGIC; 
  signal test2_top_s_0_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N92 : STD_LOGIC; 
  signal test2_top_s_10_XORF : STD_LOGIC; 
  signal test2_top_s_10_CYMUXG : STD_LOGIC; 
  signal test2_top_s_10_XORG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N97 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N95 : STD_LOGIC; 
  signal test2_top_s_10_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N40_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N40_LOGIC_ONE : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N35 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N40_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N82 : STD_LOGIC; 
  signal test2_top_s_8_XORF : STD_LOGIC; 
  signal test2_top_s_8_CYMUXG : STD_LOGIC; 
  signal test2_top_s_8_XORG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N87 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N85 : STD_LOGIC; 
  signal test2_top_s_8_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N30_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N30_LOGIC_ONE : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N25 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N30_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N72 : STD_LOGIC; 
  signal test2_top_s_6_XORF : STD_LOGIC; 
  signal test2_top_s_6_CYMUXG : STD_LOGIC; 
  signal test2_top_s_6_XORG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N77 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N75 : STD_LOGIC; 
  signal test2_top_s_6_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N20_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N20_LOGIC_ONE : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N15 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N20_CYINIT : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N10_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N10_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N5 : STD_LOGIC; 
  signal test2_top_addsub1_core_instance0_N10_LOGIC_ONE : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N12 : STD_LOGIC; 
  signal test2_top_s_x_0_2_XORF : STD_LOGIC; 
  signal test2_top_s_x_0_2_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_0_2_XORG : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N17 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N15 : STD_LOGIC; 
  signal test2_top_s_x_0_2_CYINIT : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N82 : STD_LOGIC; 
  signal test2_top_s_x_0_16_XORF : STD_LOGIC; 
  signal test2_top_s_x_0_16_CYINIT : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N2 : STD_LOGIC; 
  signal test2_top_s_x_0_0_XORF : STD_LOGIC; 
  signal test2_top_s_x_0_0_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_0_0_XORG : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N7 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N5 : STD_LOGIC; 
  signal test2_top_s_x_0_0_CYINIT : STD_LOGIC; 
  signal test2_top_s_x_0_0_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N72 : STD_LOGIC; 
  signal test2_top_s_x_0_14_XORF : STD_LOGIC; 
  signal test2_top_s_x_0_14_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_0_14_XORG : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N77 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N75 : STD_LOGIC; 
  signal test2_top_s_x_0_14_CYINIT : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N62 : STD_LOGIC; 
  signal test2_top_s_x_0_12_XORF : STD_LOGIC; 
  signal test2_top_s_x_0_12_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_0_12_XORG : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N67 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N65 : STD_LOGIC; 
  signal test2_top_s_x_0_12_CYINIT : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N52 : STD_LOGIC; 
  signal test2_top_s_x_0_10_XORF : STD_LOGIC; 
  signal test2_top_s_x_0_10_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_0_10_XORG : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N57 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N55 : STD_LOGIC; 
  signal test2_top_s_x_0_10_CYINIT : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N42 : STD_LOGIC; 
  signal test2_top_s_x_0_8_XORF : STD_LOGIC; 
  signal test2_top_s_x_0_8_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_0_8_XORG : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N47 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N45 : STD_LOGIC; 
  signal test2_top_s_x_0_8_CYINIT : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N32 : STD_LOGIC; 
  signal test2_top_s_x_0_6_XORF : STD_LOGIC; 
  signal test2_top_s_x_0_6_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_0_6_XORG : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N37 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N35 : STD_LOGIC; 
  signal test2_top_s_x_0_6_CYINIT : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N22 : STD_LOGIC; 
  signal test2_top_s_x_0_4_XORF : STD_LOGIC; 
  signal test2_top_s_x_0_4_CYMUXG : STD_LOGIC; 
  signal test2_top_s_x_0_4_XORG : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N27 : STD_LOGIC; 
  signal test2_top_addsub2_core_instance2_N25 : STD_LOGIC; 
  signal test2_top_s_x_0_4_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6169 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1173_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1173_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1173_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1173_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6174 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6172 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1173_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2092_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2092_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1978_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1978_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6159 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1175_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1175_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1175_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1175_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6164 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6162 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1175_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7748 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1225_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1225_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7753 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7751 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1225_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2094_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2094_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1980_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1980_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2349_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2349_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6149 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1177_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1177_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1177_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6154 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6152 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1177_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7738 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N245_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N245_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N245_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7743 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7741 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N245_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2097_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2097_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1982_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1982_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2351_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2351_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6139 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1179_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1179_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1179_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6144 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6142 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1179_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7728 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N247_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N247_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N247_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7733 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7731 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N247_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6832 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1206_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1206_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6837 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6835 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1206_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2099_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2099_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N256_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N256_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2467_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2467_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2353_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2353_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6129 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N253_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N253_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N253_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6134 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6132 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N253_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7718 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N249_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N249_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N249_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7723 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7721 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N249_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6822 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1208_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1208_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1208_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6827 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6825 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1208_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2100_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2100_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N258_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N258_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2470_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2470_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2356_FROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2356_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6119 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N255_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N255_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N255_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6124 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6122 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N255_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N255_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7708 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N251_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N251_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N251_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7713 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N7711 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N251_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N251_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6812 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1210_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1210_CYMUXG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1210_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6817 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N6815 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1210_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1210_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N8491 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N243_XORF : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N243_XORG : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N8496 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N8494 : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N243_CYINIT : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N243_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N1977_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2091_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2348_GROM : STD_LOGIC; 
  signal test2_top_kd_core_instance2_N2466_GROM : STD_LOGIC; 
  signal gateway_in1_0_IDELAY : STD_LOGIC; 
  signal gateway_in1_0_IBUF_0 : STD_LOGIC; 
  signal gateway_in1_1_IDELAY : STD_LOGIC; 
  signal gateway_in1_1_IBUF_1 : STD_LOGIC; 
  signal gateway_in1_2_IDELAY : STD_LOGIC; 
  signal gateway_in1_2_IBUF_2 : STD_LOGIC; 
  signal gateway_in1_3_IDELAY : STD_LOGIC; 
  signal gateway_in1_3_IBUF_3 : STD_LOGIC; 
  signal gateway_in1_4_IDELAY : STD_LOGIC; 
  signal gateway_in1_4_IBUF_4 : STD_LOGIC; 
  signal gateway_in1_5_IDELAY : STD_LOGIC; 
  signal gateway_in1_5_IBUF_5 : STD_LOGIC; 
  signal gateway_in1_6_IDELAY : STD_LOGIC; 
  signal gateway_in1_6_IBUF_6 : STD_LOGIC; 
  signal gateway_in1_7_IDELAY : STD_LOGIC; 
  signal gateway_in1_7_IBUF_7 : STD_LOGIC; 
  signal gateway_in1_8_IDELAY : STD_LOGIC; 
  signal gateway_in1_8_IBUF_8 : STD_LOGIC; 
  signal gateway_in1_9_IDELAY : STD_LOGIC; 
  signal gateway_in1_9_IBUF_9 : STD_LOGIC; 
  signal gateway_in1_10_IDELAY : STD_LOGIC; 
  signal gateway_in1_10_IBUF_10 : STD_LOGIC; 
  signal gateway_in1_11_IDELAY : STD_LOGIC; 
  signal gateway_in1_11_IBUF_11 : STD_LOGIC; 
  signal gateway_in1_12_IDELAY : STD_LOGIC; 
  signal gateway_in1_12_IBUF_12 : STD_LOGIC; 
  signal gateway_in1_13_IDELAY : STD_LOGIC; 
  signal gateway_in1_13_IBUF_13 : STD_LOGIC; 
  signal gateway_in1_14_IDELAY : STD_LOGIC; 
  signal gateway_in1_14_IBUF_14 : STD_LOGIC; 
  signal gateway_in1_15_IDELAY : STD_LOGIC; 
  signal gateway_in1_15_IBUF_15 : STD_LOGIC; 
  signal gateway_out_10_ENABLE : STD_LOGIC; 
  signal gateway_out_10_TORGTS : STD_LOGIC; 
  signal gateway_out_10_OUTMUX : STD_LOGIC; 
  signal gateway_out_11_ENABLE : STD_LOGIC; 
  signal gateway_out_11_TORGTS : STD_LOGIC; 
  signal gateway_out_11_OUTMUX : STD_LOGIC; 
  signal gateway_out_12_ENABLE : STD_LOGIC; 
  signal gateway_out_12_TORGTS : STD_LOGIC; 
  signal gateway_out_12_OUTMUX : STD_LOGIC; 
  signal gateway_out_13_ENABLE : STD_LOGIC; 
  signal gateway_out_13_TORGTS : STD_LOGIC; 
  signal gateway_out_13_OUTMUX : STD_LOGIC; 
  signal gateway_out_14_ENABLE : STD_LOGIC; 
  signal gateway_out_14_TORGTS : STD_LOGIC; 
  signal gateway_out_14_OUTMUX : STD_LOGIC; 
  signal gateway_out_15_ENABLE : STD_LOGIC; 
  signal gateway_out_15_TORGTS : STD_LOGIC; 
  signal gateway_out_15_OUTMUX : STD_LOGIC; 
  signal gateway_out_16_ENABLE : STD_LOGIC; 
  signal gateway_out_16_TORGTS : STD_LOGIC; 
  signal gateway_out_16_OUTMUX : STD_LOGIC; 
  signal gateway_out_0_ENABLE : STD_LOGIC; 
  signal gateway_out_0_TORGTS : STD_LOGIC; 
  signal gateway_out_0_OUTMUX : STD_LOGIC; 
  signal gateway_out_17_ENABLE : STD_LOGIC; 
  signal gateway_out_17_TORGTS : STD_LOGIC; 
  signal gateway_out_17_OUTMUX : STD_LOGIC; 
  signal gateway_out_1_ENABLE : STD_LOGIC; 
  signal gateway_out_1_TORGTS : STD_LOGIC; 
  signal gateway_out_1_OUTMUX : STD_LOGIC; 
  signal gateway_out_18_ENABLE : STD_LOGIC; 
  signal gateway_out_18_TORGTS : STD_LOGIC; 
  signal gateway_out_18_OUTMUX : STD_LOGIC; 
  signal gateway_out_2_ENABLE : STD_LOGIC; 
  signal gateway_out_2_TORGTS : STD_LOGIC; 
  signal gateway_out_2_OUTMUX : STD_LOGIC; 
  signal gateway_out_19_ENABLE : STD_LOGIC; 
  signal gateway_out_19_TORGTS : STD_LOGIC; 
  signal gateway_out_19_OUTMUX : STD_LOGIC; 
  signal gateway_out_3_ENABLE : STD_LOGIC; 
  signal gateway_out_3_TORGTS : STD_LOGIC; 
  signal gateway_out_3_OUTMUX : STD_LOGIC; 
  signal gateway_out_4_ENABLE : STD_LOGIC; 
  signal gateway_out_4_TORGTS : STD_LOGIC; 
  signal gateway_out_4_OUTMUX : STD_LOGIC; 
  signal gateway_out_5_ENABLE : STD_LOGIC; 
  signal gateway_out_5_TORGTS : STD_LOGIC; 
  signal gateway_out_5_OUTMUX : STD_LOGIC; 
  signal gateway_out_6_ENABLE : STD_LOGIC; 
  signal gateway_out_6_TORGTS : STD_LOGIC; 
  signal gateway_out_6_OUTMUX : STD_LOGIC; 
  signal gateway_out_7_ENABLE : STD_LOGIC; 
  signal gateway_out_7_TORGTS : STD_LOGIC; 
  signal gateway_out_7_OUTMUX : STD_LOGIC; 
  signal gateway_out_8_ENABLE : STD_LOGIC; 
  signal gateway_out_8_TORGTS : STD_LOGIC; 
  signal gateway_out_8_OUTMUX : STD_LOGIC; 
  signal gateway_out_9_ENABLE : STD_LOGIC; 
  signal gateway_out_9_TORGTS : STD_LOGIC; 
  signal gateway_out_9_OUTMUX : STD_LOGIC; 
  signal test2_top_q_x_0_1_FROM : STD_LOGIC; 
  signal test2_top_q_x_0_1_XORF : STD_LOGIC; 
  signal test2_top_q_x_0_1_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N12 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N10 : STD_LOGIC; 
  signal test2_top_q_x_0_1_CYINIT : STD_LOGIC; 
  signal test2_top_q_x_0_1_LOGIC_ZERO : STD_LOGIC; 
  signal test2_top_q_x_0_1_XORG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N17 : STD_LOGIC; 
  signal test2_top_q_x_0_3_XORF : STD_LOGIC; 
  signal test2_top_q_x_0_3_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N22 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N20 : STD_LOGIC; 
  signal test2_top_q_x_0_3_CYINIT : STD_LOGIC; 
  signal test2_top_q_x_0_3_XORG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N27 : STD_LOGIC; 
  signal test2_top_q_x_0_5_XORF : STD_LOGIC; 
  signal test2_top_q_x_0_5_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N32 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N30 : STD_LOGIC; 
  signal test2_top_q_x_0_5_CYINIT : STD_LOGIC; 
  signal test2_top_q_x_0_5_XORG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N37 : STD_LOGIC; 
  signal test2_top_q_x_0_7_XORF : STD_LOGIC; 
  signal test2_top_q_x_0_7_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N42 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N40 : STD_LOGIC; 
  signal test2_top_q_x_0_7_CYINIT : STD_LOGIC; 
  signal test2_top_q_x_0_7_XORG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N47 : STD_LOGIC; 
  signal test2_top_q_x_0_9_XORF : STD_LOGIC; 
  signal test2_top_q_x_0_9_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N52 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N50 : STD_LOGIC; 
  signal test2_top_q_x_0_9_CYINIT : STD_LOGIC; 
  signal test2_top_q_x_0_9_XORG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N57 : STD_LOGIC; 
  signal test2_top_q_x_0_11_XORF : STD_LOGIC; 
  signal test2_top_q_x_0_11_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N62 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N60 : STD_LOGIC; 
  signal test2_top_q_x_0_11_CYINIT : STD_LOGIC; 
  signal test2_top_q_x_0_11_XORG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N67 : STD_LOGIC; 
  signal test2_top_q_x_0_13_XORF : STD_LOGIC; 
  signal test2_top_q_x_0_13_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N72 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N70 : STD_LOGIC; 
  signal test2_top_q_x_0_13_CYINIT : STD_LOGIC; 
  signal test2_top_q_x_0_13_XORG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N77 : STD_LOGIC; 
  signal test2_top_q_x_0_15_XORF : STD_LOGIC; 
  signal test2_top_q_x_0_15_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N82 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N80 : STD_LOGIC; 
  signal test2_top_q_x_0_15_CYINIT : STD_LOGIC; 
  signal test2_top_q_x_0_15_XORG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N87 : STD_LOGIC; 
  signal test2_top_q_x_0_17_XORF : STD_LOGIC; 
  signal test2_top_q_x_0_17_CYMUXG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N92 : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N90 : STD_LOGIC; 
  signal test2_top_q_x_0_17_CYINIT : STD_LOGIC; 
  signal test2_top_q_x_0_17_XORG : STD_LOGIC; 
  signal test2_top_addsub6_core_instance10_N97 : STD_LOGIC; 
  signal test2_top_q_x_0_19_XORF : STD_LOGIC; 
  signal test2_top_q_x_0_19_CYINIT : STD_LOGIC; 
  signal test2_top_q_x_0_5_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_0_3_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_0_7_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_0_5_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_0_9_FFY_RST : STD_LOGIC; 
  signal gateway_in1_7_IFF_RST : STD_LOGIC; 
  signal gateway_in1_8_IFF_RST : STD_LOGIC; 
  signal gateway_in1_9_IFF_RST : STD_LOGIC; 
  signal gateway_in1_10_IFF_RST : STD_LOGIC; 
  signal gateway_in1_11_IFF_RST : STD_LOGIC; 
  signal gateway_in1_12_IFF_RST : STD_LOGIC; 
  signal gateway_in1_13_IFF_RST : STD_LOGIC; 
  signal gateway_in1_14_IFF_RST : STD_LOGIC; 
  signal test2_top_q_x_0_1_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_0_3_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_0_1_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_1_1_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_1_1_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_1_3_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_1_3_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_1_5_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_1_5_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_1_7_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_1_7_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_1_9_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_1_9_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_1_11_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_1_11_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_1_13_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_1_15_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_1_13_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_1_15_FFX_RST : STD_LOGIC; 
  signal gateway_in1_0_IFF_RST : STD_LOGIC; 
  signal gateway_in1_1_IFF_RST : STD_LOGIC; 
  signal gateway_in1_2_IFF_RST : STD_LOGIC; 
  signal gateway_in1_3_IFF_RST : STD_LOGIC; 
  signal gateway_in1_4_IFF_RST : STD_LOGIC; 
  signal gateway_in1_5_IFF_RST : STD_LOGIC; 
  signal gateway_in1_6_IFF_RST : STD_LOGIC; 
  signal test2_top_q_x_0_7_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_0_11_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_0_9_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_0_13_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_0_11_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_0_15_FFY_RST : STD_LOGIC; 
  signal gateway_in1_15_IFF_RST : STD_LOGIC; 
  signal test2_top_q_x_0_13_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_0_17_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_0_15_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_0_0_FFY_RST : STD_LOGIC; 
  signal test2_top_q_x_0_17_FFX_RST : STD_LOGIC; 
  signal test2_top_q_x_0_19_FFX_RST : STD_LOGIC; 
  signal clk_BUFGP_BUFG_CE : STD_LOGIC; 
  signal PWR_GND_0_GROM : STD_LOGIC; 
  signal PWR_GND_1_GROM : STD_LOGIC; 
  signal PWR_GND_2_GROM : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal NLW_test2_top_addsub1_core_instance0_BU28_IA_UNCONNECTED : STD_LOGIC; 
  signal NLW_test2_top_addsub1_core_instance0_BU32_IA_UNCONNECTED : STD_LOGIC; 
  signal NLW_test2_top_addsub1_core_instance0_BU20_IA_UNCONNECTED : STD_LOGIC; 
  signal NLW_test2_top_addsub1_core_instance0_BU24_IA_UNCONNECTED : STD_LOGIC; 
  signal NLW_test2_top_addsub1_core_instance0_BU12_IA_UNCONNECTED : STD_LOGIC; 
  signal NLW_test2_top_addsub1_core_instance0_BU16_IA_UNCONNECTED : STD_LOGIC; 
  signal NLW_test2_top_addsub1_core_instance0_BU8_IA_UNCONNECTED : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal test2_top_s_x_3 : STD_LOGIC_VECTOR ( 17 downto 0 ); 
  signal test2_top_s_x_0 : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal test2_top_s_x_2 : STD_LOGIC_VECTOR ( 17 downto 0 ); 
  signal test2_top_s_x_1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal test2_top_q : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal test2_top_q_x_1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal test2_top_s : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal test2_top_q_x_0 : STD_LOGIC_VECTOR ( 19 downto 0 ); 
begin
  test2_top_addsub5_core_instance8_BU84 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N253,
      IB => test2_top_s_x_3_6_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N102,
      O => test2_top_addsub5_core_instance8_N105
    );
  test2_top_addsub5_core_instance8_BU85 : X_XOR2
    port map (
      I0 => test2_top_s_x_3_6_CYINIT,
      I1 => test2_top_addsub5_core_instance8_N102,
      O => test2_top_s_x_3_6_XORF
    );
  test2_top_addsub5_core_instance8_BU83 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N253,
      ADR1 => VCC,
      ADR2 => gateway_in1_15_IBUF,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N102
    );
  test2_top_addsub5_core_instance8_BU87 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N252,
      ADR1 => VCC,
      ADR2 => gateway_in1_15_IBUF,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N107
    );
  test2_top_s_x_3_6_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_3_6_CYMUXG,
      O => test2_top_addsub5_core_instance8_N110
    );
  test2_top_s_x_3_6_XUSED : X_BUF
    port map (
      I => test2_top_s_x_3_6_XORF,
      O => test2_top_s_x_3(6)
    );
  test2_top_s_x_3_6_YUSED : X_BUF
    port map (
      I => test2_top_s_x_3_6_XORG,
      O => test2_top_s_x_3(7)
    );
  test2_top_addsub5_core_instance8_BU88 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N252,
      IB => test2_top_addsub5_core_instance8_N105,
      SEL => test2_top_addsub5_core_instance8_N107,
      O => test2_top_s_x_3_6_CYMUXG
    );
  test2_top_addsub5_core_instance8_BU89 : X_XOR2
    port map (
      I0 => test2_top_addsub5_core_instance8_N105,
      I1 => test2_top_addsub5_core_instance8_N107,
      O => test2_top_s_x_3_6_XORG
    );
  test2_top_s_x_3_6_CYINIT_16 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N100,
      O => test2_top_s_x_3_6_CYINIT
    );
  test2_top_addsub5_core_instance8_N30_LOGIC_ZERO_17 : X_ZERO
    port map (
      O => test2_top_addsub5_core_instance8_N30_LOGIC_ZERO
    );
  test2_top_addsub5_core_instance8_BU20 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N30_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N30_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N22,
      O => test2_top_addsub5_core_instance8_N25
    );
  test2_top_addsub5_core_instance8_BU19 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_3_IBUF,
      O => test2_top_addsub5_core_instance8_N22
    );
  test2_top_addsub5_core_instance8_BU23 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => gateway_in1_4_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N27
    );
  test2_top_addsub5_core_instance8_N30_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N30_CYMUXG,
      O => test2_top_addsub5_core_instance8_N30
    );
  test2_top_addsub5_core_instance8_BU24 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N30_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N25,
      SEL => test2_top_addsub5_core_instance8_N27,
      O => test2_top_addsub5_core_instance8_N30_CYMUXG
    );
  test2_top_addsub5_core_instance8_N30_CYINIT_18 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N20,
      O => test2_top_addsub5_core_instance8_N30_CYINIT
    );
  test2_top_addsub5_core_instance8_BU100 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N249,
      IB => test2_top_s_x_3_10_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N122,
      O => test2_top_addsub5_core_instance8_N125
    );
  test2_top_addsub5_core_instance8_BU101 : X_XOR2
    port map (
      I0 => test2_top_s_x_3_10_CYINIT,
      I1 => test2_top_addsub5_core_instance8_N122,
      O => test2_top_s_x_3_10_XORF
    );
  test2_top_addsub5_core_instance8_BU99 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N249,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_15_IBUF,
      O => test2_top_addsub5_core_instance8_N122
    );
  test2_top_addsub5_core_instance8_BU103 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N248,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_15_IBUF,
      O => test2_top_addsub5_core_instance8_N127
    );
  test2_top_s_x_3_10_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_3_10_CYMUXG,
      O => test2_top_addsub5_core_instance8_N130
    );
  test2_top_s_x_3_10_XUSED : X_BUF
    port map (
      I => test2_top_s_x_3_10_XORF,
      O => test2_top_s_x_3(10)
    );
  test2_top_s_x_3_10_YUSED : X_BUF
    port map (
      I => test2_top_s_x_3_10_XORG,
      O => test2_top_s_x_3(11)
    );
  test2_top_addsub5_core_instance8_BU104 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N248,
      IB => test2_top_addsub5_core_instance8_N125,
      SEL => test2_top_addsub5_core_instance8_N127,
      O => test2_top_s_x_3_10_CYMUXG
    );
  test2_top_addsub5_core_instance8_BU105 : X_XOR2
    port map (
      I0 => test2_top_addsub5_core_instance8_N125,
      I1 => test2_top_addsub5_core_instance8_N127,
      O => test2_top_s_x_3_10_XORG
    );
  test2_top_s_x_3_10_CYINIT_19 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N120,
      O => test2_top_s_x_3_10_CYINIT
    );
  test2_top_addsub5_core_instance8_BU76 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N255,
      IB => test2_top_s_x_3_4_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N92,
      O => test2_top_addsub5_core_instance8_N95
    );
  test2_top_addsub5_core_instance8_BU77 : X_XOR2
    port map (
      I0 => test2_top_s_x_3_4_CYINIT,
      I1 => test2_top_addsub5_core_instance8_N92,
      O => test2_top_s_x_3_4_XORF
    );
  test2_top_addsub5_core_instance8_BU75 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N255,
      ADR1 => gateway_in1_15_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N92
    );
  test2_top_addsub5_core_instance8_BU79 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N254,
      ADR1 => gateway_in1_15_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N97
    );
  test2_top_s_x_3_4_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_3_4_CYMUXG,
      O => test2_top_addsub5_core_instance8_N100
    );
  test2_top_s_x_3_4_XUSED : X_BUF
    port map (
      I => test2_top_s_x_3_4_XORF,
      O => test2_top_s_x_3(4)
    );
  test2_top_s_x_3_4_YUSED : X_BUF
    port map (
      I => test2_top_s_x_3_4_XORG,
      O => test2_top_s_x_3(5)
    );
  test2_top_addsub5_core_instance8_BU80 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N254,
      IB => test2_top_addsub5_core_instance8_N95,
      SEL => test2_top_addsub5_core_instance8_N97,
      O => test2_top_s_x_3_4_CYMUXG
    );
  test2_top_addsub5_core_instance8_BU81 : X_XOR2
    port map (
      I0 => test2_top_addsub5_core_instance8_N95,
      I1 => test2_top_addsub5_core_instance8_N97,
      O => test2_top_s_x_3_4_XORG
    );
  test2_top_s_x_3_4_CYINIT_20 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N90,
      O => test2_top_s_x_3_4_CYINIT
    );
  test2_top_addsub5_core_instance8_N20_LOGIC_ZERO_21 : X_ZERO
    port map (
      O => test2_top_addsub5_core_instance8_N20_LOGIC_ZERO
    );
  test2_top_addsub5_core_instance8_BU12 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N20_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N20_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N12,
      O => test2_top_addsub5_core_instance8_N15
    );
  test2_top_addsub5_core_instance8_BU11 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => gateway_in1_1_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N12
    );
  test2_top_addsub5_core_instance8_BU15 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => gateway_in1_2_IBUF,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N17
    );
  test2_top_addsub5_core_instance8_N20_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N20_CYMUXG,
      O => test2_top_addsub5_core_instance8_N20
    );
  test2_top_addsub5_core_instance8_BU16 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N20_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N15,
      SEL => test2_top_addsub5_core_instance8_N17,
      O => test2_top_addsub5_core_instance8_N20_CYMUXG
    );
  test2_top_addsub5_core_instance8_N20_CYINIT_22 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N10,
      O => test2_top_addsub5_core_instance8_N20_CYINIT
    );
  test2_top_addsub5_core_instance8_BU92 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N251,
      IB => test2_top_s_x_3_8_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N112,
      O => test2_top_addsub5_core_instance8_N115
    );
  test2_top_addsub5_core_instance8_BU93 : X_XOR2
    port map (
      I0 => test2_top_s_x_3_8_CYINIT,
      I1 => test2_top_addsub5_core_instance8_N112,
      O => test2_top_s_x_3_8_XORF
    );
  test2_top_addsub5_core_instance8_BU91 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N251,
      ADR1 => gateway_in1_15_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N112
    );
  test2_top_addsub5_core_instance8_BU95 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N250,
      ADR1 => gateway_in1_15_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N117
    );
  test2_top_s_x_3_8_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_3_8_CYMUXG,
      O => test2_top_addsub5_core_instance8_N120
    );
  test2_top_s_x_3_8_XUSED : X_BUF
    port map (
      I => test2_top_s_x_3_8_XORF,
      O => test2_top_s_x_3(8)
    );
  test2_top_s_x_3_8_YUSED : X_BUF
    port map (
      I => test2_top_s_x_3_8_XORG,
      O => test2_top_s_x_3(9)
    );
  test2_top_addsub5_core_instance8_BU96 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N250,
      IB => test2_top_addsub5_core_instance8_N115,
      SEL => test2_top_addsub5_core_instance8_N117,
      O => test2_top_s_x_3_8_CYMUXG
    );
  test2_top_addsub5_core_instance8_BU97 : X_XOR2
    port map (
      I0 => test2_top_addsub5_core_instance8_N115,
      I1 => test2_top_addsub5_core_instance8_N117,
      O => test2_top_s_x_3_8_XORG
    );
  test2_top_s_x_3_8_CYINIT_23 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N110,
      O => test2_top_s_x_3_8_CYINIT
    );
  test2_top_addsub5_core_instance8_N10_LOGIC_ZERO_24 : X_ZERO
    port map (
      O => test2_top_addsub5_core_instance8_N10_LOGIC_ZERO
    );
  test2_top_addsub5_core_instance8_BU4 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N10_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N10_LOGIC_ZERO,
      SEL => test2_top_addsub5_core_instance8_N10_FROM,
      O => test2_top_addsub5_core_instance8_N5
    );
  test2_top_addsub5_core_instance8_N10_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N10_FROM
    );
  test2_top_addsub5_core_instance8_BU7 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => gateway_in1_0_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N7
    );
  test2_top_addsub5_core_instance8_N10_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N10_CYMUXG,
      O => test2_top_addsub5_core_instance8_N10
    );
  test2_top_addsub5_core_instance8_BU8 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N10_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N5,
      SEL => test2_top_addsub5_core_instance8_N7,
      O => test2_top_addsub5_core_instance8_N10_CYMUXG
    );
  test2_top_addsub5_core_instance8_BU68 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N257,
      IB => test2_top_s_x_3_2_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N82,
      O => test2_top_addsub5_core_instance8_N85
    );
  test2_top_addsub5_core_instance8_BU69 : X_XOR2
    port map (
      I0 => test2_top_s_x_3_2_CYINIT,
      I1 => test2_top_addsub5_core_instance8_N82,
      O => test2_top_s_x_3_2_XORF
    );
  test2_top_addsub5_core_instance8_BU67 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N257,
      ADR1 => gateway_in1_15_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N82
    );
  test2_top_addsub5_core_instance8_BU71 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N256,
      ADR1 => gateway_in1_15_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N87
    );
  test2_top_s_x_3_2_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_3_2_CYMUXG,
      O => test2_top_addsub5_core_instance8_N90
    );
  test2_top_s_x_3_2_XUSED : X_BUF
    port map (
      I => test2_top_s_x_3_2_XORF,
      O => test2_top_s_x_3(2)
    );
  test2_top_s_x_3_2_YUSED : X_BUF
    port map (
      I => test2_top_s_x_3_2_XORG,
      O => test2_top_s_x_3(3)
    );
  test2_top_addsub5_core_instance8_BU72 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N256,
      IB => test2_top_addsub5_core_instance8_N85,
      SEL => test2_top_addsub5_core_instance8_N87,
      O => test2_top_s_x_3_2_CYMUXG
    );
  test2_top_addsub5_core_instance8_BU73 : X_XOR2
    port map (
      I0 => test2_top_addsub5_core_instance8_N85,
      I1 => test2_top_addsub5_core_instance8_N87,
      O => test2_top_s_x_3_2_XORG
    );
  test2_top_s_x_3_2_CYINIT_25 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N80,
      O => test2_top_s_x_3_2_CYINIT
    );
  test2_top_addsub5_core_instance8_BU60 : X_MUX2
    port map (
      IA => test2_top_s_x_0(0),
      IB => test2_top_s_x_3_0_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N72,
      O => test2_top_addsub5_core_instance8_N75
    );
  test2_top_addsub5_core_instance8_BU61 : X_XOR2
    port map (
      I0 => test2_top_s_x_3_0_CYINIT,
      I1 => test2_top_addsub5_core_instance8_N72,
      O => test2_top_s_x_3_0_XORF
    );
  test2_top_addsub5_core_instance8_BU59 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_0(0),
      ADR1 => VCC,
      ADR2 => gateway_in1_13_IBUF,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N72
    );
  test2_top_addsub5_core_instance8_BU63 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N258,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_14_IBUF,
      O => test2_top_addsub5_core_instance8_N77
    );
  test2_top_s_x_3_0_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_3_0_CYMUXG,
      O => test2_top_addsub5_core_instance8_N80
    );
  test2_top_s_x_3_0_XUSED : X_BUF
    port map (
      I => test2_top_s_x_3_0_XORF,
      O => test2_top_s_x_3(0)
    );
  test2_top_s_x_3_0_YUSED : X_BUF
    port map (
      I => test2_top_s_x_3_0_XORG,
      O => test2_top_s_x_3(1)
    );
  test2_top_addsub5_core_instance8_BU64 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N258,
      IB => test2_top_addsub5_core_instance8_N75,
      SEL => test2_top_addsub5_core_instance8_N77,
      O => test2_top_s_x_3_0_CYMUXG
    );
  test2_top_addsub5_core_instance8_BU65 : X_XOR2
    port map (
      I0 => test2_top_addsub5_core_instance8_N75,
      I1 => test2_top_addsub5_core_instance8_N77,
      O => test2_top_s_x_3_0_XORG
    );
  test2_top_s_x_3_0_CYINIT_26 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N70,
      O => test2_top_s_x_3_0_CYINIT
    );
  test2_top_addsub5_core_instance8_N70_LOGIC_ZERO_27 : X_ZERO
    port map (
      O => test2_top_addsub5_core_instance8_N70_LOGIC_ZERO
    );
  test2_top_addsub5_core_instance8_BU52 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N70_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N70_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N62,
      O => test2_top_addsub5_core_instance8_N65
    );
  test2_top_addsub5_core_instance8_BU51 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_11_IBUF,
      O => test2_top_addsub5_core_instance8_N62
    );
  test2_top_addsub5_core_instance8_BU55 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => gateway_in1_12_IBUF,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N67
    );
  test2_top_addsub5_core_instance8_N70_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N70_CYMUXG,
      O => test2_top_addsub5_core_instance8_N70
    );
  test2_top_addsub5_core_instance8_BU56 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N70_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N65,
      SEL => test2_top_addsub5_core_instance8_N67,
      O => test2_top_addsub5_core_instance8_N70_CYMUXG
    );
  test2_top_addsub5_core_instance8_N70_CYINIT_28 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N60,
      O => test2_top_addsub5_core_instance8_N70_CYINIT
    );
  test2_top_addsub5_core_instance8_N60_LOGIC_ZERO_29 : X_ZERO
    port map (
      O => test2_top_addsub5_core_instance8_N60_LOGIC_ZERO
    );
  test2_top_addsub5_core_instance8_BU44 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N60_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N60_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N52,
      O => test2_top_addsub5_core_instance8_N55
    );
  test2_top_addsub5_core_instance8_BU43 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => gateway_in1_9_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N52
    );
  test2_top_addsub5_core_instance8_BU47 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_10_IBUF,
      O => test2_top_addsub5_core_instance8_N57
    );
  test2_top_addsub5_core_instance8_N60_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N60_CYMUXG,
      O => test2_top_addsub5_core_instance8_N60
    );
  test2_top_addsub5_core_instance8_BU48 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N60_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N55,
      SEL => test2_top_addsub5_core_instance8_N57,
      O => test2_top_addsub5_core_instance8_N60_CYMUXG
    );
  test2_top_addsub5_core_instance8_N60_CYINIT_30 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N50,
      O => test2_top_addsub5_core_instance8_N60_CYINIT
    );
  test2_top_addsub5_core_instance8_BU124 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N243,
      IB => test2_top_s_x_3_16_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N152,
      O => test2_top_addsub5_core_instance8_N155
    );
  test2_top_addsub5_core_instance8_BU125 : X_XOR2
    port map (
      I0 => test2_top_s_x_3_16_CYINIT,
      I1 => test2_top_addsub5_core_instance8_N152,
      O => test2_top_s_x_3_16_XORF
    );
  test2_top_addsub5_core_instance8_BU123 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N243,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_15_IBUF,
      O => test2_top_addsub5_core_instance8_N152
    );
  test2_top_addsub5_core_instance8_BU127 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N242,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_15_IBUF,
      O => test2_top_addsub5_core_instance8_N157
    );
  test2_top_s_x_3_16_XUSED : X_BUF
    port map (
      I => test2_top_s_x_3_16_XORF,
      O => test2_top_s_x_3(16)
    );
  test2_top_s_x_3_16_YUSED : X_BUF
    port map (
      I => test2_top_s_x_3_16_XORG,
      O => test2_top_s_x_3(17)
    );
  test2_top_addsub5_core_instance8_BU129 : X_XOR2
    port map (
      I0 => test2_top_addsub5_core_instance8_N155,
      I1 => test2_top_addsub5_core_instance8_N157,
      O => test2_top_s_x_3_16_XORG
    );
  test2_top_s_x_3_16_CYINIT_31 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N150,
      O => test2_top_s_x_3_16_CYINIT
    );
  test2_top_addsub5_core_instance8_N50_LOGIC_ZERO_32 : X_ZERO
    port map (
      O => test2_top_addsub5_core_instance8_N50_LOGIC_ZERO
    );
  test2_top_addsub5_core_instance8_BU36 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N50_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N50_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N42,
      O => test2_top_addsub5_core_instance8_N45
    );
  test2_top_addsub5_core_instance8_BU35 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => gateway_in1_7_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N42
    );
  test2_top_addsub5_core_instance8_BU39 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_8_IBUF,
      O => test2_top_addsub5_core_instance8_N47
    );
  test2_top_addsub5_core_instance8_N50_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N50_CYMUXG,
      O => test2_top_addsub5_core_instance8_N50
    );
  test2_top_addsub5_core_instance8_BU40 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N50_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N45,
      SEL => test2_top_addsub5_core_instance8_N47,
      O => test2_top_addsub5_core_instance8_N50_CYMUXG
    );
  test2_top_addsub5_core_instance8_N50_CYINIT_33 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N40,
      O => test2_top_addsub5_core_instance8_N50_CYINIT
    );
  test2_top_addsub5_core_instance8_BU116 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N245,
      IB => test2_top_s_x_3_14_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N142,
      O => test2_top_addsub5_core_instance8_N145
    );
  test2_top_addsub5_core_instance8_BU117 : X_XOR2
    port map (
      I0 => test2_top_s_x_3_14_CYINIT,
      I1 => test2_top_addsub5_core_instance8_N142,
      O => test2_top_s_x_3_14_XORF
    );
  test2_top_addsub5_core_instance8_BU115 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N245,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_15_IBUF,
      O => test2_top_addsub5_core_instance8_N142
    );
  test2_top_addsub5_core_instance8_BU119 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N244,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_15_IBUF,
      O => test2_top_addsub5_core_instance8_N147
    );
  test2_top_s_x_3_14_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_3_14_CYMUXG,
      O => test2_top_addsub5_core_instance8_N150
    );
  test2_top_s_x_3_14_XUSED : X_BUF
    port map (
      I => test2_top_s_x_3_14_XORF,
      O => test2_top_s_x_3(14)
    );
  test2_top_s_x_3_14_YUSED : X_BUF
    port map (
      I => test2_top_s_x_3_14_XORG,
      O => test2_top_s_x_3(15)
    );
  test2_top_addsub5_core_instance8_BU120 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N244,
      IB => test2_top_addsub5_core_instance8_N145,
      SEL => test2_top_addsub5_core_instance8_N147,
      O => test2_top_s_x_3_14_CYMUXG
    );
  test2_top_addsub5_core_instance8_BU121 : X_XOR2
    port map (
      I0 => test2_top_addsub5_core_instance8_N145,
      I1 => test2_top_addsub5_core_instance8_N147,
      O => test2_top_s_x_3_14_XORG
    );
  test2_top_s_x_3_14_CYINIT_34 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N140,
      O => test2_top_s_x_3_14_CYINIT
    );
  test2_top_addsub5_core_instance8_N40_LOGIC_ZERO_35 : X_ZERO
    port map (
      O => test2_top_addsub5_core_instance8_N40_LOGIC_ZERO
    );
  test2_top_addsub5_core_instance8_BU28 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N40_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N40_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N32,
      O => test2_top_addsub5_core_instance8_N35
    );
  test2_top_addsub5_core_instance8_BU27 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => gateway_in1_5_IBUF,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N32
    );
  test2_top_addsub5_core_instance8_BU31 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_6_IBUF,
      O => test2_top_addsub5_core_instance8_N37
    );
  test2_top_addsub5_core_instance8_N40_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N40_CYMUXG,
      O => test2_top_addsub5_core_instance8_N40
    );
  test2_top_addsub5_core_instance8_BU32 : X_MUX2
    port map (
      IA => test2_top_addsub5_core_instance8_N40_LOGIC_ZERO,
      IB => test2_top_addsub5_core_instance8_N35,
      SEL => test2_top_addsub5_core_instance8_N37,
      O => test2_top_addsub5_core_instance8_N40_CYMUXG
    );
  test2_top_addsub5_core_instance8_N40_CYINIT_36 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N30,
      O => test2_top_addsub5_core_instance8_N40_CYINIT
    );
  test2_top_addsub5_core_instance8_BU108 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N247,
      IB => test2_top_s_x_3_12_CYINIT,
      SEL => test2_top_addsub5_core_instance8_N132,
      O => test2_top_addsub5_core_instance8_N135
    );
  test2_top_addsub5_core_instance8_BU109 : X_XOR2
    port map (
      I0 => test2_top_s_x_3_12_CYINIT,
      I1 => test2_top_addsub5_core_instance8_N132,
      O => test2_top_s_x_3_12_XORF
    );
  test2_top_addsub5_core_instance8_BU107 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N247,
      ADR1 => gateway_in1_15_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N132
    );
  test2_top_addsub5_core_instance8_BU111 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N246,
      ADR1 => gateway_in1_15_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub5_core_instance8_N137
    );
  test2_top_s_x_3_12_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_3_12_CYMUXG,
      O => test2_top_addsub5_core_instance8_N140
    );
  test2_top_s_x_3_12_XUSED : X_BUF
    port map (
      I => test2_top_s_x_3_12_XORF,
      O => test2_top_s_x_3(12)
    );
  test2_top_s_x_3_12_YUSED : X_BUF
    port map (
      I => test2_top_s_x_3_12_XORG,
      O => test2_top_s_x_3(13)
    );
  test2_top_addsub5_core_instance8_BU112 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N246,
      IB => test2_top_addsub5_core_instance8_N135,
      SEL => test2_top_addsub5_core_instance8_N137,
      O => test2_top_s_x_3_12_CYMUXG
    );
  test2_top_addsub5_core_instance8_BU113 : X_XOR2
    port map (
      I0 => test2_top_addsub5_core_instance8_N135,
      I1 => test2_top_addsub5_core_instance8_N137,
      O => test2_top_s_x_3_12_XORG
    );
  test2_top_s_x_3_12_CYINIT_37 : X_BUF
    port map (
      I => test2_top_addsub5_core_instance8_N130,
      O => test2_top_s_x_3_12_CYINIT
    );
  test2_top_addsub4_core_instance6_BU36 : X_MUX2
    port map (
      IA => test2_top_s_x_3(1),
      IB => test2_top_s_x_2_1_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N42,
      O => test2_top_addsub4_core_instance6_N45
    );
  test2_top_addsub4_core_instance6_BU37 : X_XOR2
    port map (
      I0 => test2_top_s_x_2_1_CYINIT,
      I1 => test2_top_addsub4_core_instance6_N42,
      O => test2_top_s_x_2_1_XORF
    );
  test2_top_addsub4_core_instance6_BU35 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_3(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N230,
      O => test2_top_addsub4_core_instance6_N42
    );
  test2_top_addsub4_core_instance6_BU39 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_3(2),
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N229,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N47
    );
  test2_top_s_x_2_1_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_2_1_CYMUXG,
      O => test2_top_addsub4_core_instance6_N50
    );
  test2_top_s_x_2_1_XUSED : X_BUF
    port map (
      I => test2_top_s_x_2_1_XORF,
      O => test2_top_s_x_2(1)
    );
  test2_top_s_x_2_1_YUSED : X_BUF
    port map (
      I => test2_top_s_x_2_1_XORG,
      O => test2_top_s_x_2(2)
    );
  test2_top_addsub4_core_instance6_BU40 : X_MUX2
    port map (
      IA => test2_top_s_x_3(2),
      IB => test2_top_addsub4_core_instance6_N45,
      SEL => test2_top_addsub4_core_instance6_N47,
      O => test2_top_s_x_2_1_CYMUXG
    );
  test2_top_addsub4_core_instance6_BU41 : X_XOR2
    port map (
      I0 => test2_top_addsub4_core_instance6_N45,
      I1 => test2_top_addsub4_core_instance6_N47,
      O => test2_top_s_x_2_1_XORG
    );
  test2_top_s_x_2_1_CYINIT_38 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N40,
      O => test2_top_s_x_2_1_CYINIT
    );
  test2_top_addsub4_core_instance6_BU92 : X_MUX2
    port map (
      IA => test2_top_s_x_3(15),
      IB => test2_top_s_x_2_15_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N112,
      O => test2_top_addsub4_core_instance6_N115
    );
  test2_top_addsub4_core_instance6_BU93 : X_XOR2
    port map (
      I0 => test2_top_s_x_2_15_CYINIT,
      I1 => test2_top_addsub4_core_instance6_N112,
      O => test2_top_s_x_2_15_XORF
    );
  test2_top_addsub4_core_instance6_BU91 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_3(15),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N216,
      O => test2_top_addsub4_core_instance6_N112
    );
  test2_top_addsub4_core_instance6_BU95 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_3(16),
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N215,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N117
    );
  test2_top_s_x_2_15_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_2_15_CYMUXG,
      O => test2_top_addsub4_core_instance6_N120
    );
  test2_top_s_x_2_15_XUSED : X_BUF
    port map (
      I => test2_top_s_x_2_15_XORF,
      O => test2_top_s_x_2(15)
    );
  test2_top_s_x_2_15_YUSED : X_BUF
    port map (
      I => test2_top_s_x_2_15_XORG,
      O => test2_top_s_x_2(16)
    );
  test2_top_addsub4_core_instance6_BU96 : X_MUX2
    port map (
      IA => test2_top_s_x_3(16),
      IB => test2_top_addsub4_core_instance6_N115,
      SEL => test2_top_addsub4_core_instance6_N117,
      O => test2_top_s_x_2_15_CYMUXG
    );
  test2_top_addsub4_core_instance6_BU97 : X_XOR2
    port map (
      I0 => test2_top_addsub4_core_instance6_N115,
      I1 => test2_top_addsub4_core_instance6_N117,
      O => test2_top_s_x_2_15_XORG
    );
  test2_top_s_x_2_15_CYINIT_39 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N110,
      O => test2_top_s_x_2_15_CYINIT
    );
  test2_top_addsub4_core_instance6_BU28 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_0,
      IB => test2_top_s_x_2_0_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N32,
      O => test2_top_addsub4_core_instance6_N35
    );
  test2_top_addsub4_core_instance6_BU27 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_0,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N232,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N32
    );
  test2_top_addsub4_core_instance6_BU31 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_3(0),
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N231,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N37
    );
  test2_top_s_x_2_0_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_2_0_CYMUXG,
      O => test2_top_addsub4_core_instance6_N40
    );
  test2_top_s_x_2_0_YUSED : X_BUF
    port map (
      I => test2_top_s_x_2_0_XORG,
      O => test2_top_s_x_2(0)
    );
  test2_top_addsub4_core_instance6_BU32 : X_MUX2
    port map (
      IA => test2_top_s_x_3(0),
      IB => test2_top_addsub4_core_instance6_N35,
      SEL => test2_top_addsub4_core_instance6_N37,
      O => test2_top_s_x_2_0_CYMUXG
    );
  test2_top_addsub4_core_instance6_BU33 : X_XOR2
    port map (
      I0 => test2_top_addsub4_core_instance6_N35,
      I1 => test2_top_addsub4_core_instance6_N37,
      O => test2_top_s_x_2_0_XORG
    );
  test2_top_s_x_2_0_CYINIT_40 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N30,
      O => test2_top_s_x_2_0_CYINIT
    );
  test2_top_addsub4_core_instance6_BU84 : X_MUX2
    port map (
      IA => test2_top_s_x_3(13),
      IB => test2_top_s_x_2_13_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N102,
      O => test2_top_addsub4_core_instance6_N105
    );
  test2_top_addsub4_core_instance6_BU85 : X_XOR2
    port map (
      I0 => test2_top_s_x_2_13_CYINIT,
      I1 => test2_top_addsub4_core_instance6_N102,
      O => test2_top_s_x_2_13_XORF
    );
  test2_top_addsub4_core_instance6_BU83 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_3(13),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N218,
      O => test2_top_addsub4_core_instance6_N102
    );
  test2_top_addsub4_core_instance6_BU87 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_3(14),
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N217,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N107
    );
  test2_top_s_x_2_13_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_2_13_CYMUXG,
      O => test2_top_addsub4_core_instance6_N110
    );
  test2_top_s_x_2_13_XUSED : X_BUF
    port map (
      I => test2_top_s_x_2_13_XORF,
      O => test2_top_s_x_2(13)
    );
  test2_top_s_x_2_13_YUSED : X_BUF
    port map (
      I => test2_top_s_x_2_13_XORG,
      O => test2_top_s_x_2(14)
    );
  test2_top_addsub4_core_instance6_BU88 : X_MUX2
    port map (
      IA => test2_top_s_x_3(14),
      IB => test2_top_addsub4_core_instance6_N105,
      SEL => test2_top_addsub4_core_instance6_N107,
      O => test2_top_s_x_2_13_CYMUXG
    );
  test2_top_addsub4_core_instance6_BU89 : X_XOR2
    port map (
      I0 => test2_top_addsub4_core_instance6_N105,
      I1 => test2_top_addsub4_core_instance6_N107,
      O => test2_top_s_x_2_13_XORG
    );
  test2_top_s_x_2_13_CYINIT_41 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N100,
      O => test2_top_s_x_2_13_CYINIT
    );
  test2_top_addsub4_core_instance6_N30_LOGIC_ZERO_42 : X_ZERO
    port map (
      O => test2_top_addsub4_core_instance6_N30_LOGIC_ZERO
    );
  test2_top_addsub4_core_instance6_BU20 : X_MUX2
    port map (
      IA => test2_top_addsub4_core_instance6_N30_LOGIC_ZERO,
      IB => test2_top_addsub4_core_instance6_N30_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N22,
      O => test2_top_addsub4_core_instance6_N25
    );
  test2_top_addsub4_core_instance6_BU19 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N234,
      O => test2_top_addsub4_core_instance6_N22
    );
  test2_top_addsub4_core_instance6_BU23 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N233,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N27
    );
  test2_top_addsub4_core_instance6_N30_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N30_CYMUXG,
      O => test2_top_addsub4_core_instance6_N30
    );
  test2_top_addsub4_core_instance6_BU24 : X_MUX2
    port map (
      IA => test2_top_addsub4_core_instance6_N30_LOGIC_ZERO,
      IB => test2_top_addsub4_core_instance6_N25,
      SEL => test2_top_addsub4_core_instance6_N27,
      O => test2_top_addsub4_core_instance6_N30_CYMUXG
    );
  test2_top_addsub4_core_instance6_N30_CYINIT_43 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N20,
      O => test2_top_addsub4_core_instance6_N30_CYINIT
    );
  test2_top_addsub4_core_instance6_BU76 : X_MUX2
    port map (
      IA => test2_top_s_x_3(11),
      IB => test2_top_s_x_2_11_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N92,
      O => test2_top_addsub4_core_instance6_N95
    );
  test2_top_addsub4_core_instance6_BU77 : X_XOR2
    port map (
      I0 => test2_top_s_x_2_11_CYINIT,
      I1 => test2_top_addsub4_core_instance6_N92,
      O => test2_top_s_x_2_11_XORF
    );
  test2_top_addsub4_core_instance6_BU75 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_3(11),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N220,
      O => test2_top_addsub4_core_instance6_N92
    );
  test2_top_addsub4_core_instance6_BU79 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_3(12),
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N219,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N97
    );
  test2_top_s_x_2_11_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_2_11_CYMUXG,
      O => test2_top_addsub4_core_instance6_N100
    );
  test2_top_s_x_2_11_XUSED : X_BUF
    port map (
      I => test2_top_s_x_2_11_XORF,
      O => test2_top_s_x_2(11)
    );
  test2_top_s_x_2_11_YUSED : X_BUF
    port map (
      I => test2_top_s_x_2_11_XORG,
      O => test2_top_s_x_2(12)
    );
  test2_top_addsub4_core_instance6_BU80 : X_MUX2
    port map (
      IA => test2_top_s_x_3(12),
      IB => test2_top_addsub4_core_instance6_N95,
      SEL => test2_top_addsub4_core_instance6_N97,
      O => test2_top_s_x_2_11_CYMUXG
    );
  test2_top_addsub4_core_instance6_BU81 : X_XOR2
    port map (
      I0 => test2_top_addsub4_core_instance6_N95,
      I1 => test2_top_addsub4_core_instance6_N97,
      O => test2_top_s_x_2_11_XORG
    );
  test2_top_s_x_2_11_CYINIT_44 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N90,
      O => test2_top_s_x_2_11_CYINIT
    );
  test2_top_addsub4_core_instance6_N20_LOGIC_ZERO_45 : X_ZERO
    port map (
      O => test2_top_addsub4_core_instance6_N20_LOGIC_ZERO
    );
  test2_top_addsub4_core_instance6_BU12 : X_MUX2
    port map (
      IA => test2_top_addsub4_core_instance6_N20_LOGIC_ZERO,
      IB => test2_top_addsub4_core_instance6_N20_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N12,
      O => test2_top_addsub4_core_instance6_N15
    );
  test2_top_addsub4_core_instance6_BU11 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N236,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N12
    );
  test2_top_addsub4_core_instance6_BU15 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N235,
      O => test2_top_addsub4_core_instance6_N17
    );
  test2_top_addsub4_core_instance6_N20_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N20_CYMUXG,
      O => test2_top_addsub4_core_instance6_N20
    );
  test2_top_addsub4_core_instance6_BU16 : X_MUX2
    port map (
      IA => test2_top_addsub4_core_instance6_N20_LOGIC_ZERO,
      IB => test2_top_addsub4_core_instance6_N15,
      SEL => test2_top_addsub4_core_instance6_N17,
      O => test2_top_addsub4_core_instance6_N20_CYMUXG
    );
  test2_top_addsub4_core_instance6_N20_CYINIT_46 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N10,
      O => test2_top_addsub4_core_instance6_N20_CYINIT
    );
  test2_top_addsub4_core_instance6_BU68 : X_MUX2
    port map (
      IA => test2_top_s_x_3(9),
      IB => test2_top_s_x_2_9_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N82,
      O => test2_top_addsub4_core_instance6_N85
    );
  test2_top_addsub4_core_instance6_BU69 : X_XOR2
    port map (
      I0 => test2_top_s_x_2_9_CYINIT,
      I1 => test2_top_addsub4_core_instance6_N82,
      O => test2_top_s_x_2_9_XORF
    );
  test2_top_addsub4_core_instance6_BU67 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_3(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N222,
      O => test2_top_addsub4_core_instance6_N82
    );
  test2_top_addsub4_core_instance6_BU71 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_3(10),
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N221,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N87
    );
  test2_top_s_x_2_9_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_2_9_CYMUXG,
      O => test2_top_addsub4_core_instance6_N90
    );
  test2_top_s_x_2_9_XUSED : X_BUF
    port map (
      I => test2_top_s_x_2_9_XORF,
      O => test2_top_s_x_2(9)
    );
  test2_top_s_x_2_9_YUSED : X_BUF
    port map (
      I => test2_top_s_x_2_9_XORG,
      O => test2_top_s_x_2(10)
    );
  test2_top_addsub4_core_instance6_BU72 : X_MUX2
    port map (
      IA => test2_top_s_x_3(10),
      IB => test2_top_addsub4_core_instance6_N85,
      SEL => test2_top_addsub4_core_instance6_N87,
      O => test2_top_s_x_2_9_CYMUXG
    );
  test2_top_addsub4_core_instance6_BU73 : X_XOR2
    port map (
      I0 => test2_top_addsub4_core_instance6_N85,
      I1 => test2_top_addsub4_core_instance6_N87,
      O => test2_top_s_x_2_9_XORG
    );
  test2_top_s_x_2_9_CYINIT_47 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N80,
      O => test2_top_s_x_2_9_CYINIT
    );
  test2_top_addsub4_core_instance6_N10_LOGIC_ZERO_48 : X_ZERO
    port map (
      O => test2_top_addsub4_core_instance6_N10_LOGIC_ZERO
    );
  test2_top_addsub4_core_instance6_BU4 : X_MUX2
    port map (
      IA => test2_top_addsub4_core_instance6_N10_LOGIC_ZERO,
      IB => test2_top_addsub4_core_instance6_N10_LOGIC_ZERO,
      SEL => test2_top_addsub4_core_instance6_N2,
      O => test2_top_addsub4_core_instance6_N5
    );
  test2_top_addsub4_core_instance6_BU3 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_s_x_1(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N2
    );
  test2_top_addsub4_core_instance6_BU7 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_kp_core_instance6_N237,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N7
    );
  test2_top_addsub4_core_instance6_N10_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N10_CYMUXG,
      O => test2_top_addsub4_core_instance6_N10
    );
  test2_top_addsub4_core_instance6_BU8 : X_MUX2
    port map (
      IA => test2_top_addsub4_core_instance6_N10_LOGIC_ZERO,
      IB => test2_top_addsub4_core_instance6_N5,
      SEL => test2_top_addsub4_core_instance6_N7,
      O => test2_top_addsub4_core_instance6_N10_CYMUXG
    );
  test2_top_addsub4_core_instance6_BU60 : X_MUX2
    port map (
      IA => test2_top_s_x_3(7),
      IB => test2_top_s_x_2_7_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N72,
      O => test2_top_addsub4_core_instance6_N75
    );
  test2_top_addsub4_core_instance6_BU61 : X_XOR2
    port map (
      I0 => test2_top_s_x_2_7_CYINIT,
      I1 => test2_top_addsub4_core_instance6_N72,
      O => test2_top_s_x_2_7_XORF
    );
  test2_top_addsub4_core_instance6_BU59 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_3(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N224,
      O => test2_top_addsub4_core_instance6_N72
    );
  test2_top_addsub4_core_instance6_BU63 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_3(8),
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N223,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N77
    );
  test2_top_s_x_2_7_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_2_7_CYMUXG,
      O => test2_top_addsub4_core_instance6_N80
    );
  test2_top_s_x_2_7_XUSED : X_BUF
    port map (
      I => test2_top_s_x_2_7_XORF,
      O => test2_top_s_x_2(7)
    );
  test2_top_s_x_2_7_YUSED : X_BUF
    port map (
      I => test2_top_s_x_2_7_XORG,
      O => test2_top_s_x_2(8)
    );
  test2_top_addsub4_core_instance6_BU64 : X_MUX2
    port map (
      IA => test2_top_s_x_3(8),
      IB => test2_top_addsub4_core_instance6_N75,
      SEL => test2_top_addsub4_core_instance6_N77,
      O => test2_top_s_x_2_7_CYMUXG
    );
  test2_top_addsub4_core_instance6_BU65 : X_XOR2
    port map (
      I0 => test2_top_addsub4_core_instance6_N75,
      I1 => test2_top_addsub4_core_instance6_N77,
      O => test2_top_s_x_2_7_XORG
    );
  test2_top_s_x_2_7_CYINIT_49 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N70,
      O => test2_top_s_x_2_7_CYINIT
    );
  test2_top_addsub4_core_instance6_BU52 : X_MUX2
    port map (
      IA => test2_top_s_x_3(5),
      IB => test2_top_s_x_2_5_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N62,
      O => test2_top_addsub4_core_instance6_N65
    );
  test2_top_addsub4_core_instance6_BU53 : X_XOR2
    port map (
      I0 => test2_top_s_x_2_5_CYINIT,
      I1 => test2_top_addsub4_core_instance6_N62,
      O => test2_top_s_x_2_5_XORF
    );
  test2_top_addsub4_core_instance6_BU51 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_3(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N226,
      O => test2_top_addsub4_core_instance6_N62
    );
  test2_top_addsub4_core_instance6_BU55 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_3(6),
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N225,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N67
    );
  test2_top_s_x_2_5_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_2_5_CYMUXG,
      O => test2_top_addsub4_core_instance6_N70
    );
  test2_top_s_x_2_5_XUSED : X_BUF
    port map (
      I => test2_top_s_x_2_5_XORF,
      O => test2_top_s_x_2(5)
    );
  test2_top_s_x_2_5_YUSED : X_BUF
    port map (
      I => test2_top_s_x_2_5_XORG,
      O => test2_top_s_x_2(6)
    );
  test2_top_addsub4_core_instance6_BU56 : X_MUX2
    port map (
      IA => test2_top_s_x_3(6),
      IB => test2_top_addsub4_core_instance6_N65,
      SEL => test2_top_addsub4_core_instance6_N67,
      O => test2_top_s_x_2_5_CYMUXG
    );
  test2_top_addsub4_core_instance6_BU57 : X_XOR2
    port map (
      I0 => test2_top_addsub4_core_instance6_N65,
      I1 => test2_top_addsub4_core_instance6_N67,
      O => test2_top_s_x_2_5_XORG
    );
  test2_top_s_x_2_5_CYINIT_50 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N60,
      O => test2_top_s_x_2_5_CYINIT
    );
  test2_top_addsub4_core_instance6_BU44 : X_MUX2
    port map (
      IA => test2_top_s_x_3(3),
      IB => test2_top_s_x_2_3_CYINIT,
      SEL => test2_top_addsub4_core_instance6_N52,
      O => test2_top_addsub4_core_instance6_N55
    );
  test2_top_addsub4_core_instance6_BU45 : X_XOR2
    port map (
      I0 => test2_top_s_x_2_3_CYINIT,
      I1 => test2_top_addsub4_core_instance6_N52,
      O => test2_top_s_x_2_3_XORF
    );
  test2_top_addsub4_core_instance6_BU43 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_3(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N228,
      O => test2_top_addsub4_core_instance6_N52
    );
  test2_top_addsub4_core_instance6_BU47 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_3(4),
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N227,
      ADR3 => VCC,
      O => test2_top_addsub4_core_instance6_N57
    );
  test2_top_s_x_2_3_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_2_3_CYMUXG,
      O => test2_top_addsub4_core_instance6_N60
    );
  test2_top_s_x_2_3_XUSED : X_BUF
    port map (
      I => test2_top_s_x_2_3_XORF,
      O => test2_top_s_x_2(3)
    );
  test2_top_s_x_2_3_YUSED : X_BUF
    port map (
      I => test2_top_s_x_2_3_XORG,
      O => test2_top_s_x_2(4)
    );
  test2_top_addsub4_core_instance6_BU48 : X_MUX2
    port map (
      IA => test2_top_s_x_3(4),
      IB => test2_top_addsub4_core_instance6_N55,
      SEL => test2_top_addsub4_core_instance6_N57,
      O => test2_top_s_x_2_3_CYMUXG
    );
  test2_top_addsub4_core_instance6_BU49 : X_XOR2
    port map (
      I0 => test2_top_addsub4_core_instance6_N55,
      I1 => test2_top_addsub4_core_instance6_N57,
      O => test2_top_s_x_2_3_XORG
    );
  test2_top_s_x_2_3_CYINIT_51 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N50,
      O => test2_top_s_x_2_3_CYINIT
    );
  test2_top_addsub4_core_instance6_BU101 : X_XOR2
    port map (
      I0 => test2_top_s_x_2_17_CYINIT,
      I1 => test2_top_addsub4_core_instance6_N122,
      O => test2_top_s_x_2_17_XORF
    );
  test2_top_addsub4_core_instance6_BU99 : X_LUT4
    generic map(
      INIT => X"0FF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N214,
      ADR3 => test2_top_s_x_3(17),
      O => test2_top_addsub4_core_instance6_N122
    );
  test2_top_s_x_2_17_XUSED : X_BUF
    port map (
      I => test2_top_s_x_2_17_XORF,
      O => test2_top_s_x_2(17)
    );
  test2_top_s_x_2_17_CYINIT_52 : X_BUF
    port map (
      I => test2_top_addsub4_core_instance6_N120,
      O => test2_top_s_x_2_17_CYINIT
    );
  test2_top_kp_core_instance6_BU440 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N923,
      IB => test2_top_kp_core_instance6_N228_CYINIT,
      SEL => test2_top_kp_core_instance6_N7213,
      O => test2_top_kp_core_instance6_N7216
    );
  test2_top_kp_core_instance6_BU441 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N228_CYINIT,
      I1 => test2_top_kp_core_instance6_N7213,
      O => test2_top_kp_core_instance6_N228_XORF
    );
  test2_top_kp_core_instance6_BU439 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N923,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N1991,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7213
    );
  test2_top_kp_core_instance6_BU443 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N922,
      ADR1 => test2_top_kp_core_instance6_N1990,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7218
    );
  test2_top_kp_core_instance6_N228_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N228_CYMUXG,
      O => test2_top_kp_core_instance6_N7221
    );
  test2_top_kp_core_instance6_N228_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N228_XORF,
      O => test2_top_kp_core_instance6_N228
    );
  test2_top_kp_core_instance6_N228_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N228_XORG,
      O => test2_top_kp_core_instance6_N227
    );
  test2_top_kp_core_instance6_BU444 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N922,
      IB => test2_top_kp_core_instance6_N7216,
      SEL => test2_top_kp_core_instance6_N7218,
      O => test2_top_kp_core_instance6_N228_CYMUXG
    );
  test2_top_kp_core_instance6_BU445 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N7216,
      I1 => test2_top_kp_core_instance6_N7218,
      O => test2_top_kp_core_instance6_N228_XORG
    );
  test2_top_kp_core_instance6_N228_CYINIT_53 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N7211,
      O => test2_top_kp_core_instance6_N228_CYINIT
    );
  test2_top_kp_core_instance6_BU109 : X_LUT4
    generic map(
      INIT => X"3636"
    )
    port map (
      ADR0 => test2_top_s_x_1(4),
      ADR1 => test2_top_s_x_1(6),
      ADR2 => test2_top_s_x_1(5),
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N1700_FROM
    );
  test2_top_kp_core_instance6_BU105 : X_LUT4
    generic map(
      INIT => X"33CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_s_x_1(4),
      ADR2 => VCC,
      ADR3 => test2_top_s_x_1(5),
      O => test2_top_kp_core_instance6_N1700_GROM
    );
  test2_top_kp_core_instance6_N1700_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1700_FROM,
      O => test2_top_kp_core_instance6_N1700
    );
  test2_top_kp_core_instance6_N1700_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1700_GROM,
      O => test2_top_kp_core_instance6_N1701
    );
  test2_top_kp_core_instance6_BU36 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_1(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_s_x_1(1),
      O => test2_top_kp_core_instance6_N237_FROM
    );
  test2_top_kp_core_instance6_BU40 : X_LUT4
    generic map(
      INIT => X"0F5A"
    )
    port map (
      ADR0 => test2_top_s_x_1(0),
      ADR1 => VCC,
      ADR2 => test2_top_s_x_1(2),
      ADR3 => test2_top_s_x_1(1),
      O => test2_top_kp_core_instance6_N237_GROM
    );
  test2_top_kp_core_instance6_N237_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N237_FROM,
      O => test2_top_kp_core_instance6_N237
    );
  test2_top_kp_core_instance6_N237_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N237_GROM,
      O => test2_top_kp_core_instance6_N236
    );
  test2_top_kp_core_instance6_BU306 : X_LUT4
    generic map(
      INIT => X"0FF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => test2_top_s_x_1(12),
      ADR3 => test2_top_s_x_1(13),
      O => test2_top_kp_core_instance6_N2122_FROM
    );
  test2_top_kp_core_instance6_BU310 : X_LUT4
    generic map(
      INIT => X"5566"
    )
    port map (
      ADR0 => test2_top_s_x_1(14),
      ADR1 => test2_top_s_x_1(12),
      ADR2 => VCC,
      ADR3 => test2_top_s_x_1(13),
      O => test2_top_kp_core_instance6_N2122_GROM
    );
  test2_top_kp_core_instance6_N2122_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2122_FROM,
      O => test2_top_kp_core_instance6_N2122
    );
  test2_top_kp_core_instance6_N2122_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2122_GROM,
      O => test2_top_kp_core_instance6_N2121
    );
  test2_top_kp_core_instance6_BU237 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s_x_1(8),
      ADR1 => test2_top_s_x_1(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N1992_FROM
    );
  test2_top_kp_core_instance6_BU241 : X_LUT4
    generic map(
      INIT => X"3636"
    )
    port map (
      ADR0 => test2_top_s_x_1(9),
      ADR1 => test2_top_s_x_1(10),
      ADR2 => test2_top_s_x_1(8),
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N1992_GROM
    );
  test2_top_kp_core_instance6_N1992_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1992_FROM,
      O => test2_top_kp_core_instance6_N1992
    );
  test2_top_kp_core_instance6_N1992_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1992_GROM,
      O => test2_top_kp_core_instance6_N1991
    );
  test2_top_kp_core_instance6_N957_LOGIC_ZERO_54 : X_ZERO
    port map (
      O => test2_top_kp_core_instance6_N957_LOGIC_ZERO
    );
  test2_top_kp_core_instance6_BU366 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1989,
      IB => test2_top_kp_core_instance6_N957_CYINIT,
      SEL => test2_top_kp_core_instance6_N6197,
      O => test2_top_kp_core_instance6_N6200
    );
  test2_top_kp_core_instance6_BU367 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N957_CYINIT,
      I1 => test2_top_kp_core_instance6_N6197,
      O => test2_top_kp_core_instance6_N957_XORF
    );
  test2_top_kp_core_instance6_BU365 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1989,
      ADR1 => VCC,
      ADR2 => test2_top_s_x_1(12),
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6197
    );
  test2_top_kp_core_instance6_BU369 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1988,
      ADR1 => test2_top_kp_core_instance6_N2122,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6202
    );
  test2_top_kp_core_instance6_N957_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N957_CYMUXG,
      O => test2_top_kp_core_instance6_N6205
    );
  test2_top_kp_core_instance6_N957_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N957_XORF,
      O => test2_top_kp_core_instance6_N957
    );
  test2_top_kp_core_instance6_N957_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N957_XORG,
      O => test2_top_kp_core_instance6_N956
    );
  test2_top_kp_core_instance6_BU370 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1988,
      IB => test2_top_kp_core_instance6_N6200,
      SEL => test2_top_kp_core_instance6_N6202,
      O => test2_top_kp_core_instance6_N957_CYMUXG
    );
  test2_top_kp_core_instance6_BU371 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N6200,
      I1 => test2_top_kp_core_instance6_N6202,
      O => test2_top_kp_core_instance6_N957_XORG
    );
  test2_top_kp_core_instance6_N957_CYINIT_55 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N957_LOGIC_ZERO,
      O => test2_top_kp_core_instance6_N957_CYINIT
    );
  test2_top_kp_core_instance6_N234_LOGIC_ZERO_56 : X_ZERO
    port map (
      O => test2_top_kp_core_instance6_N234_LOGIC_ZERO
    );
  test2_top_kp_core_instance6_BU166 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1568,
      IB => test2_top_kp_core_instance6_N234_CYINIT,
      SEL => test2_top_kp_core_instance6_N5400,
      O => test2_top_kp_core_instance6_N5403
    );
  test2_top_kp_core_instance6_BU167 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N234_CYINIT,
      I1 => test2_top_kp_core_instance6_N5400,
      O => test2_top_kp_core_instance6_N234_XORF
    );
  test2_top_kp_core_instance6_BU165 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1568,
      ADR1 => test2_top_s_x_1(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5400
    );
  test2_top_kp_core_instance6_BU169 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1567,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N1701,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5405
    );
  test2_top_kp_core_instance6_N234_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N234_CYMUXG,
      O => test2_top_kp_core_instance6_N5408
    );
  test2_top_kp_core_instance6_N234_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N234_XORF,
      O => test2_top_kp_core_instance6_N234
    );
  test2_top_kp_core_instance6_N234_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N234_XORG,
      O => test2_top_kp_core_instance6_N233
    );
  test2_top_kp_core_instance6_BU170 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1567,
      IB => test2_top_kp_core_instance6_N5403,
      SEL => test2_top_kp_core_instance6_N5405,
      O => test2_top_kp_core_instance6_N234_CYMUXG
    );
  test2_top_kp_core_instance6_BU171 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N5403,
      I1 => test2_top_kp_core_instance6_N5405,
      O => test2_top_kp_core_instance6_N234_XORG
    );
  test2_top_kp_core_instance6_N234_CYINIT_57 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N234_LOGIC_ZERO,
      O => test2_top_kp_core_instance6_N234_CYINIT
    );
  test2_top_kp_core_instance6_BU497 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N214_CYINIT,
      I1 => test2_top_kp_core_instance6_N7283,
      O => test2_top_kp_core_instance6_N214_XORF
    );
  test2_top_kp_core_instance6_BU495 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N945,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7283
    );
  test2_top_kp_core_instance6_N214_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N214_XORF,
      O => test2_top_kp_core_instance6_N214
    );
  test2_top_kp_core_instance6_N214_CYINIT_58 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N7281,
      O => test2_top_kp_core_instance6_N214_CYINIT
    );
  test2_top_kp_core_instance6_N230_LOGIC_ZERO_59 : X_ZERO
    port map (
      O => test2_top_kp_core_instance6_N230_LOGIC_ZERO
    );
  test2_top_kp_core_instance6_BU432 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N925,
      IB => test2_top_kp_core_instance6_N230_CYINIT,
      SEL => test2_top_kp_core_instance6_N7203,
      O => test2_top_kp_core_instance6_N7206
    );
  test2_top_kp_core_instance6_BU433 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N230_CYINIT,
      I1 => test2_top_kp_core_instance6_N7203,
      O => test2_top_kp_core_instance6_N230_XORF
    );
  test2_top_kp_core_instance6_BU431 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N925,
      ADR1 => test2_top_s_x_1(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7203
    );
  test2_top_kp_core_instance6_BU435 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N924,
      ADR1 => test2_top_kp_core_instance6_N1992,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7208
    );
  test2_top_kp_core_instance6_N230_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N230_CYMUXG,
      O => test2_top_kp_core_instance6_N7211
    );
  test2_top_kp_core_instance6_N230_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N230_XORF,
      O => test2_top_kp_core_instance6_N230
    );
  test2_top_kp_core_instance6_N230_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N230_XORG,
      O => test2_top_kp_core_instance6_N229
    );
  test2_top_kp_core_instance6_BU436 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N924,
      IB => test2_top_kp_core_instance6_N7206,
      SEL => test2_top_kp_core_instance6_N7208,
      O => test2_top_kp_core_instance6_N230_CYMUXG
    );
  test2_top_kp_core_instance6_BU437 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N7206,
      I1 => test2_top_kp_core_instance6_N7208,
      O => test2_top_kp_core_instance6_N230_XORG
    );
  test2_top_kp_core_instance6_N230_CYINIT_60 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N230_LOGIC_ZERO,
      O => test2_top_kp_core_instance6_N230_CYINIT
    );
  test2_top_kp_core_instance6_N216_LOGIC_ZERO_61 : X_ZERO
    port map (
      O => test2_top_kp_core_instance6_N216_LOGIC_ZERO
    );
  test2_top_kp_core_instance6_BU488 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N216_LOGIC_ZERO,
      IB => test2_top_kp_core_instance6_N216_CYINIT,
      SEL => test2_top_kp_core_instance6_N7273,
      O => test2_top_kp_core_instance6_N7276
    );
  test2_top_kp_core_instance6_BU489 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N216_CYINIT,
      I1 => test2_top_kp_core_instance6_N7273,
      O => test2_top_kp_core_instance6_N216_XORF
    );
  test2_top_kp_core_instance6_BU487 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N947,
      O => test2_top_kp_core_instance6_N7273
    );
  test2_top_kp_core_instance6_BU491 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_kp_core_instance6_N946,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7278
    );
  test2_top_kp_core_instance6_N216_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N216_CYMUXG,
      O => test2_top_kp_core_instance6_N7281
    );
  test2_top_kp_core_instance6_N216_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N216_XORF,
      O => test2_top_kp_core_instance6_N216
    );
  test2_top_kp_core_instance6_N216_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N216_XORG,
      O => test2_top_kp_core_instance6_N215
    );
  test2_top_kp_core_instance6_BU492 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N216_LOGIC_ZERO,
      IB => test2_top_kp_core_instance6_N7276,
      SEL => test2_top_kp_core_instance6_N7278,
      O => test2_top_kp_core_instance6_N216_CYMUXG
    );
  test2_top_kp_core_instance6_BU493 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N7276,
      I1 => test2_top_kp_core_instance6_N7278,
      O => test2_top_kp_core_instance6_N216_XORG
    );
  test2_top_kp_core_instance6_N216_CYINIT_62 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N7271,
      O => test2_top_kp_core_instance6_N216_CYINIT
    );
  test2_top_kp_core_instance6_BU415 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N945_CYINIT,
      I1 => test2_top_kp_core_instance6_N6257,
      O => test2_top_kp_core_instance6_N945_XORF
    );
  test2_top_kp_core_instance6_BU413 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N2111,
      O => test2_top_kp_core_instance6_N6257
    );
  test2_top_kp_core_instance6_N945_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N945_XORF,
      O => test2_top_kp_core_instance6_N945
    );
  test2_top_kp_core_instance6_N945_CYINIT_63 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N6255,
      O => test2_top_kp_core_instance6_N945_CYINIT
    );
  test2_top_kp_core_instance6_N917_LOGIC_ZERO_64 : X_ZERO
    port map (
      O => test2_top_kp_core_instance6_N917_LOGIC_ZERO
    );
  test2_top_kp_core_instance6_BU214 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N917_LOGIC_ZERO,
      IB => test2_top_kp_core_instance6_N917_CYINIT,
      SEL => test2_top_kp_core_instance6_N5460,
      O => test2_top_kp_core_instance6_N5463
    );
  test2_top_kp_core_instance6_BU215 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N917_CYINIT,
      I1 => test2_top_kp_core_instance6_N5460,
      O => test2_top_kp_core_instance6_N917_XORF
    );
  test2_top_kp_core_instance6_BU213 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N1690,
      O => test2_top_kp_core_instance6_N5460
    );
  test2_top_kp_core_instance6_BU217 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_kp_core_instance6_N1689,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5465
    );
  test2_top_kp_core_instance6_N917_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N917_CYMUXG,
      O => test2_top_kp_core_instance6_N915
    );
  test2_top_kp_core_instance6_N917_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N917_XORF,
      O => test2_top_kp_core_instance6_N917
    );
  test2_top_kp_core_instance6_N917_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N917_XORG,
      O => test2_top_kp_core_instance6_N916
    );
  test2_top_kp_core_instance6_BU218 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N917_LOGIC_ZERO,
      IB => test2_top_kp_core_instance6_N5463,
      SEL => test2_top_kp_core_instance6_N5465,
      O => test2_top_kp_core_instance6_N917_CYMUXG
    );
  test2_top_kp_core_instance6_BU219 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N5463,
      I1 => test2_top_kp_core_instance6_N5465,
      O => test2_top_kp_core_instance6_N917_XORG
    );
  test2_top_kp_core_instance6_N917_CYINIT_65 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N5458,
      O => test2_top_kp_core_instance6_N917_CYINIT
    );
  test2_top_kp_core_instance6_N218_LOGIC_ZERO_66 : X_ZERO
    port map (
      O => test2_top_kp_core_instance6_N218_LOGIC_ZERO
    );
  test2_top_kp_core_instance6_BU480 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N218_LOGIC_ZERO,
      IB => test2_top_kp_core_instance6_N218_CYINIT,
      SEL => test2_top_kp_core_instance6_N7263,
      O => test2_top_kp_core_instance6_N7266
    );
  test2_top_kp_core_instance6_BU481 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N218_CYINIT,
      I1 => test2_top_kp_core_instance6_N7263,
      O => test2_top_kp_core_instance6_N218_XORF
    );
  test2_top_kp_core_instance6_BU479 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N949,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7263
    );
  test2_top_kp_core_instance6_BU483 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_kp_core_instance6_N948,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7268
    );
  test2_top_kp_core_instance6_N218_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N218_CYMUXG,
      O => test2_top_kp_core_instance6_N7271
    );
  test2_top_kp_core_instance6_N218_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N218_XORF,
      O => test2_top_kp_core_instance6_N218
    );
  test2_top_kp_core_instance6_N218_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N218_XORG,
      O => test2_top_kp_core_instance6_N217
    );
  test2_top_kp_core_instance6_BU484 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N218_LOGIC_ZERO,
      IB => test2_top_kp_core_instance6_N7266,
      SEL => test2_top_kp_core_instance6_N7268,
      O => test2_top_kp_core_instance6_N218_CYMUXG
    );
  test2_top_kp_core_instance6_BU485 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N7266,
      I1 => test2_top_kp_core_instance6_N7268,
      O => test2_top_kp_core_instance6_N218_XORG
    );
  test2_top_kp_core_instance6_N218_CYINIT_67 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N7261,
      O => test2_top_kp_core_instance6_N218_CYINIT
    );
  test2_top_kp_core_instance6_BU149 : X_LUT4
    generic map(
      INIT => X"70F0"
    )
    port map (
      ADR0 => test2_top_s_x_1(4),
      ADR1 => test2_top_s_x_1(5),
      ADR2 => test2_top_s_x_1(7),
      ADR3 => test2_top_s_x_1(6),
      O => test2_top_kp_core_instance6_N1690_FROM
    );
  test2_top_kp_core_instance6_BU145 : X_LUT4
    generic map(
      INIT => X"7F80"
    )
    port map (
      ADR0 => test2_top_s_x_1(4),
      ADR1 => test2_top_s_x_1(5),
      ADR2 => test2_top_s_x_1(7),
      ADR3 => test2_top_s_x_1(6),
      O => test2_top_kp_core_instance6_N1690_GROM
    );
  test2_top_kp_core_instance6_N1690_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1690_FROM,
      O => test2_top_kp_core_instance6_N1690
    );
  test2_top_kp_core_instance6_N1690_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1690_GROM,
      O => test2_top_kp_core_instance6_N1691
    );
  test2_top_kp_core_instance6_BU76 : X_LUT4
    generic map(
      INIT => X"6AAA"
    )
    port map (
      ADR0 => test2_top_s_x_1(2),
      ADR1 => test2_top_s_x_1(3),
      ADR2 => test2_top_s_x_1(0),
      ADR3 => test2_top_s_x_1(1),
      O => test2_top_kp_core_instance6_N1561_FROM
    );
  test2_top_kp_core_instance6_BU80 : X_LUT4
    generic map(
      INIT => X"70F0"
    )
    port map (
      ADR0 => test2_top_s_x_1(2),
      ADR1 => test2_top_s_x_1(0),
      ADR2 => test2_top_s_x_1(3),
      ADR3 => test2_top_s_x_1(1),
      O => test2_top_kp_core_instance6_N1561_GROM
    );
  test2_top_kp_core_instance6_N1561_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1561_FROM,
      O => test2_top_kp_core_instance6_N1561
    );
  test2_top_kp_core_instance6_N1561_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1561_GROM,
      O => test2_top_kp_core_instance6_N1560
    );
  test2_top_kp_core_instance6_BU346 : X_LUT4
    generic map(
      INIT => X"CCC6"
    )
    port map (
      ADR0 => test2_top_s_x_1(15),
      ADR1 => test2_top_s_x_1(14),
      ADR2 => test2_top_s_x_1(12),
      ADR3 => test2_top_s_x_1(13),
      O => test2_top_kp_core_instance6_N2112_FROM
    );
  test2_top_kp_core_instance6_BU350 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => test2_top_s_x_1(15),
      ADR1 => test2_top_s_x_1(12),
      ADR2 => test2_top_s_x_1(14),
      ADR3 => test2_top_s_x_1(13),
      O => test2_top_kp_core_instance6_N2112_GROM
    );
  test2_top_kp_core_instance6_N2112_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2112_FROM,
      O => test2_top_kp_core_instance6_N2112
    );
  test2_top_kp_core_instance6_N2112_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2112_GROM,
      O => test2_top_kp_core_instance6_N2111
    );
  test2_top_kp_core_instance6_BU277 : X_LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      ADR0 => test2_top_s_x_1(8),
      ADR1 => test2_top_s_x_1(10),
      ADR2 => test2_top_s_x_1(11),
      ADR3 => test2_top_s_x_1(9),
      O => test2_top_kp_core_instance6_N1982_FROM
    );
  test2_top_kp_core_instance6_BU281 : X_LUT4
    generic map(
      INIT => X"70F0"
    )
    port map (
      ADR0 => test2_top_s_x_1(10),
      ADR1 => test2_top_s_x_1(9),
      ADR2 => test2_top_s_x_1(11),
      ADR3 => test2_top_s_x_1(8),
      O => test2_top_kp_core_instance6_N1982_GROM
    );
  test2_top_kp_core_instance6_N1982_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1982_FROM,
      O => test2_top_kp_core_instance6_N1982
    );
  test2_top_kp_core_instance6_N1982_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1982_GROM,
      O => test2_top_kp_core_instance6_N1981
    );
  test2_top_kp_core_instance6_N947_LOGIC_ZERO_68 : X_ZERO
    port map (
      O => test2_top_kp_core_instance6_N947_LOGIC_ZERO
    );
  test2_top_kp_core_instance6_BU406 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N947_LOGIC_ZERO,
      IB => test2_top_kp_core_instance6_N947_CYINIT,
      SEL => test2_top_kp_core_instance6_N6247,
      O => test2_top_kp_core_instance6_N6250
    );
  test2_top_kp_core_instance6_BU407 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N947_CYINIT,
      I1 => test2_top_kp_core_instance6_N6247,
      O => test2_top_kp_core_instance6_N947_XORF
    );
  test2_top_kp_core_instance6_BU405 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N2113,
      O => test2_top_kp_core_instance6_N6247
    );
  test2_top_kp_core_instance6_BU409 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N2112,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6252
    );
  test2_top_kp_core_instance6_N947_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N947_CYMUXG,
      O => test2_top_kp_core_instance6_N6255
    );
  test2_top_kp_core_instance6_N947_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N947_XORF,
      O => test2_top_kp_core_instance6_N947
    );
  test2_top_kp_core_instance6_N947_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N947_XORG,
      O => test2_top_kp_core_instance6_N946
    );
  test2_top_kp_core_instance6_BU410 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N947_LOGIC_ZERO,
      IB => test2_top_kp_core_instance6_N6250,
      SEL => test2_top_kp_core_instance6_N6252,
      O => test2_top_kp_core_instance6_N947_CYMUXG
    );
  test2_top_kp_core_instance6_BU411 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N6250,
      I1 => test2_top_kp_core_instance6_N6252,
      O => test2_top_kp_core_instance6_N947_XORG
    );
  test2_top_kp_core_instance6_N947_CYINIT_69 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N6245,
      O => test2_top_kp_core_instance6_N947_CYINIT
    );
  test2_top_kp_core_instance6_N919_LOGIC_ZERO_70 : X_ZERO
    port map (
      O => test2_top_kp_core_instance6_N919_LOGIC_ZERO
    );
  test2_top_kp_core_instance6_BU206 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N919_LOGIC_ZERO,
      IB => test2_top_kp_core_instance6_N919_CYINIT,
      SEL => test2_top_kp_core_instance6_N5450,
      O => test2_top_kp_core_instance6_N5453
    );
  test2_top_kp_core_instance6_BU207 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N919_CYINIT,
      I1 => test2_top_kp_core_instance6_N5450,
      O => test2_top_kp_core_instance6_N919_XORF
    );
  test2_top_kp_core_instance6_BU205 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N1692,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5450
    );
  test2_top_kp_core_instance6_BU209 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_kp_core_instance6_N1691,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5455
    );
  test2_top_kp_core_instance6_N919_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N919_CYMUXG,
      O => test2_top_kp_core_instance6_N5458
    );
  test2_top_kp_core_instance6_N919_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N919_XORF,
      O => test2_top_kp_core_instance6_N919
    );
  test2_top_kp_core_instance6_N919_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N919_XORG,
      O => test2_top_kp_core_instance6_N918
    );
  test2_top_kp_core_instance6_BU210 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N919_LOGIC_ZERO,
      IB => test2_top_kp_core_instance6_N5453,
      SEL => test2_top_kp_core_instance6_N5455,
      O => test2_top_kp_core_instance6_N919_CYMUXG
    );
  test2_top_kp_core_instance6_BU211 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N5453,
      I1 => test2_top_kp_core_instance6_N5455,
      O => test2_top_kp_core_instance6_N919_XORG
    );
  test2_top_kp_core_instance6_N919_CYINIT_71 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N5448,
      O => test2_top_kp_core_instance6_N919_CYINIT
    );
  test2_top_kp_core_instance6_BU472 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N915,
      IB => test2_top_kp_core_instance6_N220_CYINIT,
      SEL => test2_top_kp_core_instance6_N7253,
      O => test2_top_kp_core_instance6_N7256
    );
  test2_top_kp_core_instance6_BU473 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N220_CYINIT,
      I1 => test2_top_kp_core_instance6_N7253,
      O => test2_top_kp_core_instance6_N220_XORF
    );
  test2_top_kp_core_instance6_BU471 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N915,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N951,
      O => test2_top_kp_core_instance6_N7253
    );
  test2_top_kp_core_instance6_BU475 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => test2_top_kp_core_instance6_N950,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7258
    );
  test2_top_kp_core_instance6_N220_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N220_CYMUXG,
      O => test2_top_kp_core_instance6_N7261
    );
  test2_top_kp_core_instance6_N220_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N220_XORF,
      O => test2_top_kp_core_instance6_N220
    );
  test2_top_kp_core_instance6_N220_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N220_XORG,
      O => test2_top_kp_core_instance6_N219
    );
  test2_top_kp_core_instance6_BU476 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => test2_top_kp_core_instance6_N7256,
      SEL => test2_top_kp_core_instance6_N7258,
      O => test2_top_kp_core_instance6_N220_CYMUXG
    );
  test2_top_kp_core_instance6_BU477 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N7256,
      I1 => test2_top_kp_core_instance6_N7258,
      O => test2_top_kp_core_instance6_N220_XORG
    );
  test2_top_kp_core_instance6_N220_CYINIT_72 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N7251,
      O => test2_top_kp_core_instance6_N220_CYINIT
    );
  test2_top_kp_core_instance6_BU137 : X_LUT4
    generic map(
      INIT => X"3C70"
    )
    port map (
      ADR0 => test2_top_s_x_1(5),
      ADR1 => test2_top_s_x_1(7),
      ADR2 => test2_top_s_x_1(4),
      ADR3 => test2_top_s_x_1(6),
      O => test2_top_kp_core_instance6_N1693_FROM
    );
  test2_top_kp_core_instance6_BU141 : X_LUT4
    generic map(
      INIT => X"62AA"
    )
    port map (
      ADR0 => test2_top_s_x_1(5),
      ADR1 => test2_top_s_x_1(7),
      ADR2 => test2_top_s_x_1(6),
      ADR3 => test2_top_s_x_1(4),
      O => test2_top_kp_core_instance6_N1693_GROM
    );
  test2_top_kp_core_instance6_N1693_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1693_FROM,
      O => test2_top_kp_core_instance6_N1693
    );
  test2_top_kp_core_instance6_N1693_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1693_GROM,
      O => test2_top_kp_core_instance6_N1692
    );
  test2_top_kp_core_instance6_BU68 : X_LUT4
    generic map(
      INIT => X"3788"
    )
    port map (
      ADR0 => test2_top_s_x_1(2),
      ADR1 => test2_top_s_x_1(3),
      ADR2 => test2_top_s_x_1(1),
      ADR3 => test2_top_s_x_1(0),
      O => test2_top_kp_core_instance6_N1563_FROM
    );
  test2_top_kp_core_instance6_BU72 : X_LUT4
    generic map(
      INIT => X"38F0"
    )
    port map (
      ADR0 => test2_top_s_x_1(2),
      ADR1 => test2_top_s_x_1(3),
      ADR2 => test2_top_s_x_1(1),
      ADR3 => test2_top_s_x_1(0),
      O => test2_top_kp_core_instance6_N1563_GROM
    );
  test2_top_kp_core_instance6_N1563_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1563_FROM,
      O => test2_top_kp_core_instance6_N1563
    );
  test2_top_kp_core_instance6_N1563_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1563_GROM,
      O => test2_top_kp_core_instance6_N1562
    );
  test2_top_kp_core_instance6_BU338 : X_LUT4
    generic map(
      INIT => X"33CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_s_x_1(15),
      ADR2 => VCC,
      ADR3 => test2_top_s_x_1(12),
      O => test2_top_kp_core_instance6_N2114_FROM
    );
  test2_top_kp_core_instance6_BU342 : X_LUT4
    generic map(
      INIT => X"D2D2"
    )
    port map (
      ADR0 => test2_top_s_x_1(15),
      ADR1 => test2_top_s_x_1(12),
      ADR2 => test2_top_s_x_1(13),
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N2114_GROM
    );
  test2_top_kp_core_instance6_N2114_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2114_FROM,
      O => test2_top_kp_core_instance6_N2114
    );
  test2_top_kp_core_instance6_N2114_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2114_GROM,
      O => test2_top_kp_core_instance6_N2113
    );
  test2_top_kp_core_instance6_BU269 : X_LUT4
    generic map(
      INIT => X"3C4C"
    )
    port map (
      ADR0 => test2_top_s_x_1(9),
      ADR1 => test2_top_s_x_1(8),
      ADR2 => test2_top_s_x_1(11),
      ADR3 => test2_top_s_x_1(10),
      O => test2_top_kp_core_instance6_N1984_FROM
    );
  test2_top_kp_core_instance6_BU273 : X_LUT4
    generic map(
      INIT => X"64CC"
    )
    port map (
      ADR0 => test2_top_s_x_1(11),
      ADR1 => test2_top_s_x_1(9),
      ADR2 => test2_top_s_x_1(10),
      ADR3 => test2_top_s_x_1(8),
      O => test2_top_kp_core_instance6_N1984_GROM
    );
  test2_top_kp_core_instance6_N1984_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1984_FROM,
      O => test2_top_kp_core_instance6_N1984
    );
  test2_top_kp_core_instance6_N1984_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1984_GROM,
      O => test2_top_kp_core_instance6_N1983
    );
  test2_top_kp_core_instance6_BU398 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1981,
      IB => test2_top_kp_core_instance6_N949_CYINIT,
      SEL => test2_top_kp_core_instance6_N6237,
      O => test2_top_kp_core_instance6_N6240
    );
  test2_top_kp_core_instance6_BU399 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N949_CYINIT,
      I1 => test2_top_kp_core_instance6_N6237,
      O => test2_top_kp_core_instance6_N949_XORF
    );
  test2_top_kp_core_instance6_BU397 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1981,
      ADR1 => test2_top_kp_core_instance6_N2115,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6237
    );
  test2_top_kp_core_instance6_BU401 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1980,
      ADR1 => test2_top_kp_core_instance6_N2114,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6242
    );
  test2_top_kp_core_instance6_N949_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N949_CYMUXG,
      O => test2_top_kp_core_instance6_N6245
    );
  test2_top_kp_core_instance6_N949_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N949_XORF,
      O => test2_top_kp_core_instance6_N949
    );
  test2_top_kp_core_instance6_N949_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N949_XORG,
      O => test2_top_kp_core_instance6_N948
    );
  test2_top_kp_core_instance6_BU402 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1980,
      IB => test2_top_kp_core_instance6_N6240,
      SEL => test2_top_kp_core_instance6_N6242,
      O => test2_top_kp_core_instance6_N949_CYMUXG
    );
  test2_top_kp_core_instance6_BU403 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N6240,
      I1 => test2_top_kp_core_instance6_N6242,
      O => test2_top_kp_core_instance6_N949_XORG
    );
  test2_top_kp_core_instance6_N949_CYINIT_73 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N6235,
      O => test2_top_kp_core_instance6_N949_CYINIT
    );
  test2_top_kp_core_instance6_BU198 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1560,
      IB => test2_top_kp_core_instance6_N921_CYINIT,
      SEL => test2_top_kp_core_instance6_N5440,
      O => test2_top_kp_core_instance6_N5443
    );
  test2_top_kp_core_instance6_BU199 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N921_CYINIT,
      I1 => test2_top_kp_core_instance6_N5440,
      O => test2_top_kp_core_instance6_N921_XORF
    );
  test2_top_kp_core_instance6_BU197 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1560,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N1694,
      O => test2_top_kp_core_instance6_N5440
    );
  test2_top_kp_core_instance6_BU201 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1559,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N1693,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5445
    );
  test2_top_kp_core_instance6_N921_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N921_CYMUXG,
      O => test2_top_kp_core_instance6_N5448
    );
  test2_top_kp_core_instance6_N921_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N921_XORF,
      O => test2_top_kp_core_instance6_N921
    );
  test2_top_kp_core_instance6_N921_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N921_XORG,
      O => test2_top_kp_core_instance6_N920
    );
  test2_top_kp_core_instance6_BU202 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1559,
      IB => test2_top_kp_core_instance6_N5443,
      SEL => test2_top_kp_core_instance6_N5445,
      O => test2_top_kp_core_instance6_N921_CYMUXG
    );
  test2_top_kp_core_instance6_BU203 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N5443,
      I1 => test2_top_kp_core_instance6_N5445,
      O => test2_top_kp_core_instance6_N921_XORG
    );
  test2_top_kp_core_instance6_N921_CYINIT_74 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N5438,
      O => test2_top_kp_core_instance6_N921_CYINIT
    );
  test2_top_kp_core_instance6_BU464 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N917,
      IB => test2_top_kp_core_instance6_N222_CYINIT,
      SEL => test2_top_kp_core_instance6_N7243,
      O => test2_top_kp_core_instance6_N7246
    );
  test2_top_kp_core_instance6_BU465 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N222_CYINIT,
      I1 => test2_top_kp_core_instance6_N7243,
      O => test2_top_kp_core_instance6_N222_XORF
    );
  test2_top_kp_core_instance6_BU463 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N917,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N953,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7243
    );
  test2_top_kp_core_instance6_BU467 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N916,
      ADR1 => test2_top_kp_core_instance6_N952,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7248
    );
  test2_top_kp_core_instance6_N222_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N222_CYMUXG,
      O => test2_top_kp_core_instance6_N7251
    );
  test2_top_kp_core_instance6_N222_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N222_XORF,
      O => test2_top_kp_core_instance6_N222
    );
  test2_top_kp_core_instance6_N222_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N222_XORG,
      O => test2_top_kp_core_instance6_N221
    );
  test2_top_kp_core_instance6_BU468 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N916,
      IB => test2_top_kp_core_instance6_N7246,
      SEL => test2_top_kp_core_instance6_N7248,
      O => test2_top_kp_core_instance6_N222_CYMUXG
    );
  test2_top_kp_core_instance6_BU469 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N7246,
      I1 => test2_top_kp_core_instance6_N7248,
      O => test2_top_kp_core_instance6_N222_XORG
    );
  test2_top_kp_core_instance6_N222_CYINIT_75 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N7241,
      O => test2_top_kp_core_instance6_N222_CYINIT
    );
  test2_top_kp_core_instance6_BU129 : X_LUT4
    generic map(
      INIT => X"9A64"
    )
    port map (
      ADR0 => test2_top_s_x_1(5),
      ADR1 => test2_top_s_x_1(6),
      ADR2 => test2_top_s_x_1(4),
      ADR3 => test2_top_s_x_1(7),
      O => test2_top_kp_core_instance6_N1695_FROM
    );
  test2_top_kp_core_instance6_BU133 : X_LUT4
    generic map(
      INIT => X"224C"
    )
    port map (
      ADR0 => test2_top_s_x_1(5),
      ADR1 => test2_top_s_x_1(7),
      ADR2 => test2_top_s_x_1(4),
      ADR3 => test2_top_s_x_1(6),
      O => test2_top_kp_core_instance6_N1695_GROM
    );
  test2_top_kp_core_instance6_N1695_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1695_FROM,
      O => test2_top_kp_core_instance6_N1695
    );
  test2_top_kp_core_instance6_N1695_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1695_GROM,
      O => test2_top_kp_core_instance6_N1694
    );
  test2_top_kp_core_instance6_BU64 : X_LUT4
    generic map(
      INIT => X"0C70"
    )
    port map (
      ADR0 => test2_top_s_x_1(0),
      ADR1 => test2_top_s_x_1(1),
      ADR2 => test2_top_s_x_1(3),
      ADR3 => test2_top_s_x_1(2),
      O => test2_top_kp_core_instance6_N1564_FROM
    );
  test2_top_kp_core_instance6_BU60 : X_LUT4
    generic map(
      INIT => X"C638"
    )
    port map (
      ADR0 => test2_top_s_x_1(0),
      ADR1 => test2_top_s_x_1(3),
      ADR2 => test2_top_s_x_1(2),
      ADR3 => test2_top_s_x_1(1),
      O => test2_top_kp_core_instance6_N1564_GROM
    );
  test2_top_kp_core_instance6_N1564_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1564_FROM,
      O => test2_top_kp_core_instance6_N1564
    );
  test2_top_kp_core_instance6_N1564_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1564_GROM,
      O => test2_top_kp_core_instance6_N1565
    );
  test2_top_kp_core_instance6_BU334 : X_LUT4
    generic map(
      INIT => X"F8A0"
    )
    port map (
      ADR0 => test2_top_s_x_1(13),
      ADR1 => test2_top_s_x_1(12),
      ADR2 => test2_top_s_x_1(14),
      ADR3 => test2_top_s_x_1(15),
      O => test2_top_kp_core_instance6_N2115_FROM
    );
  test2_top_kp_core_instance6_BU330 : X_LUT4
    generic map(
      INIT => X"A56A"
    )
    port map (
      ADR0 => test2_top_s_x_1(15),
      ADR1 => test2_top_s_x_1(12),
      ADR2 => test2_top_s_x_1(13),
      ADR3 => test2_top_s_x_1(14),
      O => test2_top_kp_core_instance6_N2115_GROM
    );
  test2_top_kp_core_instance6_N2115_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2115_FROM,
      O => test2_top_kp_core_instance6_N2115
    );
  test2_top_kp_core_instance6_N2115_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2115_GROM,
      O => test2_top_kp_core_instance6_N2116
    );
  test2_top_kp_core_instance6_BU265 : X_LUT4
    generic map(
      INIT => X"1C30"
    )
    port map (
      ADR0 => test2_top_s_x_1(8),
      ADR1 => test2_top_s_x_1(10),
      ADR2 => test2_top_s_x_1(11),
      ADR3 => test2_top_s_x_1(9),
      O => test2_top_kp_core_instance6_N1985_FROM
    );
  test2_top_kp_core_instance6_BU261 : X_LUT4
    generic map(
      INIT => X"9698"
    )
    port map (
      ADR0 => test2_top_s_x_1(9),
      ADR1 => test2_top_s_x_1(11),
      ADR2 => test2_top_s_x_1(10),
      ADR3 => test2_top_s_x_1(8),
      O => test2_top_kp_core_instance6_N1985_GROM
    );
  test2_top_kp_core_instance6_N1985_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1985_FROM,
      O => test2_top_kp_core_instance6_N1985
    );
  test2_top_kp_core_instance6_N1985_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1985_GROM,
      O => test2_top_kp_core_instance6_N1986
    );
  test2_top_kp_core_instance6_BU390 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1983,
      IB => test2_top_kp_core_instance6_N951_CYINIT,
      SEL => test2_top_kp_core_instance6_N6227,
      O => test2_top_kp_core_instance6_N6230
    );
  test2_top_kp_core_instance6_BU391 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N951_CYINIT,
      I1 => test2_top_kp_core_instance6_N6227,
      O => test2_top_kp_core_instance6_N951_XORF
    );
  test2_top_kp_core_instance6_BU389 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1983,
      ADR1 => test2_top_kp_core_instance6_N2117,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6227
    );
  test2_top_kp_core_instance6_BU393 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1982,
      ADR1 => test2_top_kp_core_instance6_N2116,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6232
    );
  test2_top_kp_core_instance6_N951_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N951_CYMUXG,
      O => test2_top_kp_core_instance6_N6235
    );
  test2_top_kp_core_instance6_N951_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N951_XORF,
      O => test2_top_kp_core_instance6_N951
    );
  test2_top_kp_core_instance6_N951_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N951_XORG,
      O => test2_top_kp_core_instance6_N950
    );
  test2_top_kp_core_instance6_BU394 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1982,
      IB => test2_top_kp_core_instance6_N6230,
      SEL => test2_top_kp_core_instance6_N6232,
      O => test2_top_kp_core_instance6_N951_CYMUXG
    );
  test2_top_kp_core_instance6_BU395 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N6230,
      I1 => test2_top_kp_core_instance6_N6232,
      O => test2_top_kp_core_instance6_N951_XORG
    );
  test2_top_kp_core_instance6_N951_CYINIT_76 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N6225,
      O => test2_top_kp_core_instance6_N951_CYINIT
    );
  test2_top_kp_core_instance6_BU190 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1562,
      IB => test2_top_kp_core_instance6_N923_CYINIT,
      SEL => test2_top_kp_core_instance6_N5430,
      O => test2_top_kp_core_instance6_N5433
    );
  test2_top_kp_core_instance6_BU191 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N923_CYINIT,
      I1 => test2_top_kp_core_instance6_N5430,
      O => test2_top_kp_core_instance6_N923_XORF
    );
  test2_top_kp_core_instance6_BU189 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1562,
      ADR1 => test2_top_kp_core_instance6_N1696,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5430
    );
  test2_top_kp_core_instance6_BU193 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1561,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N1695,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5435
    );
  test2_top_kp_core_instance6_N923_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N923_CYMUXG,
      O => test2_top_kp_core_instance6_N5438
    );
  test2_top_kp_core_instance6_N923_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N923_XORF,
      O => test2_top_kp_core_instance6_N923
    );
  test2_top_kp_core_instance6_N923_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N923_XORG,
      O => test2_top_kp_core_instance6_N922
    );
  test2_top_kp_core_instance6_BU194 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1561,
      IB => test2_top_kp_core_instance6_N5433,
      SEL => test2_top_kp_core_instance6_N5435,
      O => test2_top_kp_core_instance6_N923_CYMUXG
    );
  test2_top_kp_core_instance6_BU195 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N5433,
      I1 => test2_top_kp_core_instance6_N5435,
      O => test2_top_kp_core_instance6_N923_XORG
    );
  test2_top_kp_core_instance6_N923_CYINIT_77 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N5428,
      O => test2_top_kp_core_instance6_N923_CYINIT
    );
  test2_top_kp_core_instance6_BU456 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N919,
      IB => test2_top_kp_core_instance6_N224_CYINIT,
      SEL => test2_top_kp_core_instance6_N7233,
      O => test2_top_kp_core_instance6_N7236
    );
  test2_top_kp_core_instance6_BU457 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N224_CYINIT,
      I1 => test2_top_kp_core_instance6_N7233,
      O => test2_top_kp_core_instance6_N224_XORF
    );
  test2_top_kp_core_instance6_BU455 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N919,
      ADR1 => test2_top_kp_core_instance6_N955,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7233
    );
  test2_top_kp_core_instance6_BU459 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N918,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N954,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7238
    );
  test2_top_kp_core_instance6_N224_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N224_CYMUXG,
      O => test2_top_kp_core_instance6_N7241
    );
  test2_top_kp_core_instance6_N224_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N224_XORF,
      O => test2_top_kp_core_instance6_N224
    );
  test2_top_kp_core_instance6_N224_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N224_XORG,
      O => test2_top_kp_core_instance6_N223
    );
  test2_top_kp_core_instance6_BU460 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N918,
      IB => test2_top_kp_core_instance6_N7236,
      SEL => test2_top_kp_core_instance6_N7238,
      O => test2_top_kp_core_instance6_N224_CYMUXG
    );
  test2_top_kp_core_instance6_BU461 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N7236,
      I1 => test2_top_kp_core_instance6_N7238,
      O => test2_top_kp_core_instance6_N224_XORG
    );
  test2_top_kp_core_instance6_N224_CYINIT_78 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N7231,
      O => test2_top_kp_core_instance6_N224_CYINIT
    );
  test2_top_kp_core_instance6_BU125 : X_LUT4
    generic map(
      INIT => X"F00E"
    )
    port map (
      ADR0 => test2_top_s_x_1(5),
      ADR1 => test2_top_s_x_1(7),
      ADR2 => test2_top_s_x_1(6),
      ADR3 => test2_top_s_x_1(4),
      O => test2_top_kp_core_instance6_N1696_FROM
    );
  test2_top_kp_core_instance6_BU121 : X_LUT4
    generic map(
      INIT => X"00FE"
    )
    port map (
      ADR0 => test2_top_s_x_1(6),
      ADR1 => test2_top_s_x_1(7),
      ADR2 => test2_top_s_x_1(4),
      ADR3 => test2_top_s_x_1(5),
      O => test2_top_kp_core_instance6_N1696_GROM
    );
  test2_top_kp_core_instance6_N1696_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1696_FROM,
      O => test2_top_kp_core_instance6_N1696
    );
  test2_top_kp_core_instance6_N1696_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1696_GROM,
      O => test2_top_kp_core_instance6_N1697
    );
  test2_top_kp_core_instance6_BU56 : X_LUT4
    generic map(
      INIT => X"A5A4"
    )
    port map (
      ADR0 => test2_top_s_x_1(2),
      ADR1 => test2_top_s_x_1(3),
      ADR2 => test2_top_s_x_1(0),
      ADR3 => test2_top_s_x_1(1),
      O => test2_top_kp_core_instance6_N1566_FROM
    );
  test2_top_kp_core_instance6_BU52 : X_LUT4
    generic map(
      INIT => X"5554"
    )
    port map (
      ADR0 => test2_top_s_x_1(1),
      ADR1 => test2_top_s_x_1(2),
      ADR2 => test2_top_s_x_1(0),
      ADR3 => test2_top_s_x_1(3),
      O => test2_top_kp_core_instance6_N1566_GROM
    );
  test2_top_kp_core_instance6_N1566_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1566_FROM,
      O => test2_top_kp_core_instance6_N1566
    );
  test2_top_kp_core_instance6_N1566_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1566_GROM,
      O => test2_top_kp_core_instance6_N1567
    );
  test2_top_kp_core_instance6_BU326 : X_LUT4
    generic map(
      INIT => X"9C98"
    )
    port map (
      ADR0 => test2_top_s_x_1(12),
      ADR1 => test2_top_s_x_1(14),
      ADR2 => test2_top_s_x_1(13),
      ADR3 => test2_top_s_x_1(15),
      O => test2_top_kp_core_instance6_N2117_FROM
    );
  test2_top_kp_core_instance6_BU322 : X_LUT4
    generic map(
      INIT => X"5A0E"
    )
    port map (
      ADR0 => test2_top_s_x_1(12),
      ADR1 => test2_top_s_x_1(14),
      ADR2 => test2_top_s_x_1(13),
      ADR3 => test2_top_s_x_1(15),
      O => test2_top_kp_core_instance6_N2117_GROM
    );
  test2_top_kp_core_instance6_N2117_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2117_FROM,
      O => test2_top_kp_core_instance6_N2117
    );
  test2_top_kp_core_instance6_N2117_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2117_GROM,
      O => test2_top_kp_core_instance6_N2118
    );
  test2_top_kp_core_instance6_BU257 : X_LUT4
    generic map(
      INIT => X"CC32"
    )
    port map (
      ADR0 => test2_top_s_x_1(11),
      ADR1 => test2_top_s_x_1(10),
      ADR2 => test2_top_s_x_1(9),
      ADR3 => test2_top_s_x_1(8),
      O => test2_top_kp_core_instance6_N1987_FROM
    );
  test2_top_kp_core_instance6_BU253 : X_LUT4
    generic map(
      INIT => X"3332"
    )
    port map (
      ADR0 => test2_top_s_x_1(10),
      ADR1 => test2_top_s_x_1(9),
      ADR2 => test2_top_s_x_1(8),
      ADR3 => test2_top_s_x_1(11),
      O => test2_top_kp_core_instance6_N1987_GROM
    );
  test2_top_kp_core_instance6_N1987_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1987_FROM,
      O => test2_top_kp_core_instance6_N1987
    );
  test2_top_kp_core_instance6_N1987_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1987_GROM,
      O => test2_top_kp_core_instance6_N1988
    );
  test2_top_kp_core_instance6_BU382 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1985,
      IB => test2_top_kp_core_instance6_N953_CYINIT,
      SEL => test2_top_kp_core_instance6_N6217,
      O => test2_top_kp_core_instance6_N6220
    );
  test2_top_kp_core_instance6_BU383 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N953_CYINIT,
      I1 => test2_top_kp_core_instance6_N6217,
      O => test2_top_kp_core_instance6_N953_XORF
    );
  test2_top_kp_core_instance6_BU381 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1985,
      ADR1 => test2_top_kp_core_instance6_N2119,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6217
    );
  test2_top_kp_core_instance6_BU385 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1984,
      ADR1 => test2_top_kp_core_instance6_N2118,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6222
    );
  test2_top_kp_core_instance6_N953_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N953_CYMUXG,
      O => test2_top_kp_core_instance6_N6225
    );
  test2_top_kp_core_instance6_N953_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N953_XORF,
      O => test2_top_kp_core_instance6_N953
    );
  test2_top_kp_core_instance6_N953_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N953_XORG,
      O => test2_top_kp_core_instance6_N952
    );
  test2_top_kp_core_instance6_BU386 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1984,
      IB => test2_top_kp_core_instance6_N6220,
      SEL => test2_top_kp_core_instance6_N6222,
      O => test2_top_kp_core_instance6_N953_CYMUXG
    );
  test2_top_kp_core_instance6_BU387 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N6220,
      I1 => test2_top_kp_core_instance6_N6222,
      O => test2_top_kp_core_instance6_N953_XORG
    );
  test2_top_kp_core_instance6_N953_CYINIT_79 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N6215,
      O => test2_top_kp_core_instance6_N953_CYINIT
    );
  test2_top_kp_core_instance6_BU182 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1564,
      IB => test2_top_kp_core_instance6_N925_CYINIT,
      SEL => test2_top_kp_core_instance6_N5420,
      O => test2_top_kp_core_instance6_N5423
    );
  test2_top_kp_core_instance6_BU183 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N925_CYINIT,
      I1 => test2_top_kp_core_instance6_N5420,
      O => test2_top_kp_core_instance6_N925_XORF
    );
  test2_top_kp_core_instance6_BU181 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1564,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N1698,
      O => test2_top_kp_core_instance6_N5420
    );
  test2_top_kp_core_instance6_BU185 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1563,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N1697,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5425
    );
  test2_top_kp_core_instance6_N925_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N925_CYMUXG,
      O => test2_top_kp_core_instance6_N5428
    );
  test2_top_kp_core_instance6_N925_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N925_XORF,
      O => test2_top_kp_core_instance6_N925
    );
  test2_top_kp_core_instance6_N925_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N925_XORG,
      O => test2_top_kp_core_instance6_N924
    );
  test2_top_kp_core_instance6_BU186 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1563,
      IB => test2_top_kp_core_instance6_N5423,
      SEL => test2_top_kp_core_instance6_N5425,
      O => test2_top_kp_core_instance6_N925_CYMUXG
    );
  test2_top_kp_core_instance6_BU187 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N5423,
      I1 => test2_top_kp_core_instance6_N5425,
      O => test2_top_kp_core_instance6_N925_XORG
    );
  test2_top_kp_core_instance6_N925_CYINIT_80 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N5418,
      O => test2_top_kp_core_instance6_N925_CYINIT
    );
  test2_top_kp_core_instance6_BU448 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N921,
      IB => test2_top_kp_core_instance6_N226_CYINIT,
      SEL => test2_top_kp_core_instance6_N7223,
      O => test2_top_kp_core_instance6_N7226
    );
  test2_top_kp_core_instance6_BU449 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N226_CYINIT,
      I1 => test2_top_kp_core_instance6_N7223,
      O => test2_top_kp_core_instance6_N226_XORF
    );
  test2_top_kp_core_instance6_BU447 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N921,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N957,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N7223
    );
  test2_top_kp_core_instance6_BU451 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N920,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kp_core_instance6_N956,
      O => test2_top_kp_core_instance6_N7228
    );
  test2_top_kp_core_instance6_N226_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N226_CYMUXG,
      O => test2_top_kp_core_instance6_N7231
    );
  test2_top_kp_core_instance6_N226_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N226_XORF,
      O => test2_top_kp_core_instance6_N226
    );
  test2_top_kp_core_instance6_N226_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N226_XORG,
      O => test2_top_kp_core_instance6_N225
    );
  test2_top_kp_core_instance6_BU452 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N920,
      IB => test2_top_kp_core_instance6_N7226,
      SEL => test2_top_kp_core_instance6_N7228,
      O => test2_top_kp_core_instance6_N226_CYMUXG
    );
  test2_top_kp_core_instance6_BU453 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N7226,
      I1 => test2_top_kp_core_instance6_N7228,
      O => test2_top_kp_core_instance6_N226_XORG
    );
  test2_top_kp_core_instance6_N226_CYINIT_81 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N7221,
      O => test2_top_kp_core_instance6_N226_CYINIT
    );
  test2_top_kp_core_instance6_BU117 : X_LUT4
    generic map(
      INIT => X"00FE"
    )
    port map (
      ADR0 => test2_top_s_x_1(5),
      ADR1 => test2_top_s_x_1(7),
      ADR2 => test2_top_s_x_1(6),
      ADR3 => test2_top_s_x_1(4),
      O => test2_top_kp_core_instance6_N1698_FROM
    );
  test2_top_kp_core_instance6_BU113 : X_LUT4
    generic map(
      INIT => X"0F1E"
    )
    port map (
      ADR0 => test2_top_s_x_1(4),
      ADR1 => test2_top_s_x_1(5),
      ADR2 => test2_top_s_x_1(7),
      ADR3 => test2_top_s_x_1(6),
      O => test2_top_kp_core_instance6_N1698_GROM
    );
  test2_top_kp_core_instance6_N1698_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1698_FROM,
      O => test2_top_kp_core_instance6_N1698
    );
  test2_top_kp_core_instance6_N1698_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1698_GROM,
      O => test2_top_kp_core_instance6_N1699
    );
  test2_top_kp_core_instance6_BU48 : X_LUT4
    generic map(
      INIT => X"3332"
    )
    port map (
      ADR0 => test2_top_s_x_1(3),
      ADR1 => test2_top_s_x_1(0),
      ADR2 => test2_top_s_x_1(2),
      ADR3 => test2_top_s_x_1(1),
      O => test2_top_kp_core_instance6_N1568_FROM
    );
  test2_top_kp_core_instance6_BU44 : X_LUT4
    generic map(
      INIT => X"0F1E"
    )
    port map (
      ADR0 => test2_top_s_x_1(1),
      ADR1 => test2_top_s_x_1(2),
      ADR2 => test2_top_s_x_1(3),
      ADR3 => test2_top_s_x_1(0),
      O => test2_top_kp_core_instance6_N1568_GROM
    );
  test2_top_kp_core_instance6_N1568_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1568_FROM,
      O => test2_top_kp_core_instance6_N1568
    );
  test2_top_kp_core_instance6_N1568_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1568_GROM,
      O => test2_top_kp_core_instance6_N235
    );
  test2_top_kp_core_instance6_BU318 : X_LUT4
    generic map(
      INIT => X"CC32"
    )
    port map (
      ADR0 => test2_top_s_x_1(14),
      ADR1 => test2_top_s_x_1(12),
      ADR2 => test2_top_s_x_1(13),
      ADR3 => test2_top_s_x_1(15),
      O => test2_top_kp_core_instance6_N2119_FROM
    );
  test2_top_kp_core_instance6_BU314 : X_LUT4
    generic map(
      INIT => X"01FE"
    )
    port map (
      ADR0 => test2_top_s_x_1(13),
      ADR1 => test2_top_s_x_1(14),
      ADR2 => test2_top_s_x_1(12),
      ADR3 => test2_top_s_x_1(15),
      O => test2_top_kp_core_instance6_N2119_GROM
    );
  test2_top_kp_core_instance6_N2119_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2119_FROM,
      O => test2_top_kp_core_instance6_N2119
    );
  test2_top_kp_core_instance6_N2119_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N2119_GROM,
      O => test2_top_kp_core_instance6_N2120
    );
  test2_top_kp_core_instance6_BU249 : X_LUT4
    generic map(
      INIT => X"3332"
    )
    port map (
      ADR0 => test2_top_s_x_1(10),
      ADR1 => test2_top_s_x_1(8),
      ADR2 => test2_top_s_x_1(11),
      ADR3 => test2_top_s_x_1(9),
      O => test2_top_kp_core_instance6_N1989_FROM
    );
  test2_top_kp_core_instance6_BU245 : X_LUT4
    generic map(
      INIT => X"0F1E"
    )
    port map (
      ADR0 => test2_top_s_x_1(10),
      ADR1 => test2_top_s_x_1(9),
      ADR2 => test2_top_s_x_1(11),
      ADR3 => test2_top_s_x_1(8),
      O => test2_top_kp_core_instance6_N1989_GROM
    );
  test2_top_kp_core_instance6_N1989_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1989_FROM,
      O => test2_top_kp_core_instance6_N1989
    );
  test2_top_kp_core_instance6_N1989_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1989_GROM,
      O => test2_top_kp_core_instance6_N1990
    );
  test2_top_kp_core_instance6_BU374 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1987,
      IB => test2_top_kp_core_instance6_N955_CYINIT,
      SEL => test2_top_kp_core_instance6_N6207,
      O => test2_top_kp_core_instance6_N6210
    );
  test2_top_kp_core_instance6_BU375 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N955_CYINIT,
      I1 => test2_top_kp_core_instance6_N6207,
      O => test2_top_kp_core_instance6_N955_XORF
    );
  test2_top_kp_core_instance6_BU373 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1987,
      ADR1 => VCC,
      ADR2 => test2_top_kp_core_instance6_N2121,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6207
    );
  test2_top_kp_core_instance6_BU377 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1986,
      ADR1 => test2_top_kp_core_instance6_N2120,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N6212
    );
  test2_top_kp_core_instance6_N955_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N955_CYMUXG,
      O => test2_top_kp_core_instance6_N6215
    );
  test2_top_kp_core_instance6_N955_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N955_XORF,
      O => test2_top_kp_core_instance6_N955
    );
  test2_top_kp_core_instance6_N955_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N955_XORG,
      O => test2_top_kp_core_instance6_N954
    );
  test2_top_kp_core_instance6_BU378 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1986,
      IB => test2_top_kp_core_instance6_N6210,
      SEL => test2_top_kp_core_instance6_N6212,
      O => test2_top_kp_core_instance6_N955_CYMUXG
    );
  test2_top_kp_core_instance6_BU379 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N6210,
      I1 => test2_top_kp_core_instance6_N6212,
      O => test2_top_kp_core_instance6_N955_XORG
    );
  test2_top_kp_core_instance6_N955_CYINIT_82 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N6205,
      O => test2_top_kp_core_instance6_N955_CYINIT
    );
  test2_top_kp_core_instance6_BU174 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1566,
      IB => test2_top_kp_core_instance6_N232_CYINIT,
      SEL => test2_top_kp_core_instance6_N5410,
      O => test2_top_kp_core_instance6_N5413
    );
  test2_top_kp_core_instance6_BU175 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N232_CYINIT,
      I1 => test2_top_kp_core_instance6_N5410,
      O => test2_top_kp_core_instance6_N232_XORF
    );
  test2_top_kp_core_instance6_BU173 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1566,
      ADR1 => test2_top_kp_core_instance6_N1700,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5410
    );
  test2_top_kp_core_instance6_BU177 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kp_core_instance6_N1565,
      ADR1 => test2_top_kp_core_instance6_N1699,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kp_core_instance6_N5415
    );
  test2_top_kp_core_instance6_N232_COUTUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N232_CYMUXG,
      O => test2_top_kp_core_instance6_N5418
    );
  test2_top_kp_core_instance6_N232_XUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N232_XORF,
      O => test2_top_kp_core_instance6_N232
    );
  test2_top_kp_core_instance6_N232_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N232_XORG,
      O => test2_top_kp_core_instance6_N231
    );
  test2_top_kp_core_instance6_BU178 : X_MUX2
    port map (
      IA => test2_top_kp_core_instance6_N1565,
      IB => test2_top_kp_core_instance6_N5413,
      SEL => test2_top_kp_core_instance6_N5415,
      O => test2_top_kp_core_instance6_N232_CYMUXG
    );
  test2_top_kp_core_instance6_BU179 : X_XOR2
    port map (
      I0 => test2_top_kp_core_instance6_N5413,
      I1 => test2_top_kp_core_instance6_N5415,
      O => test2_top_kp_core_instance6_N232_XORG
    );
  test2_top_kp_core_instance6_N232_CYINIT_83 : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N5408,
      O => test2_top_kp_core_instance6_N232_CYINIT
    );
  test2_top_kp_core_instance6_BU153 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => test2_top_s_x_1(6),
      ADR1 => test2_top_s_x_1(5),
      ADR2 => test2_top_s_x_1(4),
      ADR3 => test2_top_s_x_1(7),
      O => test2_top_kp_core_instance6_N1689_GROM
    );
  test2_top_kp_core_instance6_N1689_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1689_GROM,
      O => test2_top_kp_core_instance6_N1689
    );
  test2_top_kp_core_instance6_BU285 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => test2_top_s_x_1(11),
      ADR1 => test2_top_s_x_1(8),
      ADR2 => test2_top_s_x_1(10),
      ADR3 => test2_top_s_x_1(9),
      O => test2_top_kp_core_instance6_N1980_GROM
    );
  test2_top_kp_core_instance6_N1980_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1980_GROM,
      O => test2_top_kp_core_instance6_N1980
    );
  test2_top_kp_core_instance6_BU84 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => test2_top_s_x_1(2),
      ADR1 => test2_top_s_x_1(3),
      ADR2 => test2_top_s_x_1(0),
      ADR3 => test2_top_s_x_1(1),
      O => test2_top_kp_core_instance6_N1559_GROM
    );
  test2_top_kp_core_instance6_N1559_YUSED : X_BUF
    port map (
      I => test2_top_kp_core_instance6_N1559_GROM,
      O => test2_top_kp_core_instance6_N1559
    );
  test2_top_addsub3_core_instance4_BU52 : X_MUX2
    port map (
      IA => gateway_in1_12_IBUF,
      IB => test2_top_s_x_1_12_CYINIT,
      SEL => test2_top_addsub3_core_instance4_N62,
      O => test2_top_addsub3_core_instance4_N65
    );
  test2_top_addsub3_core_instance4_BU53 : X_XOR2
    port map (
      I0 => test2_top_s_x_1_12_CYINIT,
      I1 => test2_top_addsub3_core_instance4_N62,
      O => test2_top_s_x_1_12_XORF
    );
  test2_top_addsub3_core_instance4_BU51 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => gateway_in1_12_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(12),
      O => test2_top_addsub3_core_instance4_N62
    );
  test2_top_addsub3_core_instance4_BU55 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => gateway_in1_13_IBUF,
      ADR1 => test2_top_q(13),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N67
    );
  test2_top_s_x_1_12_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_1_12_CYMUXG,
      O => test2_top_addsub3_core_instance4_N70
    );
  test2_top_s_x_1_12_XUSED : X_BUF
    port map (
      I => test2_top_s_x_1_12_XORF,
      O => test2_top_s_x_1(12)
    );
  test2_top_s_x_1_12_YUSED : X_BUF
    port map (
      I => test2_top_s_x_1_12_XORG,
      O => test2_top_s_x_1(13)
    );
  test2_top_addsub3_core_instance4_BU56 : X_MUX2
    port map (
      IA => gateway_in1_13_IBUF,
      IB => test2_top_addsub3_core_instance4_N65,
      SEL => test2_top_addsub3_core_instance4_N67,
      O => test2_top_s_x_1_12_CYMUXG
    );
  test2_top_addsub3_core_instance4_BU57 : X_XOR2
    port map (
      I0 => test2_top_addsub3_core_instance4_N65,
      I1 => test2_top_addsub3_core_instance4_N67,
      O => test2_top_s_x_1_12_XORG
    );
  test2_top_s_x_1_12_CYINIT_84 : X_BUF
    port map (
      I => test2_top_addsub3_core_instance4_N60,
      O => test2_top_s_x_1_12_CYINIT
    );
  test2_top_addsub3_core_instance4_BU44 : X_MUX2
    port map (
      IA => gateway_in1_10_IBUF,
      IB => test2_top_s_x_1_10_CYINIT,
      SEL => test2_top_addsub3_core_instance4_N52,
      O => test2_top_addsub3_core_instance4_N55
    );
  test2_top_addsub3_core_instance4_BU45 : X_XOR2
    port map (
      I0 => test2_top_s_x_1_10_CYINIT,
      I1 => test2_top_addsub3_core_instance4_N52,
      O => test2_top_s_x_1_10_XORF
    );
  test2_top_addsub3_core_instance4_BU43 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => gateway_in1_10_IBUF,
      ADR1 => test2_top_q(10),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N52
    );
  test2_top_addsub3_core_instance4_BU47 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => gateway_in1_11_IBUF,
      ADR1 => test2_top_q(11),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N57
    );
  test2_top_s_x_1_10_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_1_10_CYMUXG,
      O => test2_top_addsub3_core_instance4_N60
    );
  test2_top_s_x_1_10_XUSED : X_BUF
    port map (
      I => test2_top_s_x_1_10_XORF,
      O => test2_top_s_x_1(10)
    );
  test2_top_s_x_1_10_YUSED : X_BUF
    port map (
      I => test2_top_s_x_1_10_XORG,
      O => test2_top_s_x_1(11)
    );
  test2_top_addsub3_core_instance4_BU48 : X_MUX2
    port map (
      IA => gateway_in1_11_IBUF,
      IB => test2_top_addsub3_core_instance4_N55,
      SEL => test2_top_addsub3_core_instance4_N57,
      O => test2_top_s_x_1_10_CYMUXG
    );
  test2_top_addsub3_core_instance4_BU49 : X_XOR2
    port map (
      I0 => test2_top_addsub3_core_instance4_N55,
      I1 => test2_top_addsub3_core_instance4_N57,
      O => test2_top_s_x_1_10_XORG
    );
  test2_top_s_x_1_10_CYINIT_85 : X_BUF
    port map (
      I => test2_top_addsub3_core_instance4_N50,
      O => test2_top_s_x_1_10_CYINIT
    );
  test2_top_addsub3_core_instance4_BU36 : X_MUX2
    port map (
      IA => gateway_in1_8_IBUF,
      IB => test2_top_s_x_1_8_CYINIT,
      SEL => test2_top_addsub3_core_instance4_N42,
      O => test2_top_addsub3_core_instance4_N45
    );
  test2_top_addsub3_core_instance4_BU37 : X_XOR2
    port map (
      I0 => test2_top_s_x_1_8_CYINIT,
      I1 => test2_top_addsub3_core_instance4_N42,
      O => test2_top_s_x_1_8_XORF
    );
  test2_top_addsub3_core_instance4_BU35 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => gateway_in1_8_IBUF,
      ADR1 => test2_top_q(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N42
    );
  test2_top_addsub3_core_instance4_BU39 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => gateway_in1_9_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(9),
      O => test2_top_addsub3_core_instance4_N47
    );
  test2_top_s_x_1_8_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_1_8_CYMUXG,
      O => test2_top_addsub3_core_instance4_N50
    );
  test2_top_s_x_1_8_XUSED : X_BUF
    port map (
      I => test2_top_s_x_1_8_XORF,
      O => test2_top_s_x_1(8)
    );
  test2_top_s_x_1_8_YUSED : X_BUF
    port map (
      I => test2_top_s_x_1_8_XORG,
      O => test2_top_s_x_1(9)
    );
  test2_top_addsub3_core_instance4_BU40 : X_MUX2
    port map (
      IA => gateway_in1_9_IBUF,
      IB => test2_top_addsub3_core_instance4_N45,
      SEL => test2_top_addsub3_core_instance4_N47,
      O => test2_top_s_x_1_8_CYMUXG
    );
  test2_top_addsub3_core_instance4_BU41 : X_XOR2
    port map (
      I0 => test2_top_addsub3_core_instance4_N45,
      I1 => test2_top_addsub3_core_instance4_N47,
      O => test2_top_s_x_1_8_XORG
    );
  test2_top_s_x_1_8_CYINIT_86 : X_BUF
    port map (
      I => test2_top_addsub3_core_instance4_N40,
      O => test2_top_s_x_1_8_CYINIT
    );
  test2_top_addsub3_core_instance4_BU28 : X_MUX2
    port map (
      IA => gateway_in1_6_IBUF,
      IB => test2_top_s_x_1_6_CYINIT,
      SEL => test2_top_addsub3_core_instance4_N32,
      O => test2_top_addsub3_core_instance4_N35
    );
  test2_top_addsub3_core_instance4_BU29 : X_XOR2
    port map (
      I0 => test2_top_s_x_1_6_CYINIT,
      I1 => test2_top_addsub3_core_instance4_N32,
      O => test2_top_s_x_1_6_XORF
    );
  test2_top_addsub3_core_instance4_BU27 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => gateway_in1_6_IBUF,
      ADR1 => test2_top_q(6),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N32
    );
  test2_top_addsub3_core_instance4_BU31 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => gateway_in1_7_IBUF,
      ADR1 => VCC,
      ADR2 => test2_top_q(7),
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N37
    );
  test2_top_s_x_1_6_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_1_6_CYMUXG,
      O => test2_top_addsub3_core_instance4_N40
    );
  test2_top_s_x_1_6_XUSED : X_BUF
    port map (
      I => test2_top_s_x_1_6_XORF,
      O => test2_top_s_x_1(6)
    );
  test2_top_s_x_1_6_YUSED : X_BUF
    port map (
      I => test2_top_s_x_1_6_XORG,
      O => test2_top_s_x_1(7)
    );
  test2_top_addsub3_core_instance4_BU32 : X_MUX2
    port map (
      IA => gateway_in1_7_IBUF,
      IB => test2_top_addsub3_core_instance4_N35,
      SEL => test2_top_addsub3_core_instance4_N37,
      O => test2_top_s_x_1_6_CYMUXG
    );
  test2_top_addsub3_core_instance4_BU33 : X_XOR2
    port map (
      I0 => test2_top_addsub3_core_instance4_N35,
      I1 => test2_top_addsub3_core_instance4_N37,
      O => test2_top_s_x_1_6_XORG
    );
  test2_top_s_x_1_6_CYINIT_87 : X_BUF
    port map (
      I => test2_top_addsub3_core_instance4_N30,
      O => test2_top_s_x_1_6_CYINIT
    );
  test2_top_addsub3_core_instance4_BU20 : X_MUX2
    port map (
      IA => gateway_in1_4_IBUF,
      IB => test2_top_s_x_1_4_CYINIT,
      SEL => test2_top_addsub3_core_instance4_N22,
      O => test2_top_addsub3_core_instance4_N25
    );
  test2_top_addsub3_core_instance4_BU21 : X_XOR2
    port map (
      I0 => test2_top_s_x_1_4_CYINIT,
      I1 => test2_top_addsub3_core_instance4_N22,
      O => test2_top_s_x_1_4_XORF
    );
  test2_top_addsub3_core_instance4_BU19 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => gateway_in1_4_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(4),
      O => test2_top_addsub3_core_instance4_N22
    );
  test2_top_addsub3_core_instance4_BU23 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => gateway_in1_5_IBUF,
      ADR1 => VCC,
      ADR2 => test2_top_q(5),
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N27
    );
  test2_top_s_x_1_4_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_1_4_CYMUXG,
      O => test2_top_addsub3_core_instance4_N30
    );
  test2_top_s_x_1_4_XUSED : X_BUF
    port map (
      I => test2_top_s_x_1_4_XORF,
      O => test2_top_s_x_1(4)
    );
  test2_top_s_x_1_4_YUSED : X_BUF
    port map (
      I => test2_top_s_x_1_4_XORG,
      O => test2_top_s_x_1(5)
    );
  test2_top_addsub3_core_instance4_BU24 : X_MUX2
    port map (
      IA => gateway_in1_5_IBUF,
      IB => test2_top_addsub3_core_instance4_N25,
      SEL => test2_top_addsub3_core_instance4_N27,
      O => test2_top_s_x_1_4_CYMUXG
    );
  test2_top_addsub3_core_instance4_BU25 : X_XOR2
    port map (
      I0 => test2_top_addsub3_core_instance4_N25,
      I1 => test2_top_addsub3_core_instance4_N27,
      O => test2_top_s_x_1_4_XORG
    );
  test2_top_s_x_1_4_CYINIT_88 : X_BUF
    port map (
      I => test2_top_addsub3_core_instance4_N20,
      O => test2_top_s_x_1_4_CYINIT
    );
  test2_top_addsub3_core_instance4_BU12 : X_MUX2
    port map (
      IA => gateway_in1_2_IBUF,
      IB => test2_top_s_x_1_2_CYINIT,
      SEL => test2_top_addsub3_core_instance4_N12,
      O => test2_top_addsub3_core_instance4_N15
    );
  test2_top_addsub3_core_instance4_BU13 : X_XOR2
    port map (
      I0 => test2_top_s_x_1_2_CYINIT,
      I1 => test2_top_addsub3_core_instance4_N12,
      O => test2_top_s_x_1_2_XORF
    );
  test2_top_addsub3_core_instance4_BU11 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => gateway_in1_2_IBUF,
      ADR1 => test2_top_q(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N12
    );
  test2_top_addsub3_core_instance4_BU15 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => gateway_in1_3_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(3),
      O => test2_top_addsub3_core_instance4_N17
    );
  test2_top_s_x_1_2_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_1_2_CYMUXG,
      O => test2_top_addsub3_core_instance4_N20
    );
  test2_top_s_x_1_2_XUSED : X_BUF
    port map (
      I => test2_top_s_x_1_2_XORF,
      O => test2_top_s_x_1(2)
    );
  test2_top_s_x_1_2_YUSED : X_BUF
    port map (
      I => test2_top_s_x_1_2_XORG,
      O => test2_top_s_x_1(3)
    );
  test2_top_addsub3_core_instance4_BU16 : X_MUX2
    port map (
      IA => gateway_in1_3_IBUF,
      IB => test2_top_addsub3_core_instance4_N15,
      SEL => test2_top_addsub3_core_instance4_N17,
      O => test2_top_s_x_1_2_CYMUXG
    );
  test2_top_addsub3_core_instance4_BU17 : X_XOR2
    port map (
      I0 => test2_top_addsub3_core_instance4_N15,
      I1 => test2_top_addsub3_core_instance4_N17,
      O => test2_top_s_x_1_2_XORG
    );
  test2_top_s_x_1_2_CYINIT_89 : X_BUF
    port map (
      I => test2_top_addsub3_core_instance4_N10,
      O => test2_top_s_x_1_2_CYINIT
    );
  test2_top_s_x_1_0_LOGIC_ONE_90 : X_ONE
    port map (
      O => test2_top_s_x_1_0_LOGIC_ONE
    );
  test2_top_addsub3_core_instance4_BU4 : X_MUX2
    port map (
      IA => gateway_in1_0_IBUF,
      IB => test2_top_s_x_1_0_CYINIT,
      SEL => test2_top_addsub3_core_instance4_N2,
      O => test2_top_addsub3_core_instance4_N5
    );
  test2_top_addsub3_core_instance4_BU5 : X_XOR2
    port map (
      I0 => test2_top_s_x_1_0_CYINIT,
      I1 => test2_top_addsub3_core_instance4_N2,
      O => test2_top_s_x_1_0_XORF
    );
  test2_top_addsub3_core_instance4_BU3 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => gateway_in1_0_IBUF,
      ADR1 => VCC,
      ADR2 => test2_top_q(0),
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N2
    );
  test2_top_addsub3_core_instance4_BU7 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => gateway_in1_1_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(1),
      O => test2_top_addsub3_core_instance4_N7
    );
  test2_top_s_x_1_0_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_1_0_CYMUXG,
      O => test2_top_addsub3_core_instance4_N10
    );
  test2_top_s_x_1_0_XUSED : X_BUF
    port map (
      I => test2_top_s_x_1_0_XORF,
      O => test2_top_s_x_1(0)
    );
  test2_top_s_x_1_0_YUSED : X_BUF
    port map (
      I => test2_top_s_x_1_0_XORG,
      O => test2_top_s_x_1(1)
    );
  test2_top_addsub3_core_instance4_BU8 : X_MUX2
    port map (
      IA => gateway_in1_1_IBUF,
      IB => test2_top_addsub3_core_instance4_N5,
      SEL => test2_top_addsub3_core_instance4_N7,
      O => test2_top_s_x_1_0_CYMUXG
    );
  test2_top_addsub3_core_instance4_BU9 : X_XOR2
    port map (
      I0 => test2_top_addsub3_core_instance4_N5,
      I1 => test2_top_addsub3_core_instance4_N7,
      O => test2_top_s_x_1_0_XORG
    );
  test2_top_s_x_1_0_CYINIT_91 : X_BUF
    port map (
      I => test2_top_s_x_1_0_LOGIC_ONE,
      O => test2_top_s_x_1_0_CYINIT
    );
  test2_top_addsub3_core_instance4_BU60 : X_MUX2
    port map (
      IA => gateway_in1_14_IBUF,
      IB => test2_top_s_x_1_14_CYINIT,
      SEL => test2_top_addsub3_core_instance4_N72,
      O => test2_top_addsub3_core_instance4_N75
    );
  test2_top_addsub3_core_instance4_BU61 : X_XOR2
    port map (
      I0 => test2_top_s_x_1_14_CYINIT,
      I1 => test2_top_addsub3_core_instance4_N72,
      O => test2_top_s_x_1_14_XORF
    );
  test2_top_addsub3_core_instance4_BU59 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => gateway_in1_14_IBUF,
      ADR1 => test2_top_q(14),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N72
    );
  test2_top_addsub3_core_instance4_BU63 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => gateway_in1_15_IBUF,
      ADR1 => VCC,
      ADR2 => test2_top_q(15),
      ADR3 => VCC,
      O => test2_top_addsub3_core_instance4_N77
    );
  test2_top_s_x_1_14_XUSED : X_BUF
    port map (
      I => test2_top_s_x_1_14_XORF,
      O => test2_top_s_x_1(14)
    );
  test2_top_s_x_1_14_YUSED : X_BUF
    port map (
      I => test2_top_s_x_1_14_XORG,
      O => test2_top_s_x_1(15)
    );
  test2_top_addsub3_core_instance4_BU65 : X_XOR2
    port map (
      I0 => test2_top_addsub3_core_instance4_N75,
      I1 => test2_top_addsub3_core_instance4_N77,
      O => test2_top_s_x_1_14_XORG
    );
  test2_top_s_x_1_14_CYINIT_92 : X_BUF
    port map (
      I => test2_top_addsub3_core_instance4_N70,
      O => test2_top_s_x_1_14_CYINIT
    );
  test2_top_addsub1_core_instance0_BU52 : X_MUX2
    port map (
      IA => test2_top_q_x_1(4),
      IB => test2_top_s_4_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N62,
      O => test2_top_addsub1_core_instance0_N65
    );
  test2_top_addsub1_core_instance0_BU53 : X_XOR2
    port map (
      I0 => test2_top_s_4_CYINIT,
      I1 => test2_top_addsub1_core_instance0_N62,
      O => test2_top_s_4_XORF
    );
  test2_top_addsub1_core_instance0_BU51 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => test2_top_q_x_1(4),
      ADR1 => test2_top_q(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub1_core_instance0_N62
    );
  test2_top_addsub1_core_instance0_BU55 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => test2_top_q_x_1(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(4),
      O => test2_top_addsub1_core_instance0_N67
    );
  test2_top_s_4_COUTUSED : X_BUF
    port map (
      I => test2_top_s_4_CYMUXG,
      O => test2_top_addsub1_core_instance0_N70
    );
  test2_top_s_4_XUSED : X_BUF
    port map (
      I => test2_top_s_4_XORF,
      O => test2_top_s(4)
    );
  test2_top_s_4_YUSED : X_BUF
    port map (
      I => test2_top_s_4_XORG,
      O => test2_top_s(5)
    );
  test2_top_addsub1_core_instance0_BU56 : X_MUX2
    port map (
      IA => test2_top_q_x_1(5),
      IB => test2_top_addsub1_core_instance0_N65,
      SEL => test2_top_addsub1_core_instance0_N67,
      O => test2_top_s_4_CYMUXG
    );
  test2_top_addsub1_core_instance0_BU57 : X_XOR2
    port map (
      I0 => test2_top_addsub1_core_instance0_N65,
      I1 => test2_top_addsub1_core_instance0_N67,
      O => test2_top_s_4_XORG
    );
  test2_top_s_4_CYINIT_93 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N60,
      O => test2_top_s_4_CYINIT
    );
  test2_top_addsub1_core_instance0_BU92 : X_MUX2
    port map (
      IA => test2_top_q_x_1(14),
      IB => test2_top_s_14_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N112,
      O => test2_top_addsub1_core_instance0_N115
    );
  test2_top_addsub1_core_instance0_BU93 : X_XOR2
    port map (
      I0 => test2_top_s_14_CYINIT,
      I1 => test2_top_addsub1_core_instance0_N112,
      O => test2_top_s_14_XORF
    );
  test2_top_addsub1_core_instance0_BU91 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => test2_top_q_x_1(14),
      ADR1 => VCC,
      ADR2 => test2_top_q(13),
      ADR3 => VCC,
      O => test2_top_addsub1_core_instance0_N112
    );
  test2_top_addsub1_core_instance0_BU95 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => test2_top_q_x_1(15),
      ADR1 => test2_top_q(14),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub1_core_instance0_N117
    );
  test2_top_s_14_XUSED : X_BUF
    port map (
      I => test2_top_s_14_XORF,
      O => test2_top_s(14)
    );
  test2_top_s_14_YUSED : X_BUF
    port map (
      I => test2_top_s_14_XORG,
      O => test2_top_s(15)
    );
  test2_top_addsub1_core_instance0_BU97 : X_XOR2
    port map (
      I0 => test2_top_addsub1_core_instance0_N115,
      I1 => test2_top_addsub1_core_instance0_N117,
      O => test2_top_s_14_XORG
    );
  test2_top_s_14_CYINIT_94 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N110,
      O => test2_top_s_14_CYINIT
    );
  test2_top_addsub1_core_instance0_BU44 : X_MUX2
    port map (
      IA => test2_top_q_x_1(2),
      IB => test2_top_s_2_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N52,
      O => test2_top_addsub1_core_instance0_N55
    );
  test2_top_addsub1_core_instance0_BU45 : X_XOR2
    port map (
      I0 => test2_top_s_2_CYINIT,
      I1 => test2_top_addsub1_core_instance0_N52,
      O => test2_top_s_2_XORF
    );
  test2_top_addsub1_core_instance0_BU43 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => test2_top_q_x_1(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(1),
      O => test2_top_addsub1_core_instance0_N52
    );
  test2_top_addsub1_core_instance0_BU47 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => test2_top_q_x_1(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(2),
      O => test2_top_addsub1_core_instance0_N57
    );
  test2_top_s_2_COUTUSED : X_BUF
    port map (
      I => test2_top_s_2_CYMUXG,
      O => test2_top_addsub1_core_instance0_N60
    );
  test2_top_s_2_XUSED : X_BUF
    port map (
      I => test2_top_s_2_XORF,
      O => test2_top_s(2)
    );
  test2_top_s_2_YUSED : X_BUF
    port map (
      I => test2_top_s_2_XORG,
      O => test2_top_s(3)
    );
  test2_top_addsub1_core_instance0_BU48 : X_MUX2
    port map (
      IA => test2_top_q_x_1(3),
      IB => test2_top_addsub1_core_instance0_N55,
      SEL => test2_top_addsub1_core_instance0_N57,
      O => test2_top_s_2_CYMUXG
    );
  test2_top_addsub1_core_instance0_BU49 : X_XOR2
    port map (
      I0 => test2_top_addsub1_core_instance0_N55,
      I1 => test2_top_addsub1_core_instance0_N57,
      O => test2_top_s_2_XORG
    );
  test2_top_s_2_CYINIT_95 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N50,
      O => test2_top_s_2_CYINIT
    );
  test2_top_addsub1_core_instance0_BU84 : X_MUX2
    port map (
      IA => test2_top_q_x_1(12),
      IB => test2_top_s_12_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N102,
      O => test2_top_addsub1_core_instance0_N105
    );
  test2_top_addsub1_core_instance0_BU85 : X_XOR2
    port map (
      I0 => test2_top_s_12_CYINIT,
      I1 => test2_top_addsub1_core_instance0_N102,
      O => test2_top_s_12_XORF
    );
  test2_top_addsub1_core_instance0_BU83 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => test2_top_q_x_1(12),
      ADR1 => VCC,
      ADR2 => test2_top_q(11),
      ADR3 => VCC,
      O => test2_top_addsub1_core_instance0_N102
    );
  test2_top_addsub1_core_instance0_BU87 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => test2_top_q_x_1(13),
      ADR1 => test2_top_q(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub1_core_instance0_N107
    );
  test2_top_s_12_COUTUSED : X_BUF
    port map (
      I => test2_top_s_12_CYMUXG,
      O => test2_top_addsub1_core_instance0_N110
    );
  test2_top_s_12_XUSED : X_BUF
    port map (
      I => test2_top_s_12_XORF,
      O => test2_top_s(12)
    );
  test2_top_s_12_YUSED : X_BUF
    port map (
      I => test2_top_s_12_XORG,
      O => test2_top_s(13)
    );
  test2_top_addsub1_core_instance0_BU88 : X_MUX2
    port map (
      IA => test2_top_q_x_1(13),
      IB => test2_top_addsub1_core_instance0_N105,
      SEL => test2_top_addsub1_core_instance0_N107,
      O => test2_top_s_12_CYMUXG
    );
  test2_top_addsub1_core_instance0_BU89 : X_XOR2
    port map (
      I0 => test2_top_addsub1_core_instance0_N105,
      I1 => test2_top_addsub1_core_instance0_N107,
      O => test2_top_s_12_XORG
    );
  test2_top_s_12_CYINIT_96 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N100,
      O => test2_top_s_12_CYINIT
    );
  test2_top_addsub1_core_instance0_BU36 : X_MUX2
    port map (
      IA => test2_top_q_x_1(0),
      IB => test2_top_s_0_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N42,
      O => test2_top_addsub1_core_instance0_N45
    );
  test2_top_addsub1_core_instance0_BU37 : X_XOR2
    port map (
      I0 => test2_top_s_0_CYINIT,
      I1 => test2_top_addsub1_core_instance0_N42,
      O => test2_top_s_0_XORF
    );
  test2_top_addsub1_core_instance0_BU35 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => test2_top_q_x_1(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub1_core_instance0_N42
    );
  test2_top_addsub1_core_instance0_BU39 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => test2_top_q_x_1(1),
      ADR1 => test2_top_q(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub1_core_instance0_N47
    );
  test2_top_s_0_COUTUSED : X_BUF
    port map (
      I => test2_top_s_0_CYMUXG,
      O => test2_top_addsub1_core_instance0_N50
    );
  test2_top_s_0_XUSED : X_BUF
    port map (
      I => test2_top_s_0_XORF,
      O => test2_top_s(0)
    );
  test2_top_s_0_YUSED : X_BUF
    port map (
      I => test2_top_s_0_XORG,
      O => test2_top_s(1)
    );
  test2_top_addsub1_core_instance0_BU40 : X_MUX2
    port map (
      IA => test2_top_q_x_1(1),
      IB => test2_top_addsub1_core_instance0_N45,
      SEL => test2_top_addsub1_core_instance0_N47,
      O => test2_top_s_0_CYMUXG
    );
  test2_top_addsub1_core_instance0_BU41 : X_XOR2
    port map (
      I0 => test2_top_addsub1_core_instance0_N45,
      I1 => test2_top_addsub1_core_instance0_N47,
      O => test2_top_s_0_XORG
    );
  test2_top_s_0_CYINIT_97 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N40,
      O => test2_top_s_0_CYINIT
    );
  test2_top_addsub1_core_instance0_BU76 : X_MUX2
    port map (
      IA => test2_top_q_x_1(10),
      IB => test2_top_s_10_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N92,
      O => test2_top_addsub1_core_instance0_N95
    );
  test2_top_addsub1_core_instance0_BU77 : X_XOR2
    port map (
      I0 => test2_top_s_10_CYINIT,
      I1 => test2_top_addsub1_core_instance0_N92,
      O => test2_top_s_10_XORF
    );
  test2_top_addsub1_core_instance0_BU75 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => test2_top_q_x_1(10),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(9),
      O => test2_top_addsub1_core_instance0_N92
    );
  test2_top_addsub1_core_instance0_BU79 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => test2_top_q_x_1(11),
      ADR1 => VCC,
      ADR2 => test2_top_q(10),
      ADR3 => VCC,
      O => test2_top_addsub1_core_instance0_N97
    );
  test2_top_s_10_COUTUSED : X_BUF
    port map (
      I => test2_top_s_10_CYMUXG,
      O => test2_top_addsub1_core_instance0_N100
    );
  test2_top_s_10_XUSED : X_BUF
    port map (
      I => test2_top_s_10_XORF,
      O => test2_top_s(10)
    );
  test2_top_s_10_YUSED : X_BUF
    port map (
      I => test2_top_s_10_XORG,
      O => test2_top_s(11)
    );
  test2_top_addsub1_core_instance0_BU80 : X_MUX2
    port map (
      IA => test2_top_q_x_1(11),
      IB => test2_top_addsub1_core_instance0_N95,
      SEL => test2_top_addsub1_core_instance0_N97,
      O => test2_top_s_10_CYMUXG
    );
  test2_top_addsub1_core_instance0_BU81 : X_XOR2
    port map (
      I0 => test2_top_addsub1_core_instance0_N95,
      I1 => test2_top_addsub1_core_instance0_N97,
      O => test2_top_s_10_XORG
    );
  test2_top_s_10_CYINIT_98 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N90,
      O => test2_top_s_10_CYINIT
    );
  test2_top_addsub1_core_instance0_N40_LOGIC_ONE_99 : X_ONE
    port map (
      O => test2_top_addsub1_core_instance0_N40_LOGIC_ONE
    );
  test2_top_addsub1_core_instance0_BU28 : X_MUX2
    port map (
      IA => NLW_test2_top_addsub1_core_instance0_BU28_IA_UNCONNECTED,
      IB => test2_top_addsub1_core_instance0_N40_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N40_LOGIC_ONE,
      O => test2_top_addsub1_core_instance0_N35
    );
  test2_top_addsub1_core_instance0_N40_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N40_CYMUXG,
      O => test2_top_addsub1_core_instance0_N40
    );
  test2_top_addsub1_core_instance0_BU32 : X_MUX2
    port map (
      IA => NLW_test2_top_addsub1_core_instance0_BU32_IA_UNCONNECTED,
      IB => test2_top_addsub1_core_instance0_N35,
      SEL => test2_top_addsub1_core_instance0_N40_LOGIC_ONE,
      O => test2_top_addsub1_core_instance0_N40_CYMUXG
    );
  test2_top_addsub1_core_instance0_N40_CYINIT_100 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N30,
      O => test2_top_addsub1_core_instance0_N40_CYINIT
    );
  test2_top_addsub1_core_instance0_BU68 : X_MUX2
    port map (
      IA => test2_top_q_x_1(8),
      IB => test2_top_s_8_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N82,
      O => test2_top_addsub1_core_instance0_N85
    );
  test2_top_addsub1_core_instance0_BU69 : X_XOR2
    port map (
      I0 => test2_top_s_8_CYINIT,
      I1 => test2_top_addsub1_core_instance0_N82,
      O => test2_top_s_8_XORF
    );
  test2_top_addsub1_core_instance0_BU67 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => test2_top_q_x_1(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(7),
      O => test2_top_addsub1_core_instance0_N82
    );
  test2_top_addsub1_core_instance0_BU71 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => test2_top_q_x_1(9),
      ADR1 => VCC,
      ADR2 => test2_top_q(8),
      ADR3 => VCC,
      O => test2_top_addsub1_core_instance0_N87
    );
  test2_top_s_8_COUTUSED : X_BUF
    port map (
      I => test2_top_s_8_CYMUXG,
      O => test2_top_addsub1_core_instance0_N90
    );
  test2_top_s_8_XUSED : X_BUF
    port map (
      I => test2_top_s_8_XORF,
      O => test2_top_s(8)
    );
  test2_top_s_8_YUSED : X_BUF
    port map (
      I => test2_top_s_8_XORG,
      O => test2_top_s(9)
    );
  test2_top_addsub1_core_instance0_BU72 : X_MUX2
    port map (
      IA => test2_top_q_x_1(9),
      IB => test2_top_addsub1_core_instance0_N85,
      SEL => test2_top_addsub1_core_instance0_N87,
      O => test2_top_s_8_CYMUXG
    );
  test2_top_addsub1_core_instance0_BU73 : X_XOR2
    port map (
      I0 => test2_top_addsub1_core_instance0_N85,
      I1 => test2_top_addsub1_core_instance0_N87,
      O => test2_top_s_8_XORG
    );
  test2_top_s_8_CYINIT_101 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N80,
      O => test2_top_s_8_CYINIT
    );
  test2_top_addsub1_core_instance0_N30_LOGIC_ONE_102 : X_ONE
    port map (
      O => test2_top_addsub1_core_instance0_N30_LOGIC_ONE
    );
  test2_top_addsub1_core_instance0_BU20 : X_MUX2
    port map (
      IA => NLW_test2_top_addsub1_core_instance0_BU20_IA_UNCONNECTED,
      IB => test2_top_addsub1_core_instance0_N30_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N30_LOGIC_ONE,
      O => test2_top_addsub1_core_instance0_N25
    );
  test2_top_addsub1_core_instance0_N30_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N30_CYMUXG,
      O => test2_top_addsub1_core_instance0_N30
    );
  test2_top_addsub1_core_instance0_BU24 : X_MUX2
    port map (
      IA => NLW_test2_top_addsub1_core_instance0_BU24_IA_UNCONNECTED,
      IB => test2_top_addsub1_core_instance0_N25,
      SEL => test2_top_addsub1_core_instance0_N30_LOGIC_ONE,
      O => test2_top_addsub1_core_instance0_N30_CYMUXG
    );
  test2_top_addsub1_core_instance0_N30_CYINIT_103 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N20,
      O => test2_top_addsub1_core_instance0_N30_CYINIT
    );
  test2_top_addsub1_core_instance0_BU60 : X_MUX2
    port map (
      IA => test2_top_q_x_1(6),
      IB => test2_top_s_6_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N72,
      O => test2_top_addsub1_core_instance0_N75
    );
  test2_top_addsub1_core_instance0_BU61 : X_XOR2
    port map (
      I0 => test2_top_s_6_CYINIT,
      I1 => test2_top_addsub1_core_instance0_N72,
      O => test2_top_s_6_XORF
    );
  test2_top_addsub1_core_instance0_BU59 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => test2_top_q_x_1(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q(5),
      O => test2_top_addsub1_core_instance0_N72
    );
  test2_top_addsub1_core_instance0_BU63 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => test2_top_q_x_1(7),
      ADR1 => test2_top_q(6),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub1_core_instance0_N77
    );
  test2_top_s_6_COUTUSED : X_BUF
    port map (
      I => test2_top_s_6_CYMUXG,
      O => test2_top_addsub1_core_instance0_N80
    );
  test2_top_s_6_XUSED : X_BUF
    port map (
      I => test2_top_s_6_XORF,
      O => test2_top_s(6)
    );
  test2_top_s_6_YUSED : X_BUF
    port map (
      I => test2_top_s_6_XORG,
      O => test2_top_s(7)
    );
  test2_top_addsub1_core_instance0_BU64 : X_MUX2
    port map (
      IA => test2_top_q_x_1(7),
      IB => test2_top_addsub1_core_instance0_N75,
      SEL => test2_top_addsub1_core_instance0_N77,
      O => test2_top_s_6_CYMUXG
    );
  test2_top_addsub1_core_instance0_BU65 : X_XOR2
    port map (
      I0 => test2_top_addsub1_core_instance0_N75,
      I1 => test2_top_addsub1_core_instance0_N77,
      O => test2_top_s_6_XORG
    );
  test2_top_s_6_CYINIT_104 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N70,
      O => test2_top_s_6_CYINIT
    );
  test2_top_addsub1_core_instance0_N20_LOGIC_ONE_105 : X_ONE
    port map (
      O => test2_top_addsub1_core_instance0_N20_LOGIC_ONE
    );
  test2_top_addsub1_core_instance0_BU12 : X_MUX2
    port map (
      IA => NLW_test2_top_addsub1_core_instance0_BU12_IA_UNCONNECTED,
      IB => test2_top_addsub1_core_instance0_N20_CYINIT,
      SEL => test2_top_addsub1_core_instance0_N20_LOGIC_ONE,
      O => test2_top_addsub1_core_instance0_N15
    );
  test2_top_addsub1_core_instance0_N20_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N20_CYMUXG,
      O => test2_top_addsub1_core_instance0_N20
    );
  test2_top_addsub1_core_instance0_BU16 : X_MUX2
    port map (
      IA => NLW_test2_top_addsub1_core_instance0_BU16_IA_UNCONNECTED,
      IB => test2_top_addsub1_core_instance0_N15,
      SEL => test2_top_addsub1_core_instance0_N20_LOGIC_ONE,
      O => test2_top_addsub1_core_instance0_N20_CYMUXG
    );
  test2_top_addsub1_core_instance0_N20_CYINIT_106 : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N10,
      O => test2_top_addsub1_core_instance0_N20_CYINIT
    );
  test2_top_addsub1_core_instance0_N10_LOGIC_ONE_107 : X_ONE
    port map (
      O => test2_top_addsub1_core_instance0_N10_LOGIC_ONE
    );
  test2_top_addsub1_core_instance0_N10_LOGIC_ZERO_108 : X_ZERO
    port map (
      O => test2_top_addsub1_core_instance0_N10_LOGIC_ZERO
    );
  test2_top_addsub1_core_instance0_BU4 : X_MUX2
    port map (
      IA => test2_top_addsub1_core_instance0_N10_LOGIC_ZERO,
      IB => test2_top_addsub1_core_instance0_N10_LOGIC_ONE,
      SEL => test2_top_addsub1_core_instance0_N10_LOGIC_ONE,
      O => test2_top_addsub1_core_instance0_N5
    );
  test2_top_addsub1_core_instance0_N10_COUTUSED : X_BUF
    port map (
      I => test2_top_addsub1_core_instance0_N10_CYMUXG,
      O => test2_top_addsub1_core_instance0_N10
    );
  test2_top_addsub1_core_instance0_BU8 : X_MUX2
    port map (
      IA => NLW_test2_top_addsub1_core_instance0_BU8_IA_UNCONNECTED,
      IB => test2_top_addsub1_core_instance0_N5,
      SEL => test2_top_addsub1_core_instance0_N10_LOGIC_ONE,
      O => test2_top_addsub1_core_instance0_N10_CYMUXG
    );
  test2_top_addsub2_core_instance2_BU12 : X_MUX2
    port map (
      IA => test2_top_s(2),
      IB => test2_top_s_x_0_2_CYINIT,
      SEL => test2_top_addsub2_core_instance2_N12,
      O => test2_top_addsub2_core_instance2_N15
    );
  test2_top_addsub2_core_instance2_BU13 : X_XOR2
    port map (
      I0 => test2_top_s_x_0_2_CYINIT,
      I1 => test2_top_addsub2_core_instance2_N12,
      O => test2_top_s_x_0_2_XORF
    );
  test2_top_addsub2_core_instance2_BU11 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s(2),
      ADR1 => gateway_in1_2_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N12
    );
  test2_top_addsub2_core_instance2_BU15 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s(3),
      ADR1 => gateway_in1_3_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N17
    );
  test2_top_s_x_0_2_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_0_2_CYMUXG,
      O => test2_top_addsub2_core_instance2_N20
    );
  test2_top_s_x_0_2_XUSED : X_BUF
    port map (
      I => test2_top_s_x_0_2_XORF,
      O => test2_top_s_x_0(2)
    );
  test2_top_s_x_0_2_YUSED : X_BUF
    port map (
      I => test2_top_s_x_0_2_XORG,
      O => test2_top_s_x_0(3)
    );
  test2_top_addsub2_core_instance2_BU16 : X_MUX2
    port map (
      IA => test2_top_s(3),
      IB => test2_top_addsub2_core_instance2_N15,
      SEL => test2_top_addsub2_core_instance2_N17,
      O => test2_top_s_x_0_2_CYMUXG
    );
  test2_top_addsub2_core_instance2_BU17 : X_XOR2
    port map (
      I0 => test2_top_addsub2_core_instance2_N15,
      I1 => test2_top_addsub2_core_instance2_N17,
      O => test2_top_s_x_0_2_XORG
    );
  test2_top_s_x_0_2_CYINIT_109 : X_BUF
    port map (
      I => test2_top_addsub2_core_instance2_N10,
      O => test2_top_s_x_0_2_CYINIT
    );
  test2_top_addsub2_core_instance2_BU68 : X_XOR2
    port map (
      I0 => test2_top_s_x_0_16_CYINIT,
      I1 => test2_top_addsub2_core_instance2_N82,
      O => test2_top_s_x_0_16_XORF
    );
  test2_top_addsub2_core_instance2_BU67 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s(15),
      ADR1 => gateway_in1_15_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N82
    );
  test2_top_s_x_0_16_XUSED : X_BUF
    port map (
      I => test2_top_s_x_0_16_XORF,
      O => test2_top_s_x_0(16)
    );
  test2_top_s_x_0_16_CYINIT_110 : X_BUF
    port map (
      I => test2_top_addsub2_core_instance2_N80,
      O => test2_top_s_x_0_16_CYINIT
    );
  test2_top_s_x_0_0_LOGIC_ZERO_111 : X_ZERO
    port map (
      O => test2_top_s_x_0_0_LOGIC_ZERO
    );
  test2_top_addsub2_core_instance2_BU4 : X_MUX2
    port map (
      IA => test2_top_s(0),
      IB => test2_top_s_x_0_0_CYINIT,
      SEL => test2_top_addsub2_core_instance2_N2,
      O => test2_top_addsub2_core_instance2_N5
    );
  test2_top_addsub2_core_instance2_BU5 : X_XOR2
    port map (
      I0 => test2_top_s_x_0_0_CYINIT,
      I1 => test2_top_addsub2_core_instance2_N2,
      O => test2_top_s_x_0_0_XORF
    );
  test2_top_addsub2_core_instance2_BU3 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s(0),
      ADR1 => gateway_in1_0_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N2
    );
  test2_top_addsub2_core_instance2_BU7 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s(1),
      ADR1 => gateway_in1_1_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N7
    );
  test2_top_s_x_0_0_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_0_0_CYMUXG,
      O => test2_top_addsub2_core_instance2_N10
    );
  test2_top_s_x_0_0_XUSED : X_BUF
    port map (
      I => test2_top_s_x_0_0_XORF,
      O => test2_top_s_x_0(0)
    );
  test2_top_s_x_0_0_YUSED : X_BUF
    port map (
      I => test2_top_s_x_0_0_XORG,
      O => test2_top_s_x_0(1)
    );
  test2_top_addsub2_core_instance2_BU8 : X_MUX2
    port map (
      IA => test2_top_s(1),
      IB => test2_top_addsub2_core_instance2_N5,
      SEL => test2_top_addsub2_core_instance2_N7,
      O => test2_top_s_x_0_0_CYMUXG
    );
  test2_top_addsub2_core_instance2_BU9 : X_XOR2
    port map (
      I0 => test2_top_addsub2_core_instance2_N5,
      I1 => test2_top_addsub2_core_instance2_N7,
      O => test2_top_s_x_0_0_XORG
    );
  test2_top_s_x_0_0_CYINIT_112 : X_BUF
    port map (
      I => test2_top_s_x_0_0_LOGIC_ZERO,
      O => test2_top_s_x_0_0_CYINIT
    );
  test2_top_addsub2_core_instance2_BU60 : X_MUX2
    port map (
      IA => test2_top_s(14),
      IB => test2_top_s_x_0_14_CYINIT,
      SEL => test2_top_addsub2_core_instance2_N72,
      O => test2_top_addsub2_core_instance2_N75
    );
  test2_top_addsub2_core_instance2_BU61 : X_XOR2
    port map (
      I0 => test2_top_s_x_0_14_CYINIT,
      I1 => test2_top_addsub2_core_instance2_N72,
      O => test2_top_s_x_0_14_XORF
    );
  test2_top_addsub2_core_instance2_BU59 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s(14),
      ADR1 => gateway_in1_14_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N72
    );
  test2_top_addsub2_core_instance2_BU63 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s(15),
      ADR1 => VCC,
      ADR2 => gateway_in1_15_IBUF,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N77
    );
  test2_top_s_x_0_14_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_0_14_CYMUXG,
      O => test2_top_addsub2_core_instance2_N80
    );
  test2_top_s_x_0_14_XUSED : X_BUF
    port map (
      I => test2_top_s_x_0_14_XORF,
      O => test2_top_s_x_0(14)
    );
  test2_top_s_x_0_14_YUSED : X_BUF
    port map (
      I => test2_top_s_x_0_14_XORG,
      O => test2_top_s_x_0(15)
    );
  test2_top_addsub2_core_instance2_BU64 : X_MUX2
    port map (
      IA => test2_top_s(15),
      IB => test2_top_addsub2_core_instance2_N75,
      SEL => test2_top_addsub2_core_instance2_N77,
      O => test2_top_s_x_0_14_CYMUXG
    );
  test2_top_addsub2_core_instance2_BU65 : X_XOR2
    port map (
      I0 => test2_top_addsub2_core_instance2_N75,
      I1 => test2_top_addsub2_core_instance2_N77,
      O => test2_top_s_x_0_14_XORG
    );
  test2_top_s_x_0_14_CYINIT_113 : X_BUF
    port map (
      I => test2_top_addsub2_core_instance2_N70,
      O => test2_top_s_x_0_14_CYINIT
    );
  test2_top_addsub2_core_instance2_BU52 : X_MUX2
    port map (
      IA => test2_top_s(12),
      IB => test2_top_s_x_0_12_CYINIT,
      SEL => test2_top_addsub2_core_instance2_N62,
      O => test2_top_addsub2_core_instance2_N65
    );
  test2_top_addsub2_core_instance2_BU53 : X_XOR2
    port map (
      I0 => test2_top_s_x_0_12_CYINIT,
      I1 => test2_top_addsub2_core_instance2_N62,
      O => test2_top_s_x_0_12_XORF
    );
  test2_top_addsub2_core_instance2_BU51 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s(12),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_12_IBUF,
      O => test2_top_addsub2_core_instance2_N62
    );
  test2_top_addsub2_core_instance2_BU55 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s(13),
      ADR1 => VCC,
      ADR2 => gateway_in1_13_IBUF,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N67
    );
  test2_top_s_x_0_12_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_0_12_CYMUXG,
      O => test2_top_addsub2_core_instance2_N70
    );
  test2_top_s_x_0_12_XUSED : X_BUF
    port map (
      I => test2_top_s_x_0_12_XORF,
      O => test2_top_s_x_0(12)
    );
  test2_top_s_x_0_12_YUSED : X_BUF
    port map (
      I => test2_top_s_x_0_12_XORG,
      O => test2_top_s_x_0(13)
    );
  test2_top_addsub2_core_instance2_BU56 : X_MUX2
    port map (
      IA => test2_top_s(13),
      IB => test2_top_addsub2_core_instance2_N65,
      SEL => test2_top_addsub2_core_instance2_N67,
      O => test2_top_s_x_0_12_CYMUXG
    );
  test2_top_addsub2_core_instance2_BU57 : X_XOR2
    port map (
      I0 => test2_top_addsub2_core_instance2_N65,
      I1 => test2_top_addsub2_core_instance2_N67,
      O => test2_top_s_x_0_12_XORG
    );
  test2_top_s_x_0_12_CYINIT_114 : X_BUF
    port map (
      I => test2_top_addsub2_core_instance2_N60,
      O => test2_top_s_x_0_12_CYINIT
    );
  test2_top_addsub2_core_instance2_BU44 : X_MUX2
    port map (
      IA => test2_top_s(10),
      IB => test2_top_s_x_0_10_CYINIT,
      SEL => test2_top_addsub2_core_instance2_N52,
      O => test2_top_addsub2_core_instance2_N55
    );
  test2_top_addsub2_core_instance2_BU45 : X_XOR2
    port map (
      I0 => test2_top_s_x_0_10_CYINIT,
      I1 => test2_top_addsub2_core_instance2_N52,
      O => test2_top_s_x_0_10_XORF
    );
  test2_top_addsub2_core_instance2_BU43 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s(10),
      ADR1 => gateway_in1_10_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N52
    );
  test2_top_addsub2_core_instance2_BU47 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s(11),
      ADR1 => VCC,
      ADR2 => gateway_in1_11_IBUF,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N57
    );
  test2_top_s_x_0_10_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_0_10_CYMUXG,
      O => test2_top_addsub2_core_instance2_N60
    );
  test2_top_s_x_0_10_XUSED : X_BUF
    port map (
      I => test2_top_s_x_0_10_XORF,
      O => test2_top_s_x_0(10)
    );
  test2_top_s_x_0_10_YUSED : X_BUF
    port map (
      I => test2_top_s_x_0_10_XORG,
      O => test2_top_s_x_0(11)
    );
  test2_top_addsub2_core_instance2_BU48 : X_MUX2
    port map (
      IA => test2_top_s(11),
      IB => test2_top_addsub2_core_instance2_N55,
      SEL => test2_top_addsub2_core_instance2_N57,
      O => test2_top_s_x_0_10_CYMUXG
    );
  test2_top_addsub2_core_instance2_BU49 : X_XOR2
    port map (
      I0 => test2_top_addsub2_core_instance2_N55,
      I1 => test2_top_addsub2_core_instance2_N57,
      O => test2_top_s_x_0_10_XORG
    );
  test2_top_s_x_0_10_CYINIT_115 : X_BUF
    port map (
      I => test2_top_addsub2_core_instance2_N50,
      O => test2_top_s_x_0_10_CYINIT
    );
  test2_top_addsub2_core_instance2_BU36 : X_MUX2
    port map (
      IA => test2_top_s(8),
      IB => test2_top_s_x_0_8_CYINIT,
      SEL => test2_top_addsub2_core_instance2_N42,
      O => test2_top_addsub2_core_instance2_N45
    );
  test2_top_addsub2_core_instance2_BU37 : X_XOR2
    port map (
      I0 => test2_top_s_x_0_8_CYINIT,
      I1 => test2_top_addsub2_core_instance2_N42,
      O => test2_top_s_x_0_8_XORF
    );
  test2_top_addsub2_core_instance2_BU35 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s(8),
      ADR1 => gateway_in1_8_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N42
    );
  test2_top_addsub2_core_instance2_BU39 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s(9),
      ADR1 => gateway_in1_9_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N47
    );
  test2_top_s_x_0_8_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_0_8_CYMUXG,
      O => test2_top_addsub2_core_instance2_N50
    );
  test2_top_s_x_0_8_XUSED : X_BUF
    port map (
      I => test2_top_s_x_0_8_XORF,
      O => test2_top_s_x_0(8)
    );
  test2_top_s_x_0_8_YUSED : X_BUF
    port map (
      I => test2_top_s_x_0_8_XORG,
      O => test2_top_s_x_0(9)
    );
  test2_top_addsub2_core_instance2_BU40 : X_MUX2
    port map (
      IA => test2_top_s(9),
      IB => test2_top_addsub2_core_instance2_N45,
      SEL => test2_top_addsub2_core_instance2_N47,
      O => test2_top_s_x_0_8_CYMUXG
    );
  test2_top_addsub2_core_instance2_BU41 : X_XOR2
    port map (
      I0 => test2_top_addsub2_core_instance2_N45,
      I1 => test2_top_addsub2_core_instance2_N47,
      O => test2_top_s_x_0_8_XORG
    );
  test2_top_s_x_0_8_CYINIT_116 : X_BUF
    port map (
      I => test2_top_addsub2_core_instance2_N40,
      O => test2_top_s_x_0_8_CYINIT
    );
  test2_top_addsub2_core_instance2_BU28 : X_MUX2
    port map (
      IA => test2_top_s(6),
      IB => test2_top_s_x_0_6_CYINIT,
      SEL => test2_top_addsub2_core_instance2_N32,
      O => test2_top_addsub2_core_instance2_N35
    );
  test2_top_addsub2_core_instance2_BU29 : X_XOR2
    port map (
      I0 => test2_top_s_x_0_6_CYINIT,
      I1 => test2_top_addsub2_core_instance2_N32,
      O => test2_top_s_x_0_6_XORF
    );
  test2_top_addsub2_core_instance2_BU27 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s(6),
      ADR1 => gateway_in1_6_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N32
    );
  test2_top_addsub2_core_instance2_BU31 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s(7),
      ADR1 => VCC,
      ADR2 => gateway_in1_7_IBUF,
      ADR3 => VCC,
      O => test2_top_addsub2_core_instance2_N37
    );
  test2_top_s_x_0_6_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_0_6_CYMUXG,
      O => test2_top_addsub2_core_instance2_N40
    );
  test2_top_s_x_0_6_XUSED : X_BUF
    port map (
      I => test2_top_s_x_0_6_XORF,
      O => test2_top_s_x_0(6)
    );
  test2_top_s_x_0_6_YUSED : X_BUF
    port map (
      I => test2_top_s_x_0_6_XORG,
      O => test2_top_s_x_0(7)
    );
  test2_top_addsub2_core_instance2_BU32 : X_MUX2
    port map (
      IA => test2_top_s(7),
      IB => test2_top_addsub2_core_instance2_N35,
      SEL => test2_top_addsub2_core_instance2_N37,
      O => test2_top_s_x_0_6_CYMUXG
    );
  test2_top_addsub2_core_instance2_BU33 : X_XOR2
    port map (
      I0 => test2_top_addsub2_core_instance2_N35,
      I1 => test2_top_addsub2_core_instance2_N37,
      O => test2_top_s_x_0_6_XORG
    );
  test2_top_s_x_0_6_CYINIT_117 : X_BUF
    port map (
      I => test2_top_addsub2_core_instance2_N30,
      O => test2_top_s_x_0_6_CYINIT
    );
  test2_top_addsub2_core_instance2_BU20 : X_MUX2
    port map (
      IA => test2_top_s(4),
      IB => test2_top_s_x_0_4_CYINIT,
      SEL => test2_top_addsub2_core_instance2_N22,
      O => test2_top_addsub2_core_instance2_N25
    );
  test2_top_addsub2_core_instance2_BU21 : X_XOR2
    port map (
      I0 => test2_top_s_x_0_4_CYINIT,
      I1 => test2_top_addsub2_core_instance2_N22,
      O => test2_top_s_x_0_4_XORF
    );
  test2_top_addsub2_core_instance2_BU19 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_4_IBUF,
      O => test2_top_addsub2_core_instance2_N22
    );
  test2_top_addsub2_core_instance2_BU23 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => gateway_in1_5_IBUF,
      O => test2_top_addsub2_core_instance2_N27
    );
  test2_top_s_x_0_4_COUTUSED : X_BUF
    port map (
      I => test2_top_s_x_0_4_CYMUXG,
      O => test2_top_addsub2_core_instance2_N30
    );
  test2_top_s_x_0_4_XUSED : X_BUF
    port map (
      I => test2_top_s_x_0_4_XORF,
      O => test2_top_s_x_0(4)
    );
  test2_top_s_x_0_4_YUSED : X_BUF
    port map (
      I => test2_top_s_x_0_4_XORG,
      O => test2_top_s_x_0(5)
    );
  test2_top_addsub2_core_instance2_BU24 : X_MUX2
    port map (
      IA => test2_top_s(5),
      IB => test2_top_addsub2_core_instance2_N25,
      SEL => test2_top_addsub2_core_instance2_N27,
      O => test2_top_s_x_0_4_CYMUXG
    );
  test2_top_addsub2_core_instance2_BU25 : X_XOR2
    port map (
      I0 => test2_top_addsub2_core_instance2_N25,
      I1 => test2_top_addsub2_core_instance2_N27,
      O => test2_top_s_x_0_4_XORG
    );
  test2_top_s_x_0_4_CYINIT_118 : X_BUF
    port map (
      I => test2_top_addsub2_core_instance2_N20,
      O => test2_top_s_x_0_4_CYINIT
    );
  test2_top_kd_core_instance2_N1173_LOGIC_ZERO_119 : X_ZERO
    port map (
      O => test2_top_kd_core_instance2_N1173_LOGIC_ZERO
    );
  test2_top_kd_core_instance2_BU193 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1173_LOGIC_ZERO,
      IB => test2_top_kd_core_instance2_N1173_CYINIT,
      SEL => test2_top_kd_core_instance2_N6169,
      O => test2_top_kd_core_instance2_N6172
    );
  test2_top_kd_core_instance2_BU194 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N1173_CYINIT,
      I1 => test2_top_kd_core_instance2_N6169,
      O => test2_top_kd_core_instance2_N1173_XORF
    );
  test2_top_kd_core_instance2_BU192 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2092,
      O => test2_top_kd_core_instance2_N6169
    );
  test2_top_kd_core_instance2_BU196 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2091,
      O => test2_top_kd_core_instance2_N6174
    );
  test2_top_kd_core_instance2_N1173_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1173_CYMUXG,
      O => test2_top_kd_core_instance2_N1171
    );
  test2_top_kd_core_instance2_N1173_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1173_XORF,
      O => test2_top_kd_core_instance2_N1173
    );
  test2_top_kd_core_instance2_N1173_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1173_XORG,
      O => test2_top_kd_core_instance2_N1172
    );
  test2_top_kd_core_instance2_BU197 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1173_LOGIC_ZERO,
      IB => test2_top_kd_core_instance2_N6172,
      SEL => test2_top_kd_core_instance2_N6174,
      O => test2_top_kd_core_instance2_N1173_CYMUXG
    );
  test2_top_kd_core_instance2_BU198 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N6172,
      I1 => test2_top_kd_core_instance2_N6174,
      O => test2_top_kd_core_instance2_N1173_XORG
    );
  test2_top_kd_core_instance2_N1173_CYINIT_120 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N6167,
      O => test2_top_kd_core_instance2_N1173_CYINIT
    );
  test2_top_kd_core_instance2_BU136 : X_LUT4
    generic map(
      INIT => X"442A"
    )
    port map (
      ADR0 => test2_top_s_x_0(7),
      ADR1 => test2_top_s_x_0(5),
      ADR2 => test2_top_s_x_0(4),
      ADR3 => test2_top_s_x_0(6),
      O => test2_top_kd_core_instance2_N2092_FROM
    );
  test2_top_kd_core_instance2_BU132 : X_LUT4
    generic map(
      INIT => X"D32C"
    )
    port map (
      ADR0 => test2_top_s_x_0(4),
      ADR1 => test2_top_s_x_0(6),
      ADR2 => test2_top_s_x_0(5),
      ADR3 => test2_top_s_x_0(7),
      O => test2_top_kd_core_instance2_N2092_GROM
    );
  test2_top_kd_core_instance2_N2092_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2092_FROM,
      O => test2_top_kd_core_instance2_N2092
    );
  test2_top_kd_core_instance2_N2092_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2092_GROM,
      O => test2_top_kd_core_instance2_N2093
    );
  test2_top_kd_core_instance2_BU75 : X_LUT4
    generic map(
      INIT => X"1858"
    )
    port map (
      ADR0 => test2_top_s_x_0(2),
      ADR1 => test2_top_s_x_0(1),
      ADR2 => test2_top_s_x_0(3),
      ADR3 => test2_top_s_x_0(0),
      O => test2_top_kd_core_instance2_N1978_FROM
    );
  test2_top_kd_core_instance2_BU71 : X_LUT4
    generic map(
      INIT => X"9C66"
    )
    port map (
      ADR0 => test2_top_s_x_0(2),
      ADR1 => test2_top_s_x_0(3),
      ADR2 => test2_top_s_x_0(0),
      ADR3 => test2_top_s_x_0(1),
      O => test2_top_kd_core_instance2_N1978_GROM
    );
  test2_top_kd_core_instance2_N1978_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1978_FROM,
      O => test2_top_kd_core_instance2_N1978
    );
  test2_top_kd_core_instance2_N1978_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1978_GROM,
      O => test2_top_kd_core_instance2_N1979
    );
  test2_top_kd_core_instance2_N1175_LOGIC_ZERO_121 : X_ZERO
    port map (
      O => test2_top_kd_core_instance2_N1175_LOGIC_ZERO
    );
  test2_top_kd_core_instance2_BU185 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1175_LOGIC_ZERO,
      IB => test2_top_kd_core_instance2_N1175_CYINIT,
      SEL => test2_top_kd_core_instance2_N6159,
      O => test2_top_kd_core_instance2_N6162
    );
  test2_top_kd_core_instance2_BU186 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N1175_CYINIT,
      I1 => test2_top_kd_core_instance2_N6159,
      O => test2_top_kd_core_instance2_N1175_XORF
    );
  test2_top_kd_core_instance2_BU184 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2094,
      O => test2_top_kd_core_instance2_N6159
    );
  test2_top_kd_core_instance2_BU188 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2093,
      O => test2_top_kd_core_instance2_N6164
    );
  test2_top_kd_core_instance2_N1175_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1175_CYMUXG,
      O => test2_top_kd_core_instance2_N6167
    );
  test2_top_kd_core_instance2_N1175_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1175_XORF,
      O => test2_top_kd_core_instance2_N1175
    );
  test2_top_kd_core_instance2_N1175_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1175_XORG,
      O => test2_top_kd_core_instance2_N1174
    );
  test2_top_kd_core_instance2_BU189 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1175_LOGIC_ZERO,
      IB => test2_top_kd_core_instance2_N6162,
      SEL => test2_top_kd_core_instance2_N6164,
      O => test2_top_kd_core_instance2_N1175_CYMUXG
    );
  test2_top_kd_core_instance2_BU190 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N6162,
      I1 => test2_top_kd_core_instance2_N6164,
      O => test2_top_kd_core_instance2_N1175_XORG
    );
  test2_top_kd_core_instance2_N1175_CYINIT_122 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N6157,
      O => test2_top_kd_core_instance2_N1175_CYINIT
    );
  test2_top_kd_core_instance2_BU416 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1171,
      IB => test2_top_kd_core_instance2_N1225_CYINIT,
      SEL => test2_top_kd_core_instance2_N7748,
      O => test2_top_kd_core_instance2_N7751
    );
  test2_top_kd_core_instance2_BU417 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N1225_CYINIT,
      I1 => test2_top_kd_core_instance2_N7748,
      O => test2_top_kd_core_instance2_N1225_XORF
    );
  test2_top_kd_core_instance2_BU415 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1171,
      ADR1 => VCC,
      ADR2 => test2_top_kd_core_instance2_N1206,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N7748
    );
  test2_top_kd_core_instance2_BU419 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1205,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N7753
    );
  test2_top_kd_core_instance2_N1225_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1225_XORF,
      O => test2_top_kd_core_instance2_N1225
    );
  test2_top_kd_core_instance2_N1225_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1225_XORG,
      O => test2_top_kd_core_instance2_N1224
    );
  test2_top_kd_core_instance2_BU421 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N7751,
      I1 => test2_top_kd_core_instance2_N7753,
      O => test2_top_kd_core_instance2_N1225_XORG
    );
  test2_top_kd_core_instance2_N1225_CYINIT_123 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N7746,
      O => test2_top_kd_core_instance2_N1225_CYINIT
    );
  test2_top_kd_core_instance2_BU128 : X_LUT4
    generic map(
      INIT => X"AA5A"
    )
    port map (
      ADR0 => test2_top_s_x_0(6),
      ADR1 => VCC,
      ADR2 => test2_top_s_x_0(5),
      ADR3 => test2_top_s_x_0(4),
      O => test2_top_kd_core_instance2_N2094_FROM
    );
  test2_top_kd_core_instance2_BU124 : X_LUT4
    generic map(
      INIT => X"0FF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => test2_top_s_x_0(4),
      ADR3 => test2_top_s_x_0(5),
      O => test2_top_kd_core_instance2_N2094_GROM
    );
  test2_top_kd_core_instance2_N2094_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2094_FROM,
      O => test2_top_kd_core_instance2_N2094
    );
  test2_top_kd_core_instance2_N2094_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2094_GROM,
      O => test2_top_kd_core_instance2_N2095
    );
  test2_top_kd_core_instance2_BU67 : X_LUT4
    generic map(
      INIT => X"A6A6"
    )
    port map (
      ADR0 => test2_top_s_x_0(2),
      ADR1 => test2_top_s_x_0(1),
      ADR2 => test2_top_s_x_0(0),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N1980_FROM
    );
  test2_top_kd_core_instance2_BU63 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_0(1),
      ADR1 => VCC,
      ADR2 => test2_top_s_x_0(0),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N1980_GROM
    );
  test2_top_kd_core_instance2_N1980_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1980_FROM,
      O => test2_top_kd_core_instance2_N1980
    );
  test2_top_kd_core_instance2_N1980_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1980_GROM,
      O => test2_top_kd_core_instance2_N1981
    );
  test2_top_kd_core_instance2_BU244 : X_LUT4
    generic map(
      INIT => X"9A9A"
    )
    port map (
      ADR0 => test2_top_s_x_0(10),
      ADR1 => test2_top_s_x_0(8),
      ADR2 => test2_top_s_x_0(9),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N2349_FROM
    );
  test2_top_kd_core_instance2_BU240 : X_LUT4
    generic map(
      INIT => X"3C3C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_s_x_0(8),
      ADR2 => test2_top_s_x_0(9),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N2349_GROM
    );
  test2_top_kd_core_instance2_N2349_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2349_FROM,
      O => test2_top_kd_core_instance2_N2349
    );
  test2_top_kd_core_instance2_N2349_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2349_GROM,
      O => test2_top_kd_core_instance2_N2350
    );
  test2_top_kd_core_instance2_BU177 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1978,
      IB => test2_top_kd_core_instance2_N1177_CYINIT,
      SEL => test2_top_kd_core_instance2_N6149,
      O => test2_top_kd_core_instance2_N6152
    );
  test2_top_kd_core_instance2_BU178 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N1177_CYINIT,
      I1 => test2_top_kd_core_instance2_N6149,
      O => test2_top_kd_core_instance2_N1177_XORF
    );
  test2_top_kd_core_instance2_BU176 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1978,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2096,
      O => test2_top_kd_core_instance2_N6149
    );
  test2_top_kd_core_instance2_BU180 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1977,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2095,
      O => test2_top_kd_core_instance2_N6154
    );
  test2_top_kd_core_instance2_N1177_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1177_CYMUXG,
      O => test2_top_kd_core_instance2_N6157
    );
  test2_top_kd_core_instance2_N1177_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1177_XORF,
      O => test2_top_kd_core_instance2_N1177
    );
  test2_top_kd_core_instance2_N1177_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1177_XORG,
      O => test2_top_kd_core_instance2_N1176
    );
  test2_top_kd_core_instance2_BU181 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1977,
      IB => test2_top_kd_core_instance2_N6152,
      SEL => test2_top_kd_core_instance2_N6154,
      O => test2_top_kd_core_instance2_N1177_CYMUXG
    );
  test2_top_kd_core_instance2_BU182 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N6152,
      I1 => test2_top_kd_core_instance2_N6154,
      O => test2_top_kd_core_instance2_N1177_XORG
    );
  test2_top_kd_core_instance2_N1177_CYINIT_124 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N6147,
      O => test2_top_kd_core_instance2_N1177_CYINIT
    );
  test2_top_kd_core_instance2_BU408 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1173,
      IB => test2_top_kd_core_instance2_N245_CYINIT,
      SEL => test2_top_kd_core_instance2_N7738,
      O => test2_top_kd_core_instance2_N7741
    );
  test2_top_kd_core_instance2_BU409 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N245_CYINIT,
      I1 => test2_top_kd_core_instance2_N7738,
      O => test2_top_kd_core_instance2_N245_XORF
    );
  test2_top_kd_core_instance2_BU407 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1173,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N1208,
      O => test2_top_kd_core_instance2_N7738
    );
  test2_top_kd_core_instance2_BU411 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1172,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N1207,
      O => test2_top_kd_core_instance2_N7743
    );
  test2_top_kd_core_instance2_N245_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N245_CYMUXG,
      O => test2_top_kd_core_instance2_N7746
    );
  test2_top_kd_core_instance2_N245_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N245_XORF,
      O => test2_top_kd_core_instance2_N245
    );
  test2_top_kd_core_instance2_N245_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N245_XORG,
      O => test2_top_kd_core_instance2_N244
    );
  test2_top_kd_core_instance2_BU412 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1172,
      IB => test2_top_kd_core_instance2_N7741,
      SEL => test2_top_kd_core_instance2_N7743,
      O => test2_top_kd_core_instance2_N245_CYMUXG
    );
  test2_top_kd_core_instance2_BU413 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N7741,
      I1 => test2_top_kd_core_instance2_N7743,
      O => test2_top_kd_core_instance2_N245_XORG
    );
  test2_top_kd_core_instance2_N245_CYINIT_125 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N7736,
      O => test2_top_kd_core_instance2_N245_CYINIT
    );
  test2_top_kd_core_instance2_BU116 : X_LUT4
    generic map(
      INIT => X"EA00"
    )
    port map (
      ADR0 => test2_top_s_x_0(6),
      ADR1 => test2_top_s_x_0(4),
      ADR2 => test2_top_s_x_0(5),
      ADR3 => test2_top_s_x_0(7),
      O => test2_top_kd_core_instance2_N2097_FROM
    );
  test2_top_kd_core_instance2_BU120 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_s_x_0(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N2097_GROM
    );
  test2_top_kd_core_instance2_N2097_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2097_FROM,
      O => test2_top_kd_core_instance2_N2097
    );
  test2_top_kd_core_instance2_N2097_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2097_GROM,
      O => test2_top_kd_core_instance2_N2096
    );
  test2_top_kd_core_instance2_BU59 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => test2_top_s_x_0(0),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N1982_FROM
    );
  test2_top_kd_core_instance2_BU55 : X_LUT4
    generic map(
      INIT => X"C888"
    )
    port map (
      ADR0 => test2_top_s_x_0(2),
      ADR1 => test2_top_s_x_0(3),
      ADR2 => test2_top_s_x_0(1),
      ADR3 => test2_top_s_x_0(0),
      O => test2_top_kd_core_instance2_N1982_GROM
    );
  test2_top_kd_core_instance2_N1982_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1982_FROM,
      O => test2_top_kd_core_instance2_N1982
    );
  test2_top_kd_core_instance2_N1982_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1982_GROM,
      O => test2_top_kd_core_instance2_N1983
    );
  test2_top_kd_core_instance2_BU236 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_s_x_0(8),
      O => test2_top_kd_core_instance2_N2351_FROM
    );
  test2_top_kd_core_instance2_BU232 : X_LUT4
    generic map(
      INIT => X"CC80"
    )
    port map (
      ADR0 => test2_top_s_x_0(8),
      ADR1 => test2_top_s_x_0(11),
      ADR2 => test2_top_s_x_0(9),
      ADR3 => test2_top_s_x_0(10),
      O => test2_top_kd_core_instance2_N2351_GROM
    );
  test2_top_kd_core_instance2_N2351_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2351_FROM,
      O => test2_top_kd_core_instance2_N2351
    );
  test2_top_kd_core_instance2_N2351_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2351_GROM,
      O => test2_top_kd_core_instance2_N2352
    );
  test2_top_kd_core_instance2_BU169 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1980,
      IB => test2_top_kd_core_instance2_N1179_CYINIT,
      SEL => test2_top_kd_core_instance2_N6139,
      O => test2_top_kd_core_instance2_N6142
    );
  test2_top_kd_core_instance2_BU170 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N1179_CYINIT,
      I1 => test2_top_kd_core_instance2_N6139,
      O => test2_top_kd_core_instance2_N1179_XORF
    );
  test2_top_kd_core_instance2_BU168 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1980,
      ADR1 => VCC,
      ADR2 => test2_top_kd_core_instance2_N2098,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N6139
    );
  test2_top_kd_core_instance2_BU172 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1979,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2097,
      O => test2_top_kd_core_instance2_N6144
    );
  test2_top_kd_core_instance2_N1179_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1179_CYMUXG,
      O => test2_top_kd_core_instance2_N6147
    );
  test2_top_kd_core_instance2_N1179_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1179_XORF,
      O => test2_top_kd_core_instance2_N1179
    );
  test2_top_kd_core_instance2_N1179_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1179_XORG,
      O => test2_top_kd_core_instance2_N1178
    );
  test2_top_kd_core_instance2_BU173 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1979,
      IB => test2_top_kd_core_instance2_N6142,
      SEL => test2_top_kd_core_instance2_N6144,
      O => test2_top_kd_core_instance2_N1179_CYMUXG
    );
  test2_top_kd_core_instance2_BU174 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N6142,
      I1 => test2_top_kd_core_instance2_N6144,
      O => test2_top_kd_core_instance2_N1179_XORG
    );
  test2_top_kd_core_instance2_N1179_CYINIT_126 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N6137,
      O => test2_top_kd_core_instance2_N1179_CYINIT
    );
  test2_top_kd_core_instance2_BU400 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1175,
      IB => test2_top_kd_core_instance2_N247_CYINIT,
      SEL => test2_top_kd_core_instance2_N7728,
      O => test2_top_kd_core_instance2_N7731
    );
  test2_top_kd_core_instance2_BU401 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N247_CYINIT,
      I1 => test2_top_kd_core_instance2_N7728,
      O => test2_top_kd_core_instance2_N247_XORF
    );
  test2_top_kd_core_instance2_BU399 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1175,
      ADR1 => VCC,
      ADR2 => test2_top_kd_core_instance2_N1210,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N7728
    );
  test2_top_kd_core_instance2_BU403 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1174,
      ADR1 => test2_top_kd_core_instance2_N1209,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N7733
    );
  test2_top_kd_core_instance2_N247_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N247_CYMUXG,
      O => test2_top_kd_core_instance2_N7736
    );
  test2_top_kd_core_instance2_N247_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N247_XORF,
      O => test2_top_kd_core_instance2_N247
    );
  test2_top_kd_core_instance2_N247_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N247_XORG,
      O => test2_top_kd_core_instance2_N246
    );
  test2_top_kd_core_instance2_BU404 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1174,
      IB => test2_top_kd_core_instance2_N7731,
      SEL => test2_top_kd_core_instance2_N7733,
      O => test2_top_kd_core_instance2_N247_CYMUXG
    );
  test2_top_kd_core_instance2_BU405 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N7731,
      I1 => test2_top_kd_core_instance2_N7733,
      O => test2_top_kd_core_instance2_N247_XORG
    );
  test2_top_kd_core_instance2_N247_CYINIT_127 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N7726,
      O => test2_top_kd_core_instance2_N247_CYINIT
    );
  test2_top_kd_core_instance2_BU345 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N2349,
      IB => test2_top_kd_core_instance2_N1206_CYINIT,
      SEL => test2_top_kd_core_instance2_N6832,
      O => test2_top_kd_core_instance2_N6835
    );
  test2_top_kd_core_instance2_BU346 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N1206_CYINIT,
      I1 => test2_top_kd_core_instance2_N6832,
      O => test2_top_kd_core_instance2_N1206_XORF
    );
  test2_top_kd_core_instance2_BU344 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N2349,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2467,
      O => test2_top_kd_core_instance2_N6832
    );
  test2_top_kd_core_instance2_BU348 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N2348,
      ADR1 => test2_top_kd_core_instance2_N2466,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N6837
    );
  test2_top_kd_core_instance2_N1206_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1206_XORF,
      O => test2_top_kd_core_instance2_N1206
    );
  test2_top_kd_core_instance2_N1206_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1206_XORG,
      O => test2_top_kd_core_instance2_N1205
    );
  test2_top_kd_core_instance2_BU350 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N6835,
      I1 => test2_top_kd_core_instance2_N6837,
      O => test2_top_kd_core_instance2_N1206_XORG
    );
  test2_top_kd_core_instance2_N1206_CYINIT_128 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N6830,
      O => test2_top_kd_core_instance2_N1206_CYINIT
    );
  test2_top_kd_core_instance2_BU108 : X_LUT4
    generic map(
      INIT => X"A65A"
    )
    port map (
      ADR0 => test2_top_s_x_0(7),
      ADR1 => test2_top_s_x_0(4),
      ADR2 => test2_top_s_x_0(6),
      ADR3 => test2_top_s_x_0(5),
      O => test2_top_kd_core_instance2_N2099_FROM
    );
  test2_top_kd_core_instance2_BU112 : X_LUT4
    generic map(
      INIT => X"340C"
    )
    port map (
      ADR0 => test2_top_s_x_0(4),
      ADR1 => test2_top_s_x_0(7),
      ADR2 => test2_top_s_x_0(6),
      ADR3 => test2_top_s_x_0(5),
      O => test2_top_kd_core_instance2_N2099_GROM
    );
  test2_top_kd_core_instance2_N2099_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2099_FROM,
      O => test2_top_kd_core_instance2_N2099
    );
  test2_top_kd_core_instance2_N2099_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2099_GROM,
      O => test2_top_kd_core_instance2_N2098
    );
  test2_top_kd_core_instance2_BU47 : X_LUT4
    generic map(
      INIT => X"A578"
    )
    port map (
      ADR0 => test2_top_s_x_0(1),
      ADR1 => test2_top_s_x_0(0),
      ADR2 => test2_top_s_x_0(3),
      ADR3 => test2_top_s_x_0(2),
      O => test2_top_kd_core_instance2_N256_FROM
    );
  test2_top_kd_core_instance2_BU51 : X_LUT4
    generic map(
      INIT => X"4262"
    )
    port map (
      ADR0 => test2_top_s_x_0(3),
      ADR1 => test2_top_s_x_0(2),
      ADR2 => test2_top_s_x_0(1),
      ADR3 => test2_top_s_x_0(0),
      O => test2_top_kd_core_instance2_N256_GROM
    );
  test2_top_kd_core_instance2_N256_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N256_FROM,
      O => test2_top_kd_core_instance2_N256
    );
  test2_top_kd_core_instance2_N256_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N256_GROM,
      O => test2_top_kd_core_instance2_N1984
    );
  test2_top_kd_core_instance2_BU289 : X_LUT4
    generic map(
      INIT => X"1C30"
    )
    port map (
      ADR0 => test2_top_s_x_0(12),
      ADR1 => test2_top_s_x_0(14),
      ADR2 => test2_top_s_x_0(15),
      ADR3 => test2_top_s_x_0(13),
      O => test2_top_kd_core_instance2_N2467_FROM
    );
  test2_top_kd_core_instance2_BU285 : X_LUT4
    generic map(
      INIT => X"D23C"
    )
    port map (
      ADR0 => test2_top_s_x_0(12),
      ADR1 => test2_top_s_x_0(14),
      ADR2 => test2_top_s_x_0(15),
      ADR3 => test2_top_s_x_0(13),
      O => test2_top_kd_core_instance2_N2467_GROM
    );
  test2_top_kd_core_instance2_N2467_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2467_FROM,
      O => test2_top_kd_core_instance2_N2467
    );
  test2_top_kd_core_instance2_N2467_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2467_GROM,
      O => test2_top_kd_core_instance2_N2468
    );
  test2_top_kd_core_instance2_BU228 : X_LUT4
    generic map(
      INIT => X"442A"
    )
    port map (
      ADR0 => test2_top_s_x_0(11),
      ADR1 => test2_top_s_x_0(9),
      ADR2 => test2_top_s_x_0(8),
      ADR3 => test2_top_s_x_0(10),
      O => test2_top_kd_core_instance2_N2353_FROM
    );
  test2_top_kd_core_instance2_BU224 : X_LUT4
    generic map(
      INIT => X"9C66"
    )
    port map (
      ADR0 => test2_top_s_x_0(10),
      ADR1 => test2_top_s_x_0(11),
      ADR2 => test2_top_s_x_0(8),
      ADR3 => test2_top_s_x_0(9),
      O => test2_top_kd_core_instance2_N2353_GROM
    );
  test2_top_kd_core_instance2_N2353_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2353_FROM,
      O => test2_top_kd_core_instance2_N2353
    );
  test2_top_kd_core_instance2_N2353_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2353_GROM,
      O => test2_top_kd_core_instance2_N2354
    );
  test2_top_kd_core_instance2_BU161 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1982,
      IB => test2_top_kd_core_instance2_N253_CYINIT,
      SEL => test2_top_kd_core_instance2_N6129,
      O => test2_top_kd_core_instance2_N6132
    );
  test2_top_kd_core_instance2_BU162 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N253_CYINIT,
      I1 => test2_top_kd_core_instance2_N6129,
      O => test2_top_kd_core_instance2_N253_XORF
    );
  test2_top_kd_core_instance2_BU160 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1982,
      ADR1 => VCC,
      ADR2 => test2_top_kd_core_instance2_N2100,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N6129
    );
  test2_top_kd_core_instance2_BU164 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1981,
      ADR1 => test2_top_kd_core_instance2_N2099,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N6134
    );
  test2_top_kd_core_instance2_N253_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N253_CYMUXG,
      O => test2_top_kd_core_instance2_N6137
    );
  test2_top_kd_core_instance2_N253_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N253_XORF,
      O => test2_top_kd_core_instance2_N253
    );
  test2_top_kd_core_instance2_N253_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N253_XORG,
      O => test2_top_kd_core_instance2_N252
    );
  test2_top_kd_core_instance2_BU165 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1981,
      IB => test2_top_kd_core_instance2_N6132,
      SEL => test2_top_kd_core_instance2_N6134,
      O => test2_top_kd_core_instance2_N253_CYMUXG
    );
  test2_top_kd_core_instance2_BU166 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N6132,
      I1 => test2_top_kd_core_instance2_N6134,
      O => test2_top_kd_core_instance2_N253_XORG
    );
  test2_top_kd_core_instance2_N253_CYINIT_129 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N6127,
      O => test2_top_kd_core_instance2_N253_CYINIT
    );
  test2_top_kd_core_instance2_BU392 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1177,
      IB => test2_top_kd_core_instance2_N249_CYINIT,
      SEL => test2_top_kd_core_instance2_N7718,
      O => test2_top_kd_core_instance2_N7721
    );
  test2_top_kd_core_instance2_BU393 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N249_CYINIT,
      I1 => test2_top_kd_core_instance2_N7718,
      O => test2_top_kd_core_instance2_N249_XORF
    );
  test2_top_kd_core_instance2_BU391 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1177,
      ADR1 => test2_top_kd_core_instance2_N2355,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N7718
    );
  test2_top_kd_core_instance2_BU395 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1176,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2354,
      O => test2_top_kd_core_instance2_N7723
    );
  test2_top_kd_core_instance2_N249_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N249_CYMUXG,
      O => test2_top_kd_core_instance2_N7726
    );
  test2_top_kd_core_instance2_N249_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N249_XORF,
      O => test2_top_kd_core_instance2_N249
    );
  test2_top_kd_core_instance2_N249_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N249_XORG,
      O => test2_top_kd_core_instance2_N248
    );
  test2_top_kd_core_instance2_BU396 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1176,
      IB => test2_top_kd_core_instance2_N7721,
      SEL => test2_top_kd_core_instance2_N7723,
      O => test2_top_kd_core_instance2_N249_CYMUXG
    );
  test2_top_kd_core_instance2_BU397 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N7721,
      I1 => test2_top_kd_core_instance2_N7723,
      O => test2_top_kd_core_instance2_N249_XORG
    );
  test2_top_kd_core_instance2_N249_CYINIT_130 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N7716,
      O => test2_top_kd_core_instance2_N249_CYINIT
    );
  test2_top_kd_core_instance2_BU337 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N2351,
      IB => test2_top_kd_core_instance2_N1208_CYINIT,
      SEL => test2_top_kd_core_instance2_N6822,
      O => test2_top_kd_core_instance2_N6825
    );
  test2_top_kd_core_instance2_BU338 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N1208_CYINIT,
      I1 => test2_top_kd_core_instance2_N6822,
      O => test2_top_kd_core_instance2_N1208_XORF
    );
  test2_top_kd_core_instance2_BU336 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N2351,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2469,
      O => test2_top_kd_core_instance2_N6822
    );
  test2_top_kd_core_instance2_BU340 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N2350,
      ADR1 => VCC,
      ADR2 => test2_top_kd_core_instance2_N2468,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N6827
    );
  test2_top_kd_core_instance2_N1208_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1208_CYMUXG,
      O => test2_top_kd_core_instance2_N6830
    );
  test2_top_kd_core_instance2_N1208_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1208_XORF,
      O => test2_top_kd_core_instance2_N1208
    );
  test2_top_kd_core_instance2_N1208_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1208_XORG,
      O => test2_top_kd_core_instance2_N1207
    );
  test2_top_kd_core_instance2_BU341 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N2350,
      IB => test2_top_kd_core_instance2_N6825,
      SEL => test2_top_kd_core_instance2_N6827,
      O => test2_top_kd_core_instance2_N1208_CYMUXG
    );
  test2_top_kd_core_instance2_BU342 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N6825,
      I1 => test2_top_kd_core_instance2_N6827,
      O => test2_top_kd_core_instance2_N1208_XORG
    );
  test2_top_kd_core_instance2_N1208_CYINIT_131 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N6820,
      O => test2_top_kd_core_instance2_N1208_CYINIT
    );
  test2_top_kd_core_instance2_BU104 : X_LUT4
    generic map(
      INIT => X"A6A6"
    )
    port map (
      ADR0 => test2_top_s_x_0(6),
      ADR1 => test2_top_s_x_0(5),
      ADR2 => test2_top_s_x_0(4),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N2100_FROM
    );
  test2_top_kd_core_instance2_BU100 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_0(5),
      ADR1 => VCC,
      ADR2 => test2_top_s_x_0(4),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N2100_GROM
    );
  test2_top_kd_core_instance2_N2100_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2100_FROM,
      O => test2_top_kd_core_instance2_N2100
    );
  test2_top_kd_core_instance2_N2100_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2100_GROM,
      O => test2_top_kd_core_instance2_N2101
    );
  test2_top_kd_core_instance2_BU39 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_0(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_s_x_0(1),
      O => test2_top_kd_core_instance2_N258_FROM
    );
  test2_top_kd_core_instance2_BU43 : X_LUT4
    generic map(
      INIT => X"9C9C"
    )
    port map (
      ADR0 => test2_top_s_x_0(0),
      ADR1 => test2_top_s_x_0(2),
      ADR2 => test2_top_s_x_0(1),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N258_GROM
    );
  test2_top_kd_core_instance2_N258_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N258_FROM,
      O => test2_top_kd_core_instance2_N258
    );
  test2_top_kd_core_instance2_N258_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N258_GROM,
      O => test2_top_kd_core_instance2_N257
    );
  test2_top_kd_core_instance2_BU277 : X_LUT4
    generic map(
      INIT => X"3C3C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_s_x_0(12),
      ADR2 => test2_top_s_x_0(13),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N2470_FROM
    );
  test2_top_kd_core_instance2_BU281 : X_LUT4
    generic map(
      INIT => X"9A9A"
    )
    port map (
      ADR0 => test2_top_s_x_0(14),
      ADR1 => test2_top_s_x_0(12),
      ADR2 => test2_top_s_x_0(13),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N2470_GROM
    );
  test2_top_kd_core_instance2_N2470_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2470_FROM,
      O => test2_top_kd_core_instance2_N2470
    );
  test2_top_kd_core_instance2_N2470_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2470_GROM,
      O => test2_top_kd_core_instance2_N2469
    );
  test2_top_kd_core_instance2_BU216 : X_LUT4
    generic map(
      INIT => X"3C3C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_s_x_0(9),
      ADR2 => test2_top_s_x_0(8),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N2356_FROM
    );
  test2_top_kd_core_instance2_BU220 : X_LUT4
    generic map(
      INIT => X"F30C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => test2_top_s_x_0(9),
      ADR2 => test2_top_s_x_0(8),
      ADR3 => test2_top_s_x_0(10),
      O => test2_top_kd_core_instance2_N2356_GROM
    );
  test2_top_kd_core_instance2_N2356_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2356_FROM,
      O => test2_top_kd_core_instance2_N2356
    );
  test2_top_kd_core_instance2_N2356_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2356_GROM,
      O => test2_top_kd_core_instance2_N2355
    );
  test2_top_kd_core_instance2_N255_LOGIC_ZERO_132 : X_ZERO
    port map (
      O => test2_top_kd_core_instance2_N255_LOGIC_ZERO
    );
  test2_top_kd_core_instance2_BU153 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1984,
      IB => test2_top_kd_core_instance2_N255_CYINIT,
      SEL => test2_top_kd_core_instance2_N6119,
      O => test2_top_kd_core_instance2_N6122
    );
  test2_top_kd_core_instance2_BU154 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N255_CYINIT,
      I1 => test2_top_kd_core_instance2_N6119,
      O => test2_top_kd_core_instance2_N255_XORF
    );
  test2_top_kd_core_instance2_BU152 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1984,
      ADR1 => test2_top_s_x_0(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N6119
    );
  test2_top_kd_core_instance2_BU156 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1983,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2101,
      O => test2_top_kd_core_instance2_N6124
    );
  test2_top_kd_core_instance2_N255_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N255_CYMUXG,
      O => test2_top_kd_core_instance2_N6127
    );
  test2_top_kd_core_instance2_N255_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N255_XORF,
      O => test2_top_kd_core_instance2_N255
    );
  test2_top_kd_core_instance2_N255_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N255_XORG,
      O => test2_top_kd_core_instance2_N254
    );
  test2_top_kd_core_instance2_BU157 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1983,
      IB => test2_top_kd_core_instance2_N6122,
      SEL => test2_top_kd_core_instance2_N6124,
      O => test2_top_kd_core_instance2_N255_CYMUXG
    );
  test2_top_kd_core_instance2_BU158 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N6122,
      I1 => test2_top_kd_core_instance2_N6124,
      O => test2_top_kd_core_instance2_N255_XORG
    );
  test2_top_kd_core_instance2_N255_CYINIT_133 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N255_LOGIC_ZERO,
      O => test2_top_kd_core_instance2_N255_CYINIT
    );
  test2_top_kd_core_instance2_N251_LOGIC_ZERO_134 : X_ZERO
    port map (
      O => test2_top_kd_core_instance2_N251_LOGIC_ZERO
    );
  test2_top_kd_core_instance2_BU384 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1179,
      IB => test2_top_kd_core_instance2_N251_CYINIT,
      SEL => test2_top_kd_core_instance2_N7708,
      O => test2_top_kd_core_instance2_N7711
    );
  test2_top_kd_core_instance2_BU385 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N251_CYINIT,
      I1 => test2_top_kd_core_instance2_N7708,
      O => test2_top_kd_core_instance2_N251_XORF
    );
  test2_top_kd_core_instance2_BU383 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1179,
      ADR1 => VCC,
      ADR2 => test2_top_s_x_0(8),
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N7708
    );
  test2_top_kd_core_instance2_BU387 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1178,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_kd_core_instance2_N2356,
      O => test2_top_kd_core_instance2_N7713
    );
  test2_top_kd_core_instance2_N251_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N251_CYMUXG,
      O => test2_top_kd_core_instance2_N7716
    );
  test2_top_kd_core_instance2_N251_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N251_XORF,
      O => test2_top_kd_core_instance2_N251
    );
  test2_top_kd_core_instance2_N251_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N251_XORG,
      O => test2_top_kd_core_instance2_N250
    );
  test2_top_kd_core_instance2_BU388 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1178,
      IB => test2_top_kd_core_instance2_N7711,
      SEL => test2_top_kd_core_instance2_N7713,
      O => test2_top_kd_core_instance2_N251_CYMUXG
    );
  test2_top_kd_core_instance2_BU389 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N7711,
      I1 => test2_top_kd_core_instance2_N7713,
      O => test2_top_kd_core_instance2_N251_XORG
    );
  test2_top_kd_core_instance2_N251_CYINIT_135 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N251_LOGIC_ZERO,
      O => test2_top_kd_core_instance2_N251_CYINIT
    );
  test2_top_kd_core_instance2_N1210_LOGIC_ZERO_136 : X_ZERO
    port map (
      O => test2_top_kd_core_instance2_N1210_LOGIC_ZERO
    );
  test2_top_kd_core_instance2_BU329 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N2353,
      IB => test2_top_kd_core_instance2_N1210_CYINIT,
      SEL => test2_top_kd_core_instance2_N6812,
      O => test2_top_kd_core_instance2_N6815
    );
  test2_top_kd_core_instance2_BU330 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N1210_CYINIT,
      I1 => test2_top_kd_core_instance2_N6812,
      O => test2_top_kd_core_instance2_N1210_XORF
    );
  test2_top_kd_core_instance2_BU328 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N2353,
      ADR1 => test2_top_s_x_0(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N6812
    );
  test2_top_kd_core_instance2_BU332 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N2352,
      ADR1 => VCC,
      ADR2 => test2_top_kd_core_instance2_N2470,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N6817
    );
  test2_top_kd_core_instance2_N1210_COUTUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1210_CYMUXG,
      O => test2_top_kd_core_instance2_N6820
    );
  test2_top_kd_core_instance2_N1210_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1210_XORF,
      O => test2_top_kd_core_instance2_N1210
    );
  test2_top_kd_core_instance2_N1210_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1210_XORG,
      O => test2_top_kd_core_instance2_N1209
    );
  test2_top_kd_core_instance2_BU333 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N2352,
      IB => test2_top_kd_core_instance2_N6815,
      SEL => test2_top_kd_core_instance2_N6817,
      O => test2_top_kd_core_instance2_N1210_CYMUXG
    );
  test2_top_kd_core_instance2_BU334 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N6815,
      I1 => test2_top_kd_core_instance2_N6817,
      O => test2_top_kd_core_instance2_N1210_XORG
    );
  test2_top_kd_core_instance2_N1210_CYINIT_137 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1210_LOGIC_ZERO,
      O => test2_top_kd_core_instance2_N1210_CYINIT
    );
  test2_top_kd_core_instance2_N243_LOGIC_ZERO_138 : X_ZERO
    port map (
      O => test2_top_kd_core_instance2_N243_LOGIC_ZERO
    );
  test2_top_kd_core_instance2_BU510 : X_MUX2
    port map (
      IA => test2_top_kd_core_instance2_N1225,
      IB => test2_top_kd_core_instance2_N243_CYINIT,
      SEL => test2_top_kd_core_instance2_N8491,
      O => test2_top_kd_core_instance2_N8494
    );
  test2_top_kd_core_instance2_BU511 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N243_CYINIT,
      I1 => test2_top_kd_core_instance2_N8491,
      O => test2_top_kd_core_instance2_N243_XORF
    );
  test2_top_kd_core_instance2_BU509 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1225,
      ADR1 => test2_top_s_x_0(16),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N8491
    );
  test2_top_kd_core_instance2_BU513 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => test2_top_kd_core_instance2_N1224,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_kd_core_instance2_N8496
    );
  test2_top_kd_core_instance2_N243_XUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N243_XORF,
      O => test2_top_kd_core_instance2_N243
    );
  test2_top_kd_core_instance2_N243_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N243_XORG,
      O => test2_top_kd_core_instance2_N242
    );
  test2_top_kd_core_instance2_BU515 : X_XOR2
    port map (
      I0 => test2_top_kd_core_instance2_N8494,
      I1 => test2_top_kd_core_instance2_N8496,
      O => test2_top_kd_core_instance2_N243_XORG
    );
  test2_top_kd_core_instance2_N243_CYINIT_139 : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N243_LOGIC_ZERO,
      O => test2_top_kd_core_instance2_N243_CYINIT
    );
  test2_top_kd_core_instance2_BU79 : X_LUT4
    generic map(
      INIT => X"E0A0"
    )
    port map (
      ADR0 => test2_top_s_x_0(2),
      ADR1 => test2_top_s_x_0(1),
      ADR2 => test2_top_s_x_0(3),
      ADR3 => test2_top_s_x_0(0),
      O => test2_top_kd_core_instance2_N1977_GROM
    );
  test2_top_kd_core_instance2_N1977_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N1977_GROM,
      O => test2_top_kd_core_instance2_N1977
    );
  test2_top_kd_core_instance2_BU140 : X_LUT4
    generic map(
      INIT => X"F800"
    )
    port map (
      ADR0 => test2_top_s_x_0(5),
      ADR1 => test2_top_s_x_0(4),
      ADR2 => test2_top_s_x_0(6),
      ADR3 => test2_top_s_x_0(7),
      O => test2_top_kd_core_instance2_N2091_GROM
    );
  test2_top_kd_core_instance2_N2091_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2091_GROM,
      O => test2_top_kd_core_instance2_N2091
    );
  test2_top_kd_core_instance2_BU248 : X_LUT4
    generic map(
      INIT => X"96A6"
    )
    port map (
      ADR0 => test2_top_s_x_0(11),
      ADR1 => test2_top_s_x_0(10),
      ADR2 => test2_top_s_x_0(9),
      ADR3 => test2_top_s_x_0(8),
      O => test2_top_kd_core_instance2_N2348_GROM
    );
  test2_top_kd_core_instance2_N2348_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2348_GROM,
      O => test2_top_kd_core_instance2_N2348
    );
  test2_top_kd_core_instance2_BU293 : X_LUT4
    generic map(
      INIT => X"EA00"
    )
    port map (
      ADR0 => test2_top_s_x_0(14),
      ADR1 => test2_top_s_x_0(13),
      ADR2 => test2_top_s_x_0(12),
      ADR3 => test2_top_s_x_0(15),
      O => test2_top_kd_core_instance2_N2466_GROM
    );
  test2_top_kd_core_instance2_N2466_YUSED : X_BUF
    port map (
      I => test2_top_kd_core_instance2_N2466_GROM,
      O => test2_top_kd_core_instance2_N2466
    );
  gateway_in1_0_IMUX : X_BUF
    port map (
      I => gateway_in1_0_IBUF_0,
      O => gateway_in1_0_IBUF
    );
  gateway_in1_0_IBUF_140 : X_BUF
    port map (
      I => gateway_in1(0),
      O => gateway_in1_0_IBUF_0
    );
  gateway_in1_0_DELAY : X_BUF
    port map (
      I => gateway_in1_0_IBUF_0,
      O => gateway_in1_0_IDELAY
    );
  gateway_in1_1_IMUX : X_BUF
    port map (
      I => gateway_in1_1_IBUF_1,
      O => gateway_in1_1_IBUF
    );
  gateway_in1_1_IBUF_141 : X_BUF
    port map (
      I => gateway_in1(1),
      O => gateway_in1_1_IBUF_1
    );
  gateway_in1_1_DELAY : X_BUF
    port map (
      I => gateway_in1_1_IBUF_1,
      O => gateway_in1_1_IDELAY
    );
  gateway_in1_2_IMUX : X_BUF
    port map (
      I => gateway_in1_2_IBUF_2,
      O => gateway_in1_2_IBUF
    );
  gateway_in1_2_IBUF_142 : X_BUF
    port map (
      I => gateway_in1(2),
      O => gateway_in1_2_IBUF_2
    );
  gateway_in1_2_DELAY : X_BUF
    port map (
      I => gateway_in1_2_IBUF_2,
      O => gateway_in1_2_IDELAY
    );
  gateway_in1_3_IMUX : X_BUF
    port map (
      I => gateway_in1_3_IBUF_3,
      O => gateway_in1_3_IBUF
    );
  gateway_in1_3_IBUF_143 : X_BUF
    port map (
      I => gateway_in1(3),
      O => gateway_in1_3_IBUF_3
    );
  gateway_in1_3_DELAY : X_BUF
    port map (
      I => gateway_in1_3_IBUF_3,
      O => gateway_in1_3_IDELAY
    );
  gateway_in1_4_IMUX : X_BUF
    port map (
      I => gateway_in1_4_IBUF_4,
      O => gateway_in1_4_IBUF
    );
  gateway_in1_4_IBUF_144 : X_BUF
    port map (
      I => gateway_in1(4),
      O => gateway_in1_4_IBUF_4
    );
  gateway_in1_4_DELAY : X_BUF
    port map (
      I => gateway_in1_4_IBUF_4,
      O => gateway_in1_4_IDELAY
    );
  gateway_in1_5_IMUX : X_BUF
    port map (
      I => gateway_in1_5_IBUF_5,
      O => gateway_in1_5_IBUF
    );
  gateway_in1_5_IBUF_145 : X_BUF
    port map (
      I => gateway_in1(5),
      O => gateway_in1_5_IBUF_5
    );
  gateway_in1_5_DELAY : X_BUF
    port map (
      I => gateway_in1_5_IBUF_5,
      O => gateway_in1_5_IDELAY
    );
  gateway_in1_6_IMUX : X_BUF
    port map (
      I => gateway_in1_6_IBUF_6,
      O => gateway_in1_6_IBUF
    );
  gateway_in1_6_IBUF_146 : X_BUF
    port map (
      I => gateway_in1(6),
      O => gateway_in1_6_IBUF_6
    );
  gateway_in1_6_DELAY : X_BUF
    port map (
      I => gateway_in1_6_IBUF_6,
      O => gateway_in1_6_IDELAY
    );
  gateway_in1_7_IMUX : X_BUF
    port map (
      I => gateway_in1_7_IBUF_7,
      O => gateway_in1_7_IBUF
    );
  gateway_in1_7_IBUF_147 : X_BUF
    port map (
      I => gateway_in1(7),
      O => gateway_in1_7_IBUF_7
    );
  gateway_in1_7_DELAY : X_BUF
    port map (
      I => gateway_in1_7_IBUF_7,
      O => gateway_in1_7_IDELAY
    );
  gateway_in1_8_IMUX : X_BUF
    port map (
      I => gateway_in1_8_IBUF_8,
      O => gateway_in1_8_IBUF
    );
  gateway_in1_8_IBUF_148 : X_BUF
    port map (
      I => gateway_in1(8),
      O => gateway_in1_8_IBUF_8
    );
  gateway_in1_8_DELAY : X_BUF
    port map (
      I => gateway_in1_8_IBUF_8,
      O => gateway_in1_8_IDELAY
    );
  gateway_in1_9_IMUX : X_BUF
    port map (
      I => gateway_in1_9_IBUF_9,
      O => gateway_in1_9_IBUF
    );
  gateway_in1_9_IBUF_149 : X_BUF
    port map (
      I => gateway_in1(9),
      O => gateway_in1_9_IBUF_9
    );
  gateway_in1_9_DELAY : X_BUF
    port map (
      I => gateway_in1_9_IBUF_9,
      O => gateway_in1_9_IDELAY
    );
  gateway_in1_10_IMUX : X_BUF
    port map (
      I => gateway_in1_10_IBUF_10,
      O => gateway_in1_10_IBUF
    );
  gateway_in1_10_IBUF_150 : X_BUF
    port map (
      I => gateway_in1(10),
      O => gateway_in1_10_IBUF_10
    );
  gateway_in1_10_DELAY : X_BUF
    port map (
      I => gateway_in1_10_IBUF_10,
      O => gateway_in1_10_IDELAY
    );
  gateway_in1_11_IMUX : X_BUF
    port map (
      I => gateway_in1_11_IBUF_11,
      O => gateway_in1_11_IBUF
    );
  gateway_in1_11_IBUF_151 : X_BUF
    port map (
      I => gateway_in1(11),
      O => gateway_in1_11_IBUF_11
    );
  gateway_in1_11_DELAY : X_BUF
    port map (
      I => gateway_in1_11_IBUF_11,
      O => gateway_in1_11_IDELAY
    );
  gateway_in1_12_IMUX : X_BUF
    port map (
      I => gateway_in1_12_IBUF_12,
      O => gateway_in1_12_IBUF
    );
  gateway_in1_12_IBUF_152 : X_BUF
    port map (
      I => gateway_in1(12),
      O => gateway_in1_12_IBUF_12
    );
  gateway_in1_12_DELAY : X_BUF
    port map (
      I => gateway_in1_12_IBUF_12,
      O => gateway_in1_12_IDELAY
    );
  gateway_in1_13_IMUX : X_BUF
    port map (
      I => gateway_in1_13_IBUF_13,
      O => gateway_in1_13_IBUF
    );
  gateway_in1_13_IBUF_153 : X_BUF
    port map (
      I => gateway_in1(13),
      O => gateway_in1_13_IBUF_13
    );
  gateway_in1_13_DELAY : X_BUF
    port map (
      I => gateway_in1_13_IBUF_13,
      O => gateway_in1_13_IDELAY
    );
  gateway_in1_14_IMUX : X_BUF
    port map (
      I => gateway_in1_14_IBUF_14,
      O => gateway_in1_14_IBUF
    );
  gateway_in1_14_IBUF_154 : X_BUF
    port map (
      I => gateway_in1(14),
      O => gateway_in1_14_IBUF_14
    );
  gateway_in1_14_DELAY : X_BUF
    port map (
      I => gateway_in1_14_IBUF_14,
      O => gateway_in1_14_IDELAY
    );
  gateway_in1_15_IMUX : X_BUF
    port map (
      I => gateway_in1_15_IBUF_15,
      O => gateway_in1_15_IBUF
    );
  gateway_in1_15_IBUF_155 : X_BUF
    port map (
      I => gateway_in1(15),
      O => gateway_in1_15_IBUF_15
    );
  gateway_in1_15_DELAY : X_BUF
    port map (
      I => gateway_in1_15_IBUF_15,
      O => gateway_in1_15_IDELAY
    );
  gateway_out_10_OBUF_156 : X_TRI
    port map (
      I => gateway_out_10_OUTMUX,
      CTL => gateway_out_10_ENABLE,
      O => gateway_out(10)
    );
  gateway_out_10_ENABLEINV : X_INV
    port map (
      I => gateway_out_10_TORGTS,
      O => gateway_out_10_ENABLE
    );
  gateway_out_10_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_10_TORGTS
    );
  gateway_out_10_OUTMUX_157 : X_BUF
    port map (
      I => gateway_out_10_OBUF,
      O => gateway_out_10_OUTMUX
    );
  gateway_out_11_OBUF_158 : X_TRI
    port map (
      I => gateway_out_11_OUTMUX,
      CTL => gateway_out_11_ENABLE,
      O => gateway_out(11)
    );
  gateway_out_11_ENABLEINV : X_INV
    port map (
      I => gateway_out_11_TORGTS,
      O => gateway_out_11_ENABLE
    );
  gateway_out_11_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_11_TORGTS
    );
  gateway_out_11_OUTMUX_159 : X_BUF
    port map (
      I => gateway_out_11_OBUF,
      O => gateway_out_11_OUTMUX
    );
  gateway_out_12_OBUF_160 : X_TRI
    port map (
      I => gateway_out_12_OUTMUX,
      CTL => gateway_out_12_ENABLE,
      O => gateway_out(12)
    );
  gateway_out_12_ENABLEINV : X_INV
    port map (
      I => gateway_out_12_TORGTS,
      O => gateway_out_12_ENABLE
    );
  gateway_out_12_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_12_TORGTS
    );
  gateway_out_12_OUTMUX_161 : X_BUF
    port map (
      I => gateway_out_12_OBUF,
      O => gateway_out_12_OUTMUX
    );
  gateway_out_13_OBUF_162 : X_TRI
    port map (
      I => gateway_out_13_OUTMUX,
      CTL => gateway_out_13_ENABLE,
      O => gateway_out(13)
    );
  gateway_out_13_ENABLEINV : X_INV
    port map (
      I => gateway_out_13_TORGTS,
      O => gateway_out_13_ENABLE
    );
  gateway_out_13_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_13_TORGTS
    );
  gateway_out_13_OUTMUX_163 : X_BUF
    port map (
      I => gateway_out_13_OBUF,
      O => gateway_out_13_OUTMUX
    );
  gateway_out_14_OBUF_164 : X_TRI
    port map (
      I => gateway_out_14_OUTMUX,
      CTL => gateway_out_14_ENABLE,
      O => gateway_out(14)
    );
  gateway_out_14_ENABLEINV : X_INV
    port map (
      I => gateway_out_14_TORGTS,
      O => gateway_out_14_ENABLE
    );
  gateway_out_14_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_14_TORGTS
    );
  gateway_out_14_OUTMUX_165 : X_BUF
    port map (
      I => gateway_out_14_OBUF,
      O => gateway_out_14_OUTMUX
    );
  gateway_out_15_OBUF_166 : X_TRI
    port map (
      I => gateway_out_15_OUTMUX,
      CTL => gateway_out_15_ENABLE,
      O => gateway_out(15)
    );
  gateway_out_15_ENABLEINV : X_INV
    port map (
      I => gateway_out_15_TORGTS,
      O => gateway_out_15_ENABLE
    );
  gateway_out_15_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_15_TORGTS
    );
  gateway_out_15_OUTMUX_167 : X_BUF
    port map (
      I => gateway_out_15_OBUF,
      O => gateway_out_15_OUTMUX
    );
  gateway_out_16_OBUF_168 : X_TRI
    port map (
      I => gateway_out_16_OUTMUX,
      CTL => gateway_out_16_ENABLE,
      O => gateway_out(16)
    );
  gateway_out_16_ENABLEINV : X_INV
    port map (
      I => gateway_out_16_TORGTS,
      O => gateway_out_16_ENABLE
    );
  gateway_out_16_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_16_TORGTS
    );
  gateway_out_16_OUTMUX_169 : X_BUF
    port map (
      I => gateway_out_16_OBUF,
      O => gateway_out_16_OUTMUX
    );
  gateway_out_0_OBUF : X_TRI
    port map (
      I => gateway_out_0_OUTMUX,
      CTL => gateway_out_0_ENABLE,
      O => gateway_out(0)
    );
  gateway_out_0_ENABLEINV : X_INV
    port map (
      I => gateway_out_0_TORGTS,
      O => gateway_out_0_ENABLE
    );
  gateway_out_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_0_TORGTS
    );
  gateway_out_0_OUTMUX_170 : X_BUF
    port map (
      I => test2_top_q_x_0(0),
      O => gateway_out_0_OUTMUX
    );
  gateway_out_17_OBUF_171 : X_TRI
    port map (
      I => gateway_out_17_OUTMUX,
      CTL => gateway_out_17_ENABLE,
      O => gateway_out(17)
    );
  gateway_out_17_ENABLEINV : X_INV
    port map (
      I => gateway_out_17_TORGTS,
      O => gateway_out_17_ENABLE
    );
  gateway_out_17_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_17_TORGTS
    );
  gateway_out_17_OUTMUX_172 : X_BUF
    port map (
      I => gateway_out_17_OBUF,
      O => gateway_out_17_OUTMUX
    );
  gateway_out_1_OBUF_173 : X_TRI
    port map (
      I => gateway_out_1_OUTMUX,
      CTL => gateway_out_1_ENABLE,
      O => gateway_out(1)
    );
  gateway_out_1_ENABLEINV : X_INV
    port map (
      I => gateway_out_1_TORGTS,
      O => gateway_out_1_ENABLE
    );
  gateway_out_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_1_TORGTS
    );
  gateway_out_1_OUTMUX_174 : X_BUF
    port map (
      I => gateway_out_1_OBUF,
      O => gateway_out_1_OUTMUX
    );
  gateway_out_18_OBUF_175 : X_TRI
    port map (
      I => gateway_out_18_OUTMUX,
      CTL => gateway_out_18_ENABLE,
      O => gateway_out(18)
    );
  gateway_out_18_ENABLEINV : X_INV
    port map (
      I => gateway_out_18_TORGTS,
      O => gateway_out_18_ENABLE
    );
  gateway_out_18_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_18_TORGTS
    );
  gateway_out_18_OUTMUX_176 : X_BUF
    port map (
      I => gateway_out_18_OBUF,
      O => gateway_out_18_OUTMUX
    );
  gateway_out_2_OBUF_177 : X_TRI
    port map (
      I => gateway_out_2_OUTMUX,
      CTL => gateway_out_2_ENABLE,
      O => gateway_out(2)
    );
  gateway_out_2_ENABLEINV : X_INV
    port map (
      I => gateway_out_2_TORGTS,
      O => gateway_out_2_ENABLE
    );
  gateway_out_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_2_TORGTS
    );
  gateway_out_2_OUTMUX_178 : X_BUF
    port map (
      I => gateway_out_2_OBUF,
      O => gateway_out_2_OUTMUX
    );
  gateway_out_19_OBUF_179 : X_TRI
    port map (
      I => gateway_out_19_OUTMUX,
      CTL => gateway_out_19_ENABLE,
      O => gateway_out(19)
    );
  gateway_out_19_ENABLEINV : X_INV
    port map (
      I => gateway_out_19_TORGTS,
      O => gateway_out_19_ENABLE
    );
  gateway_out_19_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_19_TORGTS
    );
  gateway_out_19_OUTMUX_180 : X_BUF
    port map (
      I => gateway_out_19_OBUF,
      O => gateway_out_19_OUTMUX
    );
  gateway_out_3_OBUF_181 : X_TRI
    port map (
      I => gateway_out_3_OUTMUX,
      CTL => gateway_out_3_ENABLE,
      O => gateway_out(3)
    );
  gateway_out_3_ENABLEINV : X_INV
    port map (
      I => gateway_out_3_TORGTS,
      O => gateway_out_3_ENABLE
    );
  gateway_out_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_3_TORGTS
    );
  gateway_out_3_OUTMUX_182 : X_BUF
    port map (
      I => gateway_out_3_OBUF,
      O => gateway_out_3_OUTMUX
    );
  gateway_out_4_OBUF_183 : X_TRI
    port map (
      I => gateway_out_4_OUTMUX,
      CTL => gateway_out_4_ENABLE,
      O => gateway_out(4)
    );
  gateway_out_4_ENABLEINV : X_INV
    port map (
      I => gateway_out_4_TORGTS,
      O => gateway_out_4_ENABLE
    );
  gateway_out_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_4_TORGTS
    );
  gateway_out_4_OUTMUX_184 : X_BUF
    port map (
      I => gateway_out_4_OBUF,
      O => gateway_out_4_OUTMUX
    );
  gateway_out_5_OBUF_185 : X_TRI
    port map (
      I => gateway_out_5_OUTMUX,
      CTL => gateway_out_5_ENABLE,
      O => gateway_out(5)
    );
  gateway_out_5_ENABLEINV : X_INV
    port map (
      I => gateway_out_5_TORGTS,
      O => gateway_out_5_ENABLE
    );
  gateway_out_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_5_TORGTS
    );
  gateway_out_5_OUTMUX_186 : X_BUF
    port map (
      I => gateway_out_5_OBUF,
      O => gateway_out_5_OUTMUX
    );
  gateway_out_6_OBUF_187 : X_TRI
    port map (
      I => gateway_out_6_OUTMUX,
      CTL => gateway_out_6_ENABLE,
      O => gateway_out(6)
    );
  gateway_out_6_ENABLEINV : X_INV
    port map (
      I => gateway_out_6_TORGTS,
      O => gateway_out_6_ENABLE
    );
  gateway_out_6_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_6_TORGTS
    );
  gateway_out_6_OUTMUX_188 : X_BUF
    port map (
      I => gateway_out_6_OBUF,
      O => gateway_out_6_OUTMUX
    );
  gateway_out_7_OBUF_189 : X_TRI
    port map (
      I => gateway_out_7_OUTMUX,
      CTL => gateway_out_7_ENABLE,
      O => gateway_out(7)
    );
  gateway_out_7_ENABLEINV : X_INV
    port map (
      I => gateway_out_7_TORGTS,
      O => gateway_out_7_ENABLE
    );
  gateway_out_7_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_7_TORGTS
    );
  gateway_out_7_OUTMUX_190 : X_BUF
    port map (
      I => gateway_out_7_OBUF,
      O => gateway_out_7_OUTMUX
    );
  gateway_out_8_OBUF_191 : X_TRI
    port map (
      I => gateway_out_8_OUTMUX,
      CTL => gateway_out_8_ENABLE,
      O => gateway_out(8)
    );
  gateway_out_8_ENABLEINV : X_INV
    port map (
      I => gateway_out_8_TORGTS,
      O => gateway_out_8_ENABLE
    );
  gateway_out_8_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_8_TORGTS
    );
  gateway_out_8_OUTMUX_192 : X_BUF
    port map (
      I => gateway_out_8_OBUF,
      O => gateway_out_8_OUTMUX
    );
  gateway_out_9_OBUF_193 : X_TRI
    port map (
      I => gateway_out_9_OUTMUX,
      CTL => gateway_out_9_ENABLE,
      O => gateway_out(9)
    );
  gateway_out_9_ENABLEINV : X_INV
    port map (
      I => gateway_out_9_TORGTS,
      O => gateway_out_9_ENABLE
    );
  gateway_out_9_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => gateway_out_9_TORGTS
    );
  gateway_out_9_OUTMUX_194 : X_BUF
    port map (
      I => gateway_out_9_OBUF,
      O => gateway_out_9_OUTMUX
    );
  test2_top_q_x_0_1_LOGIC_ZERO_195 : X_ZERO
    port map (
      O => test2_top_q_x_0_1_LOGIC_ZERO
    );
  test2_top_addsub6_core_instance10_BU8 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_1,
      IB => test2_top_q_x_0_1_CYINIT,
      SEL => test2_top_q_x_0_1_FROM,
      O => test2_top_addsub6_core_instance10_N10
    );
  test2_top_addsub6_core_instance10_BU9 : X_XOR2
    port map (
      I0 => test2_top_q_x_0_1_CYINIT,
      I1 => test2_top_q_x_0_1_FROM,
      O => test2_top_q_x_0_1_XORF
    );
  test2_top_q_x_0_1_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_1,
      ADR1 => test2_top_q_x_0(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_q_x_0_1_FROM
    );
  test2_top_addsub6_core_instance10_BU11 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_2(0),
      ADR1 => VCC,
      ADR2 => test2_top_q_x_0(2),
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N12
    );
  test2_top_q_x_0_1_COUTUSED : X_BUF
    port map (
      I => test2_top_q_x_0_1_CYMUXG,
      O => test2_top_addsub6_core_instance10_N15
    );
  test2_top_q_x_0_1_XUSED : X_BUF
    port map (
      I => test2_top_q_x_0_1_XORF,
      O => gateway_out_1_OBUF
    );
  test2_top_q_x_0_1_YUSED : X_BUF
    port map (
      I => test2_top_q_x_0_1_XORG,
      O => gateway_out_2_OBUF
    );
  test2_top_addsub6_core_instance10_BU12 : X_MUX2
    port map (
      IA => test2_top_s_x_2(0),
      IB => test2_top_addsub6_core_instance10_N10,
      SEL => test2_top_addsub6_core_instance10_N12,
      O => test2_top_q_x_0_1_CYMUXG
    );
  test2_top_addsub6_core_instance10_BU13 : X_XOR2
    port map (
      I0 => test2_top_addsub6_core_instance10_N10,
      I1 => test2_top_addsub6_core_instance10_N12,
      O => test2_top_q_x_0_1_XORG
    );
  test2_top_q_x_0_1_CYINIT_196 : X_BUF
    port map (
      I => test2_top_q_x_0_1_LOGIC_ZERO,
      O => test2_top_q_x_0_1_CYINIT
    );
  test2_top_addsub6_core_instance10_BU16 : X_MUX2
    port map (
      IA => test2_top_s_x_2(1),
      IB => test2_top_q_x_0_3_CYINIT,
      SEL => test2_top_addsub6_core_instance10_N17,
      O => test2_top_addsub6_core_instance10_N20
    );
  test2_top_addsub6_core_instance10_BU17 : X_XOR2
    port map (
      I0 => test2_top_q_x_0_3_CYINIT,
      I1 => test2_top_addsub6_core_instance10_N17,
      O => test2_top_q_x_0_3_XORF
    );
  test2_top_addsub6_core_instance10_BU15 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s_x_2(1),
      ADR1 => test2_top_q_x_0(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N17
    );
  test2_top_addsub6_core_instance10_BU19 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_2(2),
      ADR1 => VCC,
      ADR2 => test2_top_q_x_0(4),
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N22
    );
  test2_top_q_x_0_3_COUTUSED : X_BUF
    port map (
      I => test2_top_q_x_0_3_CYMUXG,
      O => test2_top_addsub6_core_instance10_N25
    );
  test2_top_q_x_0_3_XUSED : X_BUF
    port map (
      I => test2_top_q_x_0_3_XORF,
      O => gateway_out_3_OBUF
    );
  test2_top_q_x_0_3_YUSED : X_BUF
    port map (
      I => test2_top_q_x_0_3_XORG,
      O => gateway_out_4_OBUF
    );
  test2_top_addsub6_core_instance10_BU20 : X_MUX2
    port map (
      IA => test2_top_s_x_2(2),
      IB => test2_top_addsub6_core_instance10_N20,
      SEL => test2_top_addsub6_core_instance10_N22,
      O => test2_top_q_x_0_3_CYMUXG
    );
  test2_top_addsub6_core_instance10_BU21 : X_XOR2
    port map (
      I0 => test2_top_addsub6_core_instance10_N20,
      I1 => test2_top_addsub6_core_instance10_N22,
      O => test2_top_q_x_0_3_XORG
    );
  test2_top_q_x_0_3_CYINIT_197 : X_BUF
    port map (
      I => test2_top_addsub6_core_instance10_N15,
      O => test2_top_q_x_0_3_CYINIT
    );
  test2_top_addsub6_core_instance10_BU24 : X_MUX2
    port map (
      IA => test2_top_s_x_2(3),
      IB => test2_top_q_x_0_5_CYINIT,
      SEL => test2_top_addsub6_core_instance10_N27,
      O => test2_top_addsub6_core_instance10_N30
    );
  test2_top_addsub6_core_instance10_BU25 : X_XOR2
    port map (
      I0 => test2_top_q_x_0_5_CYINIT,
      I1 => test2_top_addsub6_core_instance10_N27,
      O => test2_top_q_x_0_5_XORF
    );
  test2_top_addsub6_core_instance10_BU23 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s_x_2(3),
      ADR1 => test2_top_q_x_0(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N27
    );
  test2_top_addsub6_core_instance10_BU27 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_2(4),
      ADR1 => VCC,
      ADR2 => test2_top_q_x_0(6),
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N32
    );
  test2_top_q_x_0_5_COUTUSED : X_BUF
    port map (
      I => test2_top_q_x_0_5_CYMUXG,
      O => test2_top_addsub6_core_instance10_N35
    );
  test2_top_q_x_0_5_XUSED : X_BUF
    port map (
      I => test2_top_q_x_0_5_XORF,
      O => gateway_out_5_OBUF
    );
  test2_top_q_x_0_5_YUSED : X_BUF
    port map (
      I => test2_top_q_x_0_5_XORG,
      O => gateway_out_6_OBUF
    );
  test2_top_addsub6_core_instance10_BU28 : X_MUX2
    port map (
      IA => test2_top_s_x_2(4),
      IB => test2_top_addsub6_core_instance10_N30,
      SEL => test2_top_addsub6_core_instance10_N32,
      O => test2_top_q_x_0_5_CYMUXG
    );
  test2_top_addsub6_core_instance10_BU29 : X_XOR2
    port map (
      I0 => test2_top_addsub6_core_instance10_N30,
      I1 => test2_top_addsub6_core_instance10_N32,
      O => test2_top_q_x_0_5_XORG
    );
  test2_top_q_x_0_5_CYINIT_198 : X_BUF
    port map (
      I => test2_top_addsub6_core_instance10_N25,
      O => test2_top_q_x_0_5_CYINIT
    );
  test2_top_addsub6_core_instance10_BU32 : X_MUX2
    port map (
      IA => test2_top_s_x_2(5),
      IB => test2_top_q_x_0_7_CYINIT,
      SEL => test2_top_addsub6_core_instance10_N37,
      O => test2_top_addsub6_core_instance10_N40
    );
  test2_top_addsub6_core_instance10_BU33 : X_XOR2
    port map (
      I0 => test2_top_q_x_0_7_CYINIT,
      I1 => test2_top_addsub6_core_instance10_N37,
      O => test2_top_q_x_0_7_XORF
    );
  test2_top_addsub6_core_instance10_BU31 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s_x_2(5),
      ADR1 => test2_top_q_x_0(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N37
    );
  test2_top_addsub6_core_instance10_BU35 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_2(6),
      ADR1 => VCC,
      ADR2 => test2_top_q_x_0(8),
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N42
    );
  test2_top_q_x_0_7_COUTUSED : X_BUF
    port map (
      I => test2_top_q_x_0_7_CYMUXG,
      O => test2_top_addsub6_core_instance10_N45
    );
  test2_top_q_x_0_7_XUSED : X_BUF
    port map (
      I => test2_top_q_x_0_7_XORF,
      O => gateway_out_7_OBUF
    );
  test2_top_q_x_0_7_YUSED : X_BUF
    port map (
      I => test2_top_q_x_0_7_XORG,
      O => gateway_out_8_OBUF
    );
  test2_top_addsub6_core_instance10_BU36 : X_MUX2
    port map (
      IA => test2_top_s_x_2(6),
      IB => test2_top_addsub6_core_instance10_N40,
      SEL => test2_top_addsub6_core_instance10_N42,
      O => test2_top_q_x_0_7_CYMUXG
    );
  test2_top_addsub6_core_instance10_BU37 : X_XOR2
    port map (
      I0 => test2_top_addsub6_core_instance10_N40,
      I1 => test2_top_addsub6_core_instance10_N42,
      O => test2_top_q_x_0_7_XORG
    );
  test2_top_q_x_0_7_CYINIT_199 : X_BUF
    port map (
      I => test2_top_addsub6_core_instance10_N35,
      O => test2_top_q_x_0_7_CYINIT
    );
  test2_top_addsub6_core_instance10_BU40 : X_MUX2
    port map (
      IA => test2_top_s_x_2(7),
      IB => test2_top_q_x_0_9_CYINIT,
      SEL => test2_top_addsub6_core_instance10_N47,
      O => test2_top_addsub6_core_instance10_N50
    );
  test2_top_addsub6_core_instance10_BU41 : X_XOR2
    port map (
      I0 => test2_top_q_x_0_9_CYINIT,
      I1 => test2_top_addsub6_core_instance10_N47,
      O => test2_top_q_x_0_9_XORF
    );
  test2_top_addsub6_core_instance10_BU39 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s_x_2(7),
      ADR1 => test2_top_q_x_0(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N47
    );
  test2_top_addsub6_core_instance10_BU43 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_2(8),
      ADR1 => VCC,
      ADR2 => test2_top_q_x_0(10),
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N52
    );
  test2_top_q_x_0_9_COUTUSED : X_BUF
    port map (
      I => test2_top_q_x_0_9_CYMUXG,
      O => test2_top_addsub6_core_instance10_N55
    );
  test2_top_q_x_0_9_XUSED : X_BUF
    port map (
      I => test2_top_q_x_0_9_XORF,
      O => gateway_out_9_OBUF
    );
  test2_top_q_x_0_9_YUSED : X_BUF
    port map (
      I => test2_top_q_x_0_9_XORG,
      O => gateway_out_10_OBUF
    );
  test2_top_addsub6_core_instance10_BU44 : X_MUX2
    port map (
      IA => test2_top_s_x_2(8),
      IB => test2_top_addsub6_core_instance10_N50,
      SEL => test2_top_addsub6_core_instance10_N52,
      O => test2_top_q_x_0_9_CYMUXG
    );
  test2_top_addsub6_core_instance10_BU45 : X_XOR2
    port map (
      I0 => test2_top_addsub6_core_instance10_N50,
      I1 => test2_top_addsub6_core_instance10_N52,
      O => test2_top_q_x_0_9_XORG
    );
  test2_top_q_x_0_9_CYINIT_200 : X_BUF
    port map (
      I => test2_top_addsub6_core_instance10_N45,
      O => test2_top_q_x_0_9_CYINIT
    );
  test2_top_addsub6_core_instance10_BU48 : X_MUX2
    port map (
      IA => test2_top_s_x_2(9),
      IB => test2_top_q_x_0_11_CYINIT,
      SEL => test2_top_addsub6_core_instance10_N57,
      O => test2_top_addsub6_core_instance10_N60
    );
  test2_top_addsub6_core_instance10_BU49 : X_XOR2
    port map (
      I0 => test2_top_q_x_0_11_CYINIT,
      I1 => test2_top_addsub6_core_instance10_N57,
      O => test2_top_q_x_0_11_XORF
    );
  test2_top_addsub6_core_instance10_BU47 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s_x_2(9),
      ADR1 => test2_top_q_x_0(11),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N57
    );
  test2_top_addsub6_core_instance10_BU51 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => test2_top_s_x_2(10),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => test2_top_q_x_0(12),
      O => test2_top_addsub6_core_instance10_N62
    );
  test2_top_q_x_0_11_COUTUSED : X_BUF
    port map (
      I => test2_top_q_x_0_11_CYMUXG,
      O => test2_top_addsub6_core_instance10_N65
    );
  test2_top_q_x_0_11_XUSED : X_BUF
    port map (
      I => test2_top_q_x_0_11_XORF,
      O => gateway_out_11_OBUF
    );
  test2_top_q_x_0_11_YUSED : X_BUF
    port map (
      I => test2_top_q_x_0_11_XORG,
      O => gateway_out_12_OBUF
    );
  test2_top_addsub6_core_instance10_BU52 : X_MUX2
    port map (
      IA => test2_top_s_x_2(10),
      IB => test2_top_addsub6_core_instance10_N60,
      SEL => test2_top_addsub6_core_instance10_N62,
      O => test2_top_q_x_0_11_CYMUXG
    );
  test2_top_addsub6_core_instance10_BU53 : X_XOR2
    port map (
      I0 => test2_top_addsub6_core_instance10_N60,
      I1 => test2_top_addsub6_core_instance10_N62,
      O => test2_top_q_x_0_11_XORG
    );
  test2_top_q_x_0_11_CYINIT_201 : X_BUF
    port map (
      I => test2_top_addsub6_core_instance10_N55,
      O => test2_top_q_x_0_11_CYINIT
    );
  test2_top_addsub6_core_instance10_BU56 : X_MUX2
    port map (
      IA => test2_top_s_x_2(11),
      IB => test2_top_q_x_0_13_CYINIT,
      SEL => test2_top_addsub6_core_instance10_N67,
      O => test2_top_addsub6_core_instance10_N70
    );
  test2_top_addsub6_core_instance10_BU57 : X_XOR2
    port map (
      I0 => test2_top_q_x_0_13_CYINIT,
      I1 => test2_top_addsub6_core_instance10_N67,
      O => test2_top_q_x_0_13_XORF
    );
  test2_top_addsub6_core_instance10_BU55 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s_x_2(11),
      ADR1 => test2_top_q_x_0(13),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N67
    );
  test2_top_addsub6_core_instance10_BU59 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_2(12),
      ADR1 => VCC,
      ADR2 => test2_top_q_x_0(14),
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N72
    );
  test2_top_q_x_0_13_COUTUSED : X_BUF
    port map (
      I => test2_top_q_x_0_13_CYMUXG,
      O => test2_top_addsub6_core_instance10_N75
    );
  test2_top_q_x_0_13_XUSED : X_BUF
    port map (
      I => test2_top_q_x_0_13_XORF,
      O => gateway_out_13_OBUF
    );
  test2_top_q_x_0_13_YUSED : X_BUF
    port map (
      I => test2_top_q_x_0_13_XORG,
      O => gateway_out_14_OBUF
    );
  test2_top_addsub6_core_instance10_BU60 : X_MUX2
    port map (
      IA => test2_top_s_x_2(12),
      IB => test2_top_addsub6_core_instance10_N70,
      SEL => test2_top_addsub6_core_instance10_N72,
      O => test2_top_q_x_0_13_CYMUXG
    );
  test2_top_addsub6_core_instance10_BU61 : X_XOR2
    port map (
      I0 => test2_top_addsub6_core_instance10_N70,
      I1 => test2_top_addsub6_core_instance10_N72,
      O => test2_top_q_x_0_13_XORG
    );
  test2_top_q_x_0_13_CYINIT_202 : X_BUF
    port map (
      I => test2_top_addsub6_core_instance10_N65,
      O => test2_top_q_x_0_13_CYINIT
    );
  test2_top_addsub6_core_instance10_BU64 : X_MUX2
    port map (
      IA => test2_top_s_x_2(13),
      IB => test2_top_q_x_0_15_CYINIT,
      SEL => test2_top_addsub6_core_instance10_N77,
      O => test2_top_addsub6_core_instance10_N80
    );
  test2_top_addsub6_core_instance10_BU65 : X_XOR2
    port map (
      I0 => test2_top_q_x_0_15_CYINIT,
      I1 => test2_top_addsub6_core_instance10_N77,
      O => test2_top_q_x_0_15_XORF
    );
  test2_top_addsub6_core_instance10_BU63 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s_x_2(13),
      ADR1 => test2_top_q_x_0(15),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N77
    );
  test2_top_addsub6_core_instance10_BU67 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_2(14),
      ADR1 => VCC,
      ADR2 => test2_top_q_x_0(16),
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N82
    );
  test2_top_q_x_0_15_COUTUSED : X_BUF
    port map (
      I => test2_top_q_x_0_15_CYMUXG,
      O => test2_top_addsub6_core_instance10_N85
    );
  test2_top_q_x_0_15_XUSED : X_BUF
    port map (
      I => test2_top_q_x_0_15_XORF,
      O => gateway_out_15_OBUF
    );
  test2_top_q_x_0_15_YUSED : X_BUF
    port map (
      I => test2_top_q_x_0_15_XORG,
      O => gateway_out_16_OBUF
    );
  test2_top_addsub6_core_instance10_BU68 : X_MUX2
    port map (
      IA => test2_top_s_x_2(14),
      IB => test2_top_addsub6_core_instance10_N80,
      SEL => test2_top_addsub6_core_instance10_N82,
      O => test2_top_q_x_0_15_CYMUXG
    );
  test2_top_addsub6_core_instance10_BU69 : X_XOR2
    port map (
      I0 => test2_top_addsub6_core_instance10_N80,
      I1 => test2_top_addsub6_core_instance10_N82,
      O => test2_top_q_x_0_15_XORG
    );
  test2_top_q_x_0_15_CYINIT_203 : X_BUF
    port map (
      I => test2_top_addsub6_core_instance10_N75,
      O => test2_top_q_x_0_15_CYINIT
    );
  test2_top_addsub6_core_instance10_BU72 : X_MUX2
    port map (
      IA => test2_top_s_x_2(15),
      IB => test2_top_q_x_0_17_CYINIT,
      SEL => test2_top_addsub6_core_instance10_N87,
      O => test2_top_addsub6_core_instance10_N90
    );
  test2_top_addsub6_core_instance10_BU73 : X_XOR2
    port map (
      I0 => test2_top_q_x_0_17_CYINIT,
      I1 => test2_top_addsub6_core_instance10_N87,
      O => test2_top_q_x_0_17_XORF
    );
  test2_top_addsub6_core_instance10_BU71 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_s_x_2(15),
      ADR1 => test2_top_q_x_0(17),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N87
    );
  test2_top_addsub6_core_instance10_BU75 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => test2_top_s_x_2(16),
      ADR1 => VCC,
      ADR2 => test2_top_q_x_0(18),
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N92
    );
  test2_top_q_x_0_17_COUTUSED : X_BUF
    port map (
      I => test2_top_q_x_0_17_CYMUXG,
      O => test2_top_addsub6_core_instance10_N95
    );
  test2_top_q_x_0_17_XUSED : X_BUF
    port map (
      I => test2_top_q_x_0_17_XORF,
      O => gateway_out_17_OBUF
    );
  test2_top_q_x_0_17_YUSED : X_BUF
    port map (
      I => test2_top_q_x_0_17_XORG,
      O => gateway_out_18_OBUF
    );
  test2_top_addsub6_core_instance10_BU76 : X_MUX2
    port map (
      IA => test2_top_s_x_2(16),
      IB => test2_top_addsub6_core_instance10_N90,
      SEL => test2_top_addsub6_core_instance10_N92,
      O => test2_top_q_x_0_17_CYMUXG
    );
  test2_top_addsub6_core_instance10_BU77 : X_XOR2
    port map (
      I0 => test2_top_addsub6_core_instance10_N90,
      I1 => test2_top_addsub6_core_instance10_N92,
      O => test2_top_q_x_0_17_XORG
    );
  test2_top_q_x_0_17_CYINIT_204 : X_BUF
    port map (
      I => test2_top_addsub6_core_instance10_N85,
      O => test2_top_q_x_0_17_CYINIT
    );
  test2_top_addsub6_core_instance10_BU81 : X_XOR2
    port map (
      I0 => test2_top_q_x_0_19_CYINIT,
      I1 => test2_top_addsub6_core_instance10_N97,
      O => test2_top_q_x_0_19_XORF
    );
  test2_top_addsub6_core_instance10_BU79 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => test2_top_q_x_0(19),
      ADR1 => test2_top_s_x_2(17),
      ADR2 => VCC,
      ADR3 => VCC,
      O => test2_top_addsub6_core_instance10_N97
    );
  test2_top_q_x_0_19_XUSED : X_BUF
    port map (
      I => test2_top_q_x_0_19_XORF,
      O => gateway_out_19_OBUF
    );
  test2_top_q_x_0_19_CYINIT_205 : X_BUF
    port map (
      I => test2_top_addsub6_core_instance10_N95,
      O => test2_top_q_x_0_19_CYINIT
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_5_XORG,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_5_FFY_RST,
      O => test2_top_q_x_0(6)
    );
  test2_top_q_x_0_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_5_FFY_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_3_XORF,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_3_FFX_RST,
      O => test2_top_q_x_0(3)
    );
  test2_top_q_x_0_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_3_FFX_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_7_XORG,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_7_FFY_RST,
      O => test2_top_q_x_0(8)
    );
  test2_top_q_x_0_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_7_FFY_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_5_XORF,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_5_FFX_RST,
      O => test2_top_q_x_0(5)
    );
  test2_top_q_x_0_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_5_FFX_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u210 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_9_XORG,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_9_FFY_RST,
      O => test2_top_q_x_0(10)
    );
  test2_top_q_x_0_9_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_9_FFY_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_7_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_7_IFF_RST,
      O => test2_top_q(7)
    );
  gateway_in1_7_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_7_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_8_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_8_IFF_RST,
      O => test2_top_q(8)
    );
  gateway_in1_8_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_8_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_9_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_9_IFF_RST,
      O => test2_top_q(9)
    );
  gateway_in1_9_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_9_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u210 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_10_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_10_IFF_RST,
      O => test2_top_q(10)
    );
  gateway_in1_10_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_10_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u211 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_11_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_11_IFF_RST,
      O => test2_top_q(11)
    );
  gateway_in1_11_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_11_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u212 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_12_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_12_IFF_RST,
      O => test2_top_q(12)
    );
  gateway_in1_12_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_12_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u213 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_13_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_13_IFF_RST,
      O => test2_top_q(13)
    );
  gateway_in1_13_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_13_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u214 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_14_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_14_IFF_RST,
      O => test2_top_q(14)
    );
  gateway_in1_14_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_14_IFF_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_1_XORG,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_1_FFY_RST,
      O => test2_top_q_x_0(2)
    );
  test2_top_q_x_0_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_1_FFY_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_3_XORG,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_3_FFY_RST,
      O => test2_top_q_x_0(4)
    );
  test2_top_q_x_0_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_3_FFY_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_1_XORF,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_1_FFX_RST,
      O => test2_top_q_x_0(1)
    );
  test2_top_q_x_0_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_1_FFX_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(0),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_1_FFY_RST,
      O => test2_top_q_x_1(0)
    );
  test2_top_q_x_1_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_1_FFY_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(1),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_1_FFX_RST,
      O => test2_top_q_x_1(1)
    );
  test2_top_q_x_1_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_1_FFX_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(2),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_3_FFY_RST,
      O => test2_top_q_x_1(2)
    );
  test2_top_q_x_1_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_3_FFY_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(3),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_3_FFX_RST,
      O => test2_top_q_x_1(3)
    );
  test2_top_q_x_1_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_3_FFX_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(4),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_5_FFY_RST,
      O => test2_top_q_x_1(4)
    );
  test2_top_q_x_1_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_5_FFY_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(5),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_5_FFX_RST,
      O => test2_top_q_x_1(5)
    );
  test2_top_q_x_1_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_5_FFX_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(6),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_7_FFY_RST,
      O => test2_top_q_x_1(6)
    );
  test2_top_q_x_1_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_7_FFY_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(7),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_7_FFX_RST,
      O => test2_top_q_x_1(7)
    );
  test2_top_q_x_1_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_7_FFX_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(8),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_9_FFY_RST,
      O => test2_top_q_x_1(8)
    );
  test2_top_q_x_1_9_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_9_FFY_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(9),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_9_FFX_RST,
      O => test2_top_q_x_1(9)
    );
  test2_top_q_x_1_9_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_9_FFX_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u210 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(10),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_11_FFY_RST,
      O => test2_top_q_x_1(10)
    );
  test2_top_q_x_1_11_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_11_FFY_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u211 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(11),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_11_FFX_RST,
      O => test2_top_q_x_1(11)
    );
  test2_top_q_x_1_11_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_11_FFX_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u212 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(12),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_13_FFY_RST,
      O => test2_top_q_x_1(12)
    );
  test2_top_q_x_1_13_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_13_FFY_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u214 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(14),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_15_FFY_RST,
      O => test2_top_q_x_1(14)
    );
  test2_top_q_x_1_15_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_15_FFY_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u213 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(13),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_13_FFX_RST,
      O => test2_top_q_x_1(13)
    );
  test2_top_q_x_1_13_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_13_FFX_RST
    );
  test2_top_delay2_synth_reg_srl_inst_last_srl17e_u215 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q(15),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_1_15_FFX_RST,
      O => test2_top_q_x_1(15)
    );
  test2_top_q_x_1_15_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_1_15_FFX_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_0_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_0_IFF_RST,
      O => test2_top_q(0)
    );
  gateway_in1_0_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_0_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_1_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_1_IFF_RST,
      O => test2_top_q(1)
    );
  gateway_in1_1_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_1_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_2_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_2_IFF_RST,
      O => test2_top_q(2)
    );
  gateway_in1_2_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_2_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_3_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_3_IFF_RST,
      O => test2_top_q(3)
    );
  gateway_in1_3_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_3_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_4_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_4_IFF_RST,
      O => test2_top_q(4)
    );
  gateway_in1_4_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_4_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_5_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_5_IFF_RST,
      O => test2_top_q(5)
    );
  gateway_in1_5_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_5_IFF_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_6_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_6_IFF_RST,
      O => test2_top_q(6)
    );
  gateway_in1_6_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_6_IFF_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_7_XORF,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_7_FFX_RST,
      O => test2_top_q_x_0(7)
    );
  test2_top_q_x_0_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_7_FFX_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u212 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_11_XORG,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_11_FFY_RST,
      O => test2_top_q_x_0(12)
    );
  test2_top_q_x_0_11_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_11_FFY_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_9_XORF,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_9_FFX_RST,
      O => test2_top_q_x_0(9)
    );
  test2_top_q_x_0_9_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_9_FFX_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u214 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_13_XORG,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_13_FFY_RST,
      O => test2_top_q_x_0(14)
    );
  test2_top_q_x_0_13_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_13_FFY_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u211 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_11_XORF,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_11_FFX_RST,
      O => test2_top_q_x_0(11)
    );
  test2_top_q_x_0_11_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_11_FFX_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u216 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_15_XORG,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_15_FFY_RST,
      O => test2_top_q_x_0(16)
    );
  test2_top_q_x_0_15_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_15_FFY_RST
    );
  test2_top_delay_synth_reg_srl_inst_last_srl17e_u215 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => gateway_in1_15_IDELAY,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => gateway_in1_15_IFF_RST,
      O => test2_top_q(15)
    );
  gateway_in1_15_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => gateway_in1_15_IFF_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u213 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_13_XORF,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_13_FFX_RST,
      O => test2_top_q_x_0(13)
    );
  test2_top_q_x_0_13_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_13_FFX_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u218 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_17_XORG,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_17_FFY_RST,
      O => test2_top_q_x_0(18)
    );
  test2_top_q_x_0_17_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_17_FFY_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u215 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_15_XORF,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_15_FFX_RST,
      O => test2_top_q_x_0(15)
    );
  test2_top_q_x_0_15_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_15_FFX_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0(0),
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_0_FFY_RST,
      O => test2_top_q_x_0(0)
    );
  test2_top_q_x_0_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_0_FFY_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u217 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_17_XORF,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_17_FFX_RST,
      O => test2_top_q_x_0(17)
    );
  test2_top_q_x_0_17_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_17_FFX_RST
    );
  test2_top_delay1_synth_reg_srl_inst_last_srl17e_u219 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => test2_top_q_x_0_19_XORF,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => test2_top_q_x_0_19_FFX_RST,
      O => test2_top_q_x_0(19)
    );
  test2_top_q_x_0_19_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => test2_top_q_x_0_19_FFX_RST
    );
  clk_BUF : X_CKBUF
    port map (
      I => clk,
      O => clk_BUFGP_IBUFG
    );
  clk_BUFGP_BUFG_BUF : X_CKBUF
    port map (
      I => clk_BUFGP_IBUFG,
      O => clk_BUFGP
    );
  PWR_GND_0_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_0_GROM
    );
  PWR_GND_0_YUSED : X_BUF
    port map (
      I => PWR_GND_0_GROM,
      O => GLOBAL_LOGIC0
    );
  PWR_GND_1_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_1_GROM
    );
  PWR_GND_1_YUSED : X_BUF
    port map (
      I => PWR_GND_1_GROM,
      O => GLOBAL_LOGIC0_0
    );
  PWR_GND_2_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_2_GROM
    );
  PWR_GND_2_YUSED : X_BUF
    port map (
      I => PWR_GND_2_GROM,
      O => GLOBAL_LOGIC0_1
    );
  NlwBlock_test2_clk_wrapper_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_test2_clk_wrapper_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

