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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xtest1/test1_pkgs.vhd in Library work.
Completed process "Check Syntax".



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Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do test1_tbw.ado 
listening on address 127.0.0.1 port 1200
# resume
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity srl16e
# -- Loading entity fde
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Loading entity srl17e
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Loading entity fdre
# -- Loading entity fdse
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Loading entity single_reg_w_init
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Loading entity synth_reg_w_init
# -- Loading entity bufg
# -- Compiling entity xlclockgenerator
# -- Compiling architecture structural of xlclockgenerator
# -- Loading entity dcm
# -- Loading entity bufgmux
# -- Compiling entity xlsl2slv
# -- Compiling architecture behavior of xlsl2slv
# -- Compiling entity xlslv2sl
# -- Compiling architecture behavior of xlslv2sl
# -- Compiling entity synth_addsub
# -- Compiling architecture behavior of synth_addsub
# -- Loading entity synth_reg
# -- Compiling entity test1_addsub1
# -- Compiling architecture behavior of test1_addsub1
# -- Loading entity synth_addsub
# WARNING[1]: test1_files.vhd(1507): No default binding for component: "adder_subtracter_spartan2_6_0_438ebd1a25415d4b". (No entity named "adder_subtracter_spartan2_6_0_438ebd1a25415d4b" was found)
# -- Loading package prims_constants_v6_0
# -- Loading package prims_utils_v6_0
# -- Loading package c_reg_fd_v6_0_comp
# -- Loading entity c_addsub_v6_0
# WARNING[1]: test1_files.vhd(1570): No default binding for component: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0". (No entity named "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0" was found)
# WARNING[1]: test1_files.vhd(1633): No default binding for component: "adder_subtracter_spartan2_6_0_86c498140491d6df". (No entity named "adder_subtracter_spartan2_6_0_86c498140491d6df" was found)
# WARNING[1]: test1_files.vhd(1696): No default binding for component: "adder_subtracter_spartan2_6_0_59d46904916909df". (No entity named "adder_subtracter_spartan2_6_0_59d46904916909df" was found)
# WARNING[1]: test1_files.vhd(1759): No default binding for component: "adder_subtracter_spartan2_6_0_350b80de9e916006". (No entity named "adder_subtracter_spartan2_6_0_350b80de9e916006" was found)
# WARNING[1]: test1_files.vhd(1822): No default binding for component: "adder_subtracter_spartan2_6_0_bfeb857b6aedd324". (No entity named "adder_subtracter_spartan2_6_0_bfeb857b6aedd324" was found)
# -- Compiling entity test1_cmult3
# -- Compiling architecture behavior of test1_cmult3
# WARNING[1]: test1_files.vhd(2148): No default binding for component: "multiplier_spartan2_6_0_c898a6c13135c6d0". (No entity named "multiplier_spartan2_6_0_c898a6c13135c6d0" was found)
# -- Loading package mult_const_pkg_v6_0
# -- Loading package mult_gen_v6_0_non_seq_comp
# -- Loading package mult_gen_v6_0_seq_comp
# -- Loading package parm_v6_0_services
# -- Loading package ccm_v6_0_services
# -- Loading package sqm_v6_0_services
# -- Loading package mult_gen_v6_0_services
# -- Loading entity mult_gen_v6_0
# WARNING[1]: test1_files.vhd(2201): No default binding for component: "multiplier_spartan2_6_0_7d52cda8234e03c2". (No entity named "multiplier_spartan2_6_0_7d52cda8234e03c2" was found)
# WARNING[1]: test1_files.vhd(2254): No default binding for component: "multiplier_spartan2_6_0_13a3d468139afdbd". (No entity named "multiplier_spartan2_6_0_13a3d468139afdbd" was found)
# WARNING[1]: test1_files.vhd(2307): No default binding for component: "multiplier_spartan2_6_0_6f13cc9ee672d655". (No entity named "multiplier_spartan2_6_0_6f13cc9ee672d655" was found)
# -- Compiling entity xldelay
# -- Compiling architecture behavior of xldelay
# -- Loading entity synth_reg_reg
# -- Compiling entity test1
# -- Compiling architecture structural of test1
# -- Loading entity test1_addsub1
# -- Loading entity test1_cmult3
# -- Loading entity xldelay
# -- Loading entity xlsl2slv
# -- Compiling entity test1_clock_driver
# -- Compiling architecture structural of test1_clock_driver
# -- Loading entity xlclockdriver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity test1_clk_wrapper
# -- Compiling architecture structural of test1_clk_wrapper
# -- Loading entity test1_clock_driver
# -- Loading entity test1
# -- Loading entity xlclkprobe
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity test1_tbw
# -- Compiling architecture testbench_arch of test1_tbw
# -- Loading entity test1_clk_wrapper
# -- Compiling configuration test1_clk_wrapper_cfg
# -- Loading entity test1_tbw
# -- Loading architecture testbench_arch of test1_tbw
# vsim -lib work -t 1ps test1_tbw 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading work.clock_pkg
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.test1_tbw(testbench_arch)
# Loading work.test1_clk_wrapper(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading work.test1_clock_driver(structural)
# Loading work.xlclockdriver(behavior)
# Loading work.synth_reg_w_init(structural)
# Loading work.single_reg_w_init(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading work.test1(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_constants_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.prims_utils_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.test1_addsub1(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.c_addsub_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_const_pkg_v6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_seq_comp
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.parm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.ccm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.sqm_v6_0_services(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_services(body)
# Loading work.test1_cmult3(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_pkg_v6_0(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0(behavioral)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.mult_gen_v6_0_non_seq(behavioral)
# Loading work.xldelay(behavior)
# Loading work.synth_reg(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vpkg(body)
# Loading work.srl17e(structural)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fde(fde_v)
# Loading work.xlsl2slv(behavior)
# Loading work.xlclkprobe(behavior)
# WARNING: Design size of 6944 statements or 27 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Failure: Success! Simulation for annotation completed
#    Time: 910 ns  Iteration: 0  Process: /test1_tbw/line__81 File: test1_tbw.ant
# Break at test1_tbw.ant line 126
# Stopped at test1_tbw.ant line 126 


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