JDF G
//
// Created by System Generator v6.2    Mon Apr  4 22:44:57 2005
//
// Note: This file is produced automatically, and will be overwritten the next
// time you press "Generate" in System Generator.
//
PROJECT pid2sg_clk_wrapper
DESIGN pid2sg_clk_wrapper Normal
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
DEVGENERATEDSIMULATIONMODEL VHDL
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
LIBFILE conv_pkg.vhd work ***
LIBFILE clock_pkg.vhd work ***
SOURCE synth_reg.vhd
SOURCE synth_reg_w_init.vhd
SOURCE xlclkprobe.vhd
SOURCE xlclockdriver.vhd
SOURCE xlclockgenerator.vhd
SOURCE xlsl2slv.vhd
SOURCE xlslv2sl.vhd
SOURCE synth_addsub.vhd
SOURCE pid2sg_addsub1.vhd
SOURCE pid2sg_cmult3.vhd
SOURCE xldelay.vhd
SOURCE pid2sg.vhd
SOURCE pid2sg_clock_driver.vhd
SOURCE pid2sg_clk_wrapper.vhd
[STRATEGY-LIST]
Normal=True, 0
[Normal]
NetlistDoNotWriteNcf=leovhd, spartan2, VHDL.t_synthesize, 0, True
p_xstWriteTimingConstraints=xstvhd, spartan2, Schematic.t_synthesize, 0, True
p_xstBusDelimiter=xstvhd, virtex2, VHDL.t_synthesize, 0, ()
xilxMapPackRegInto=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 0, For Inputs and Outputs
_SynthConstraintsFile=xstvhd, spartan2, Schematic.t_synthesize, 0, .\pid2sg_clk_wrapper.xcf
