-- HIERARCHY
-- MODULE logic
-- ENDHIERARCHY


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity srl17e is
    generic (width : integer:=16;
             latency : integer :=8);
    port (clk   : in std_logic;
          ce    : in std_logic;
          d     : in std_logic_vector(width-1 downto 0);
          q     : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
    component SRL16E
        port (D   : in STD_ULOGIC;
              CE  : in STD_ULOGIC;
              CLK : in STD_ULOGIC;
              A0  : in STD_ULOGIC;
              A1  : in STD_ULOGIC;
              A2  : in STD_ULOGIC;
              A3  : in STD_ULOGIC;
              Q   : out STD_ULOGIC);
    end component;
    attribute syn_black_box of SRL16E : component is true;
    attribute fpga_dont_touch of SRL16E : component is "true";
    component FDE
        port(
            Q  :        out   STD_ULOGIC;
            D  :        in    STD_ULOGIC;
            C  :        in    STD_ULOGIC;
            CE :        in    STD_ULOGIC);
    end component;
    attribute syn_black_box of FDE : component is true;
    attribute fpga_dont_touch of FDE : component is "true";
    constant a : std_logic_vector(4 downto 0) :=
        integer_to_std_logic_vector(latency-2,5,xlSigned);
    signal d_delayed : std_logic_vector(width-1 downto 0);
    signal srl16_out : std_logic_vector(width-1 downto 0);
begin
    d_delayed <= d after 200 ps;
    reg_array : for i in 0 to width-1 generate
        srl16_used: if latency > 1 generate
            u1 : srl16e port map(clk => clk,
                                 d => d_delayed(i),
                                 q => srl16_out(i),
                                 ce => ce,
                                 a0 => a(0),
                                 a1 => a(1),
                                 a2 => a(2),
                                 a3 => a(3));
        end generate;
        srl16_not_used: if latency <= 1 generate
            srl16_out(i) <= d_delayed(i);
        end generate;
        fde_used: if latency /= 0  generate
            u2 : fde port map(c => clk,
                              d => srl16_out(i),
                              q => q(i),
                              ce => ce);
        end generate;
        fde_not_used: if latency = 0  generate
            q(i) <= srl16_out(i);
        end generate;
    end generate;
 end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
    generic (width           : integer := 8;
             latency         : integer := 1);
    port (i       : in std_logic_vector(width-1 downto 0);
          ce      : in std_logic;
          clr     : in std_logic;
          clk     : in std_logic;
          o       : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
    component srl17e
        generic (width : integer:=16;
                 latency : integer :=8);
        port (clk : in std_logic;
              ce  : in std_logic;
              d   : in std_logic_vector(width-1 downto 0);
              q   : out std_logic_vector(width-1 downto 0));
    end component;
    function calc_num_srl17es (latency : integer)
        return integer
    is
        variable remaining_latency : integer;
        variable result : integer;
    begin
        result := latency / 17;
        remaining_latency := latency - (result * 17);
        if (remaining_latency /= 0) then
            result := result + 1;
        end if;
        return result;
    end;
    constant complete_num_srl17es : integer := latency / 17;
    constant num_srl17es : integer := calc_num_srl17es(latency);
    constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
    type register_array is array (num_srl17es downto 0) of
        std_logic_vector(width-1 downto 0);
    signal z : register_array;
begin
    z(0) <= i;
    complete_ones : if complete_num_srl17es > 0 generate
        srl17e_array: for i in 0 to complete_num_srl17es-1 generate
            delay_comp : srl17e
                generic map (width => width,
                             latency => 17)
                port map (clk => clk,
                          ce  => ce,
                          d       => z(i),
                          q       => z(i+1));
        end generate;
    end generate;
    partial_one : if remaining_latency > 0 generate
        last_srl17e : srl17e
            generic map (width => width,
                         latency => remaining_latency)
            port map (clk => clk,
                      ce  => ce,
                      d   => z(num_srl17es-1),
                      q   => z(num_srl17es));
    end generate;
    o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
    generic (width           : integer := 8;
             latency         : integer := 1);
    port (i       : in std_logic_vector(width-1 downto 0);
          ce      : in std_logic;
          clr     : in std_logic;
          clk     : in std_logic;
          o       : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
  type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
  signal reg_bank : reg_array_type := (others => (others => '0'));
  signal reg_bank_in : reg_array_type := (others => (others => '0'));
  attribute syn_allow_retiming : boolean;
  attribute syn_srlstyle : string;
  attribute syn_allow_retiming of reg_bank : signal is true;
  attribute syn_allow_retiming of reg_bank_in : signal is true;
  attribute syn_srlstyle of reg_bank : signal is "registers";
  attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
  latency_eq_0: if latency = 0 generate
    o <= i;
  end generate latency_eq_0;
  latency_gt_0: if latency >= 1 generate
    o <= reg_bank(latency-1);
    reg_bank_in(0) <= i;
    loop_gen: for idx in latency-2 downto 0 generate
      reg_bank_in(idx+1) <= reg_bank(idx);
    end generate loop_gen;
    sync_loop: for sync_idx in latency-1 downto 0 generate
      sync_proc: process (clk)
      begin
        if clk'event and clk = '1' then
          if ce = '1'  then
            reg_bank(sync_idx) <= reg_bank_in(sync_idx);
          end if;
        end if;
      end process sync_proc;
    end generate sync_loop;
  end generate latency_gt_0;
end behav;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity single_reg_w_init is
  generic (
    width: integer := 8;
    init_index: integer := 0;
    init_value: bit_vector := b"0000"
  );
  port (
    i: in std_logic_vector(width - 1 downto 0);
    ce: in std_logic;
    clr: in std_logic;
    clk: in std_logic;
    o: out std_logic_vector(width - 1 downto 0)
  );
end single_reg_w_init;
architecture structural of single_reg_w_init is
  function build_init_const(width: integer;
                            init_index: integer;
                            init_value: bit_vector)
    return std_logic_vector
  is
    variable result: std_logic_vector(width - 1 downto 0);
  begin
    if init_index = 0 then
      result := (others => '0');
    elsif init_index = 1 then
      result := (others => '0');
      result(0) := '1';
    else
      result := to_stdlogicvector(init_value);
    end if;
    return result;
  end;
  component fdre
    port (
      q: out std_ulogic;
      d: in  std_ulogic;
      c: in  std_ulogic;
      ce: in  std_ulogic;
      r: in  std_ulogic
    );
  end component;
  attribute syn_black_box of fdre: component is true;
  attribute fpga_dont_touch of fdre: component is "true";
  component fdse
    port (
      q: out std_ulogic;
      d: in  std_ulogic;
      c: in  std_ulogic;
      ce: in  std_ulogic;
      s: in  std_ulogic
    );
  end component;
  attribute syn_black_box of fdse: component is true;
  attribute fpga_dont_touch of fdse: component is "true";
  constant init_const: std_logic_vector(width - 1 downto 0)
    := build_init_const(width, init_index, init_value);
begin
  fd_prim_array: for index in 0 to width - 1 generate
    bit_is_0: if (init_const(index) = '0') generate
      fdre_comp: fdre
        port map (
          c => clk,
          d => i(index),
          q => o(index),
          ce => ce,
          r => clr
        );
    end generate;
    bit_is_1: if (init_const(index) = '1') generate
      fdse_comp: fdse
        port map (
          c => clk,
          d => i(index),
          q => o(index),
          ce => ce,
          s => clr
        );
    end generate;
  end generate;
end architecture structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity synth_reg_w_init is
  generic (
    width: integer := 8;
    init_index: integer := 0;
    init_value: bit_vector := b"0000";
    latency: integer := 1
  );
  port (
    i: in std_logic_vector(width - 1 downto 0);
    ce: in std_logic;
    clr: in std_logic;
    clk: in std_logic;
    o: out std_logic_vector(width - 1 downto 0)
  );
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
  component single_reg_w_init
    generic (
      width: integer := 8;
      init_index: integer := 0;
      init_value: bit_vector := b"0000"
    );
    port (
      i: in std_logic_vector(width - 1 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      o: out std_logic_vector(width - 1 downto 0)
    );
  end component;
  signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
  signal dly_clr: std_logic;
begin
  latency_eq_0: if (latency = 0) generate
    o <= i;
  end generate;
  latency_gt_0: if (latency >= 1) generate
    dly_i((latency + 1) * width - 1 downto latency * width) <= i
      after 200 ps;
    dly_clr <= clr after 200 ps;
    fd_array: for index in latency downto 1 generate
       reg_comp: single_reg_w_init
          generic map (
            width => width,
            init_index => init_index,
            init_value => init_value
          )
          port map (
            clk => clk,
            i => dly_i((index + 1) * width - 1 downto index * width),
            o => dly_i(index * width - 1 downto (index - 1) * width),
            ce => ce,
            clr => dly_clr
          );
    end generate;
    o <= dly_i(width - 1 downto 0);
  end generate;
end structural;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;
entity xlclkprobe is
  port (clk             : in std_logic;
        clr             : in std_logic;
        ce              : in std_logic;
        fakeOutForXst   : out std_logic);
end xlclkprobe;
architecture behavior of xlclkprobe is
begin
   fakeOutForXst <= '0';
-- synopsys translate_off
   work.clock_pkg.int_clk <= clk;
-- synopsys translate_on
end behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
  generic (
    period: integer := 2;
    use_bufg: boolean := false
  );
  port (
    sysclk: in std_logic;
    sysclr: in std_logic;
    sysce: in std_logic;
    clk: out std_logic;
    clr: out std_logic;
    ce: out std_logic
  );
end xlclockdriver;
architecture behavior of xlclockdriver is
  component bufg
    port (
      i: in std_logic;
      o: out std_logic
    );
  end component;
  component synth_reg_w_init
    generic (
      width: integer;
      init_index: integer;
      init_value: bit_vector;
      latency: integer
    );
    port (
      i: in std_logic_vector(width - 1 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      o: out std_logic_vector(width - 1 downto 0)
    );
  end component;
  function size_of_uint(inp: integer; power_of_2: boolean)
    return integer
  is
    constant inp_vec: std_logic_vector(31 downto 0) :=
      integer_to_std_logic_vector(inp,32, xlUnsigned);
    variable result: integer;
  begin
    result := 32;
    for i in 0 to 31 loop
      if inp_vec(i) = '1' then
        result := i;
      end if;
    end loop;
    if power_of_2 then
      return result;
    else
      return result+1;
    end if;
  end;
  function is_power_of_2(inp: std_logic_vector)
    return boolean
  is
    constant width: integer := inp'length;
    variable vec: std_logic_vector(width - 1 downto 0);
    variable single_bit_set: boolean;
    variable more_than_one_bit_set: boolean;
    variable result: boolean;
  begin
    vec := inp;
    single_bit_set := false;
    more_than_one_bit_set := false;
    -- synopsys translate_off
    if (is_XorU(vec)) then
      return false;
    end if;
     -- synopsys translate_on
    if width > 0 then
      for i in 0 to width - 1 loop
        if vec(i) = '1' then
          if single_bit_set then
            more_than_one_bit_set := true;
          end if;
          single_bit_set := true;
        end if;
      end loop;
    end if;
    if (single_bit_set and not(more_than_one_bit_set)) then
      result := true;
    else
      result := false;
    end if;
    return result;
  end;
  constant period_floor: integer := max(2, period);
  constant power_of_2_counter: boolean :=
    is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
  constant cnt_width: integer :=
    size_of_uint(period_floor, power_of_2_counter);
  constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
    integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
  constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
    integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
  signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
  signal ce_vec, internal_ce: std_logic_vector(0 downto 0);
  signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
  clk <= sysclk;
  clr <= sysclr;
  cntr_gen: process(sysclk)
  begin
    if sysclk'event and sysclk = '1'  then
      if (sysce = '1') then
        if (cnt_clr_dly(0) = '1') then
          clk_num <= (others => '0');
        else
          clk_num <= clk_num + 1;
        end if;
    end if;
    end if;
  end process;
  clr_gen: process(clk_num, sysclr)
  begin
    if power_of_2_counter then
      cnt_clr(0) <= sysclr;
    else
      if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
          or sysclr = '1') then
        cnt_clr(0) <= '1';
      else
        cnt_clr(0) <= '0';
      end if;
    end if;
  end process;
  clr_reg: synth_reg_w_init
    generic map (
      width => 1,
      init_index => 0,
      init_value => b"0000",
      latency => 1
    )
    port map (
      i => cnt_clr,
      ce => sysce,
      clr => sysclr,
      clk => sysclk,
      o => cnt_clr_dly
    );
  non_pipelined_ce : if period = 2 generate
      ce_gen: process(clk_num)
      begin
          if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 then
              ce_vec(0) <= '1';
          else
              ce_vec(0) <= '0';
          end if;
      end process;
      ce_reg: synth_reg_w_init
          generic map (
              width => 1,
              init_index => 0,
              init_value => b"0000",
              latency => 1
              )
          port map (
              i => ce_vec,
              ce => sysce,
              clr => sysclr,
              clk => sysclk,
              o => internal_ce
              );
  end generate;
  pipelined_ce : if period > 2 generate
      ce_gen: process(clk_num)
      begin
          if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus2 then
              ce_vec(0) <= '1';
          else
              ce_vec(0) <= '0';
          end if;
      end process;
      ce_reg: synth_reg_w_init
          generic map (
              width => 1,
              init_index => 0,
              init_value => b"0000",
              latency => 2
              )
          port map (
              i => ce_vec,
              ce => sysce,
              clr => sysclr,
              clk => sysclk,
              o => internal_ce
              );
  end generate;
  use_bufg_true: if period > 1 and use_bufg generate
    ce_bufg_inst: bufg
      port map (
        i => internal_ce(0),
        o => ce
      );
  end generate;
  use_bufg_false: if period > 1 and not(use_bufg) generate
    ce <= internal_ce(0);
  end generate;
  generate_system_clk: if period = 1 generate
    ce <= sysce;
  end generate;
end architecture behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockgenerator is
    generic (ensure_clks_stable       : boolean := false;
             lcm_select               : integer := 0;
             frequency_mode           : string  := "low";
             clkdv_divide_generic     : real    := 2.0;
             clkdv_divide_attribute   : string  := "2.0";
             clkfx_multiply_generic   : integer := 4;
             clkfx_multiply_attribute : string  := "4";
             clkfx_divide_generic     : integer := 1;
             clkfx_divide_attribute   : string  := "1");
    port (clk   : in std_logic;
          rst   : in std_logic;
          clk0  : out std_logic;
          clk2x : out std_logic;
          clkfx : out std_logic;
          clkdv : out std_logic;
          lock  : out std_logic);
end xlclockgenerator;
architecture structural of xlclockgenerator is
   component bufg
      port(i: in std_logic;
           o: out std_logic);
   end component;
   component bufgmux
      port(i0 : in std_logic;
           i1 : in std_logic;
           s  : in std_logic;
           o  : out std_logic);
   end component;
   component dcm
      -- synopsys translate_off
      generic (clkout_phase_shift    : string := "fixed";
               dll_frequency_mode    : string := "low";
               duty_cycle_correction : boolean := true;
               clkdv_divide          : real := 2.0;
               clkfx_multiply        : integer := 4;
               clkfx_divide          : integer := 1);
      -- synopsys translate_on
      port (clkin    : in  std_logic;
            clkfb    : in  std_logic;
            dssen    : in  std_logic;
            psincdec : in  std_logic;
            psen     : in  std_logic;
            psclk    : in  std_logic;
            rst      : in  std_logic;
            clk0     : out std_logic;
            clk90    : out std_logic;
            clk180   : out std_logic;
            clk270   : out std_logic;
            clk2x    : out std_logic;
            clk2x180 : out std_logic;
            clkdv    : out std_logic;
            clkfx    : out std_logic;
            clkfx180 : out std_logic;
            locked   : out std_logic;
            psdone   : out std_logic;
            status   : out std_logic_vector(7 downto 0));
   end component;
   attribute dll_frequency_mode    : string;
   attribute duty_cycle_correction : string;
   attribute startup_wait          : string;
   attribute clkdv_divide          : string;
   attribute clkfx_multiply        : string;
   attribute clkfx_divide          : string;
   attribute duty_cycle_correction of dcm_comp1 : label is "true";
   attribute startup_wait of dcm_comp1          : label is "false";
   attribute dll_frequency_mode of dcm_comp1    : label is frequency_mode;
   attribute clkdv_divide of dcm_comp1   : label is clkdv_divide_attribute;
   attribute clkfx_multiply of dcm_comp1 : label is clkfx_multiply_attribute;
   attribute clkfx_divide of dcm_comp1   : label is clkfx_divide_attribute;
   component fdre
      port(q  : out   std_ulogic;
           d  : in    std_ulogic;
           c  : in    std_ulogic;
           r  : in    std_ulogic;
           ce : in    std_ulogic);
   end component;
   signal feedback    : std_logic;
   signal clklcm      : std_logic;
   signal clk0unbuf   : std_logic;
   signal clk0buf     : std_logic;
   signal clk2xunbuf  : std_logic;
   signal clkfxunbuf  : std_logic;
   signal clkdvunbuf  : std_logic;
   signal clkswitch   : std_logic;
   signal intlock     : std_logic;
begin
   dcm_comp1: dcm
      -- synopsys translate_off
      generic map (dll_frequency_mode => frequency_mode,
                   clkdv_divide       => clkdv_divide_generic,
                   clkfx_multiply     => clkfx_multiply_generic,
                   clkfx_divide       => clkfx_divide_generic)
      -- synopsys translate_on
      port map (clkin    => clk,
                clkfb    => feedback,
                dssen    => '0',
                psincdec => '0',
                psen     => '0',
                psclk    => '0',
                rst      => rst,
                clk0     => clk0unbuf,
                clk2x    => clk2xunbuf,
                clkfx    => clkfxunbuf,
                clkdv    => clkdvunbuf,
                locked   => intlock);
   bufgmux_clk0: bufgmux
      port map (i0 => '0',
                i1 => clk0unbuf,
                o  => clk0buf,
                s  => clkswitch);
   bufgmux_clk2x: bufgmux
      port map (i0 => '0',
                i1 => clk2xunbuf,
                o  => clk2x,
                s  => clkswitch);
   bufgmux_clkfx: bufgmux
      port map (i0 => '0',
                i1 => clkfxunbuf,
                o  => clkfx,
                s  => clkswitch);
   bufgmux_clkdv: bufgmux
      port map (i0 => '0',
                i1 => clkdvunbuf,
                o  => clkdv,
                s  => clkswitch);
   stability_req: if (ensure_clks_stable = true) generate
      mux_ctrl_reg: fdre
         port map (d  => intlock,
                   q  => clkswitch,
                   ce => '1',
                   c  => clklcm,
                   r  => rst);
      bufg_feedback: bufg
         port map(i => clk0unbuf,
                  o => feedback);
      lcm_is_clk0: if (lcm_select = 0) generate
         clklcm <= feedback;
      end generate;
      lcm_is_clkdv: if (lcm_select = 1) generate
         bufg_lcmclk: bufg
            port map(i => clkdvunbuf,
                     o => feedback);
      end generate;
   end generate;
   stability_not_req: if (ensure_clks_stable = false) generate
      feedback  <= clk0buf;
      clkswitch <= '1';
   end generate;
   lock <= intlock;
   clk0 <= clk0buf;
end architecture structural;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlsl2slv is
  generic (
    dout_width: integer := 1;
    dout_bin_pt: integer := 0;
    dout_arith: integer := xlUnsigned
  );
  port (
    din: in std_logic;
    dout: out std_logic_vector(dout_width - 1 downto 0)
  );
end xlsl2slv;
architecture behavior of xlsl2slv is
begin
    dout(0) <= din;
end behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslv2sl is
  generic (
    din_width: integer := 1;
    din_bin_pt: integer := 0;
    din_arith: integer := xlUnsigned
  );
  port (
    din: in std_logic_vector(din_width - 1 downto 0);
    dout: out std_logic
  );
end xlslv2sl;
architecture behavior of xlslv2sl is
begin
    dout <= din(0);
end behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlinv is
   generic (din_width   : integer := 12;
            din_bin_pt  : integer := 7;
            din_arith   : integer := xlSigned;
            dout_width  : integer := 12;
            dout_bin_pt : integer := 7;
            dout_arith  : integer := xlSigned;
            en_width    : integer := 5;
            en_bin_pt   : integer := 2;
            en_arith    : integer := xlUnsigned;
            latency     : integer := 1);
   port (din  : in std_logic_vector (din_width-1 downto 0);
         dout : out std_logic_vector (dout_width-1 downto 0);
         ce   : in std_logic;
         clr  : in std_logic;
         clk  : in std_logic;
         en   : in std_logic_vector (en_width-1 downto 0));
end xlinv;
architecture dataflow of xlinv is
   component synth_reg
      generic (width   : integer;
               latency : integer);
      port (i   : in std_logic_vector(width-1 downto 0);
            ce  : in std_logic;
            clr : in std_logic;
            clk : in std_logic;
            o   : out std_logic_vector(width-1 downto 0));
   end component;
   signal dout_unreg : std_logic_vector (dout_width-1 downto 0);
   signal dout_reg   : std_logic_vector (dout_width-1 downto 0);
   signal block_ce   : std_logic;
begin
   block_ce <= ce and en(0);
   dout_unreg <= not(din);
   latency_gt_0 : if (latency > 0) generate
      reg_inst : synth_reg
         generic map (width   => dout_width,
                      latency => 1)
         port map (i   => dout_unreg,
                   ce  => block_ce,
                   clr => clr,
                   clk => clk,
                   o   => dout_reg);
   end generate;
   latency_eq_0 : if (latency = 0) generate
      dout_reg <= dout_unreg;
   end generate;
   extra_latency : if (latency > 1) generate
      latency_pipe : synth_reg
         generic map (width   => dout_width,
                      latency => latency-1)
         port map (i   => dout_reg,
                   ce  => block_ce,
                   clr => clr,
                   clk => clk,
                   o   => dout);
   end generate;
   no_extra_latency : if (latency = 0 or latency = 1) generate
      dout <= dout_reg;
   end generate;
end architecture dataflow;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xllogical2 is
   generic (din0_width   : integer := 12;
            din0_bin_pt  : integer := 7;
            din0_arith   : integer := xlSigned;
            din1_width   : integer := 12;
            din1_bin_pt  : integer := 7;
            din1_arith   : integer := xlSigned;
            dout_width   : integer := 12;
            dout_bin_pt  : integer := 7;
            dout_arith   : integer := xlSigned;
            en_width     : integer := 1;
            en_bin_pt    : integer := 0;
            en_arith     : integer := xlUnsigned;
            full_width   : integer := 12;
            full_arith   : integer := xlUnsigned;
            full_bin_pt  : integer := 0;
            num_inputs   : integer := 2;
            latency      : integer := 2;
            gate_type    : integer := 0);
   port (din0       : in std_logic_vector (din0_width-1 downto 0);
         din1       : in std_logic_vector (din1_width-1 downto 0);
         dout       : out std_logic_vector (dout_width-1 downto 0);
         en         : in std_logic_vector(en_width-1 downto 0);
         ce         : in std_logic;
         clr        : in std_logic;
         clk        : in std_logic);
end xllogical2;
architecture behavior of xllogical2 is
   component synth_reg
      generic (width   : integer;
               latency : integer);
      port (i   : in std_logic_vector(width-1 downto 0);
            ce  : in std_logic;
            clr : in std_logic;
            clk : in std_logic;
            o   : out std_logic_vector(width-1 downto 0));
   end component;
   signal full_din0       : std_logic_vector (full_width-1 downto 0);
   signal full_din1       : std_logic_vector (full_width-1 downto 0);
   signal full_dout_unreg : std_logic_vector (full_width-1 downto 0);
   signal full_dout_reg   : std_logic_vector (full_width-1 downto 0);
   signal user_dout       : std_logic_vector (dout_width-1 downto 0);
   signal block_ce        : std_logic;
   constant quantization    : integer := xlTruncate;
   constant overflow        : integer := xlWrap;
begin
   block_ce  <= ce and en(0);
   full_din0 <= align_input(din0, din0_width, full_bin_pt - din0_bin_pt,
                            din0_arith, full_width);
   full_din1 <= align_input(din1, din1_width, full_bin_pt - din1_bin_pt,
                            din1_arith, full_width);
   AND_gate : if (gate_type = 0) generate
      full_dout_unreg <= full_din0 and full_din1;
   end generate;
   NAND_gate : if (gate_type = 1) generate
      full_dout_unreg <= not(full_din0 and full_din1);
   end generate;
   OR_gate : if (gate_type = 2) generate
      full_dout_unreg <= full_din0 or full_din1;
   end generate;
   NOR_gate : if (gate_type = 3) generate
      full_dout_unreg <= not(full_din0 or full_din1);
   end generate;
   XOR_gate : if (gate_type = 4) generate
      full_dout_unreg <= full_din0 xor full_din1;
   end generate;
   XNOR_gate : if (gate_type = 5) generate
      full_dout_unreg <= not(full_din0 xor full_din1);
   end generate;
   latency_gt_0 : if (latency > 0) generate
      reg_inst : synth_reg
         generic map (width   => full_width,
                      latency => 1)
         port map (i   => full_dout_unreg,
                   ce  => block_ce,
                   clr => clr,
                   clk => clk,
                   o   => full_dout_reg);
   end generate;
   latency_eq_0 : if (latency = 0) generate
      full_dout_reg <= full_dout_unreg;
   end generate;
   user_dout <= convert_type(full_dout_reg, full_width, full_bin_pt, full_arith,
                             dout_width, dout_bin_pt, dout_arith, quantization,
                             overflow);
   extra_latency : if (latency > 1) generate
      latency_pipe : synth_reg
         generic map (width   => dout_width,
                      latency => latency-1)
         port map (i   => user_dout,
                   ce  => block_ce,
                   clr => clr,
                   clk => clk,
                   o   => dout);
   end generate;
   no_extra_latency : if (latency = 0 or latency = 1) generate
      dout <= user_dout;
   end generate;
end architecture behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xllogical3 is
   generic (din0_width   : integer := 12;
            din0_bin_pt  : integer := 7;
            din0_arith   : integer := xlSigned;
            din1_width   : integer := 12;
            din1_bin_pt  : integer := 7;
            din1_arith   : integer := xlSigned;
            din2_width   : integer := 12;
            din2_bin_pt  : integer := 7;
            din2_arith   : integer := xlSigned;
            dout_width   : integer := 12;
            dout_bin_pt  : integer := 7;
            dout_arith   : integer := xlSigned;
            en_width     : integer := 1;
            en_bin_pt    : integer := 0;
            en_arith     : integer := xlUnsigned;
            full_width   : integer := 12;
            full_arith   : integer := xlUnsigned;
            full_bin_pt  : integer := 0;
            num_inputs   : integer := 2;
            latency      : integer := 1;
            gate_type    : integer := 0);
   port (din0       : in std_logic_vector (din0_width-1 downto 0);
         din1       : in std_logic_vector (din1_width-1 downto 0);
         din2       : in std_logic_vector (din2_width-1 downto 0);
         dout       : out std_logic_vector (dout_width-1 downto 0);
         en         : in std_logic_vector(en_width-1 downto 0);
         ce         : in std_logic;
         clr        : in std_logic;
         clk        : in std_logic);
end xllogical3;
architecture behavior of xllogical3 is
   component synth_reg
      generic (width   : integer;
               latency : integer);
      port (i   : in std_logic_vector(width-1 downto 0);
            ce  : in std_logic;
            clr : in std_logic;
            clk : in std_logic;
            o   : out std_logic_vector(width-1 downto 0));
   end component;
   signal full_din0       : std_logic_vector (full_width-1 downto 0);
   signal full_din1       : std_logic_vector (full_width-1 downto 0);
   signal full_din2       : std_logic_vector (full_width-1 downto 0);
   signal full_dout_unreg : std_logic_vector (full_width-1 downto 0);
   signal full_dout_reg   : std_logic_vector (full_width-1 downto 0);
   signal user_dout       : std_logic_vector (dout_width-1 downto 0);
   signal block_ce        : std_logic;
   constant quantization    : integer := xlTruncate;
   constant overflow        : integer := xlWrap;
begin
   block_ce  <= ce and en(0);
   full_din0 <= align_input(din0, din0_width, full_bin_pt - din0_bin_pt,
                            din0_arith, full_width);
   full_din1 <= align_input(din1, din1_width, full_bin_pt - din1_bin_pt,
                            din1_arith, full_width);
   full_din2 <= align_input(din2, din2_width, full_bin_pt - din2_bin_pt,
                            din2_arith, full_width);
   AND_gate : if (gate_type = 0) generate
      full_dout_unreg <= full_din0 and full_din1 and full_din2;
   end generate;
   NAND_gate : if (gate_type = 1) generate
      full_dout_unreg <= not(full_din0 and full_din1 and full_din2);
   end generate;
   OR_gate : if (gate_type = 2) generate
      full_dout_unreg <= full_din0 or full_din1 or full_din2;
   end generate;
   NOR_gate : if (gate_type = 3) generate
      full_dout_unreg <= not(full_din0 or full_din1 or full_din2);
   end generate;
   XOR_gate : if (gate_type = 4) generate
      full_dout_unreg <= full_din0 xor full_din1 xor full_din2;
   end generate;
   XNOR_gate : if (gate_type = 5) generate
      full_dout_unreg <= not(full_din0 xor full_din1 xor full_din2);
   end generate;
   latency_gt_0 : if (latency > 0) generate
      reg_inst : synth_reg
         generic map (width   => full_width,
                      latency => 1)
         port map (i   => full_dout_unreg,
                   ce  => block_ce,
                   clr => clr,
                   clk => clk,
                   o   => full_dout_reg);
   end generate;
   latency_eq_0 : if (latency = 0) generate
      full_dout_reg <= full_dout_unreg;
   end generate;
   user_dout <= convert_type(full_dout_reg, full_width, full_bin_pt, full_arith,
                             dout_width, dout_bin_pt, dout_arith, quantization,
                             overflow);
   extra_latency : if (latency > 1) generate
      latency_pipe : synth_reg
         generic map (width   => dout_width,
                      latency => latency-1)
         port map (i   => user_dout,
                   ce  => block_ce,
                   clr => clr,
                   clk => clk,
                   o   => dout);
   end generate;
   no_extra_latency : if (latency = 0 or latency = 1) generate
      dout <= user_dout;
   end generate;
end architecture behavior;


-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2005 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2005 Xilinx, Inc. 
-- All rights reserved.
--------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;

entity logic is
  port (
    gateway_in: in std_logic_vector(7 downto 0);
    gateway_in1: in std_logic_vector(7 downto 0);
    gateway_in2: in std_logic_vector(7 downto 0);
    gateway_in3: in std_logic_vector(7 downto 0);
    gateway_out: out std_logic_vector(7 downto 0);
    gateway_out1: out std_logic_vector(7 downto 0)
  );
end logic;

architecture structural of logic is
  signal dout: std_logic_vector(7 downto 0);
  signal dout_x_0: std_logic_vector(7 downto 0);
  signal dout_x_1: std_logic_vector(7 downto 0);
  signal dout_x_10: std_logic_vector(0 downto 0);
  signal dout_x_2: std_logic_vector(7 downto 0);
  signal dout_x_3: std_logic_vector(7 downto 0);
  signal dout_x_4: std_logic_vector(7 downto 0);
  signal dout_x_5: std_logic_vector(0 downto 0);
  signal dout_x_6: std_logic_vector(0 downto 0);
  signal dout_x_7: std_logic_vector(0 downto 0);
  signal dout_x_8: std_logic_vector(0 downto 0);
  signal dout_x_9: std_logic_vector(0 downto 0);
  signal gateway_in1_x_0: std_logic_vector(7 downto 0);
  signal gateway_in2_x_0: std_logic_vector(7 downto 0);
  signal gateway_in3_x_0: std_logic_vector(7 downto 0);
  signal gateway_in_x_0: std_logic_vector(7 downto 0);

begin
  gateway_in_x_0 <= gateway_in;
  gateway_in1_x_0 <= gateway_in1;
  gateway_in2_x_0 <= gateway_in2;
  gateway_in3_x_0 <= gateway_in3;
  gateway_out <= dout_x_4;
  gateway_out1 <= dout_x_0;

  inverter: entity work.xlinv
    generic map (
      din_width => 8,
      din_arith => xlSigned,
      din_bin_pt => 6,
      dout_width => 8,
      dout_arith => xlSigned,
      dout_bin_pt => 6,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      latency => 0
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => gateway_in2_x_0,
      en => dout_x_5,
      dout => dout
    );
  inverter1: entity work.xlinv
    generic map (
      din_width => 8,
      din_arith => xlSigned,
      din_bin_pt => 6,
      dout_width => 8,
      dout_arith => xlSigned,
      dout_bin_pt => 6,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      latency => 0
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dout_x_1,
      en => dout_x_6,
      dout => dout_x_0
    );
  logical: entity work.xllogical3
    generic map (
      din0_width => 8,
      din0_arith => xlSigned,
      din0_bin_pt => 6,
      din1_width => 8,
      din1_arith => xlSigned,
      din1_bin_pt => 6,
      din2_width => 8,
      din2_arith => xlSigned,
      din2_bin_pt => 6,
      dout_width => 8,
      dout_arith => xlSigned,
      dout_bin_pt => 6,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      full_arith => xlSigned,
      full_bin_pt => 6,
      full_width => 8,
      gate_type => 1,
      latency => 0,
      num_inputs => 3
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din0 => gateway_in3_x_0,
      din1 => dout,
      din2 => dout_x_2,
      en => dout_x_10,
      dout => dout_x_1
    );
  logical1: entity work.xllogical2
    generic map (
      din0_width => 8,
      din0_arith => xlSigned,
      din0_bin_pt => 6,
      din1_width => 8,
      din1_arith => xlSigned,
      din1_bin_pt => 6,
      dout_width => 8,
      dout_arith => xlSigned,
      dout_bin_pt => 6,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      full_arith => xlSigned,
      full_bin_pt => 6,
      full_width => 8,
      gate_type => 2,
      latency => 0,
      num_inputs => 2
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din0 => gateway_in_x_0,
      din1 => gateway_in1_x_0,
      en => dout_x_7,
      dout => dout_x_2
    );
  logical2: entity work.xllogical2
    generic map (
      din0_width => 8,
      din0_arith => xlSigned,
      din0_bin_pt => 6,
      din1_width => 8,
      din1_arith => xlSigned,
      din1_bin_pt => 6,
      dout_width => 8,
      dout_arith => xlSigned,
      dout_bin_pt => 6,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      full_arith => xlSigned,
      full_bin_pt => 6,
      full_width => 8,
      gate_type => 1,
      latency => 0,
      num_inputs => 2
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din0 => gateway_in_x_0,
      din1 => gateway_in1_x_0,
      en => dout_x_8,
      dout => dout_x_3
    );
  logical3: entity work.xllogical2
    generic map (
      din0_width => 8,
      din0_arith => xlSigned,
      din0_bin_pt => 6,
      din1_width => 8,
      din1_arith => xlSigned,
      din1_bin_pt => 6,
      dout_width => 8,
      dout_arith => xlSigned,
      dout_bin_pt => 6,
      en_width => 1,
      en_arith => xlUnsigned,
      en_bin_pt => 0,
      full_arith => xlSigned,
      full_bin_pt => 6,
      full_width => 8,
      gate_type => 1,
      latency => 0,
      num_inputs => 2
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din0 => dout_x_0,
      din1 => dout_x_3,
      en => dout_x_9,
      dout => dout_x_4
    );
  x: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_5
    );
  x_x_0: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_6
    );
  x_x_1: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_7
    );
  x_x_2: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_8
    );
  x_x_3: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_9
    );
  x_x_4: entity work.xlsl2slv
    generic map (
      dout_width => 1,
      dout_arith => xlUnsigned,
      dout_bin_pt => 0
    )
    port map (
      din => '1',
      dout => dout_x_10
    );
end structural;

