module clk_d10ms (clock_sys, clock_div10ms);

input clock_sys;
output clock_div10ms;

reg [18:0] clock_cnt;
reg  clock_div10ms;
integer count = 0;

always @ (posedge clock_sys)
begin
		clock_cnt <= clock_cnt + 1;
end


always @ (posedge clock_sys)
begin
     if (clock_cnt==250000)
	     begin
            if (count < 1500)
                clock_div10ms = !clock_div10ms;
                count = count + 1;
                end
end

endmodule
