
-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
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-------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xldelay is
   generic(d_width    : integer := 5;
           d_bin_pt   : integer := 2;
           d_arith    : integer := xlUnsigned;
           q_width    : integer := 5;
           q_bin_pt   : integer := 2;
           q_arith    : integer := xlUnsigned;
           rst_width  : integer := 1;
           rst_bin_pt : integer := 0;
           en_width   : integer := 5;
           en_bin_pt  : integer := 2;
           en_arith   : integer := xlUnsigned;
           rst_arith  : integer := xlUnsigned;
           latency    : integer := 10;
           reg_retiming: boolean := false);
   port(d       : in std_logic_vector (d_width-1 downto 0);
        ce      : in std_logic;
        clr     : in std_logic;
        clk     : in std_logic;
        rst     : in std_logic_vector (rst_width-1 downto 0);
        en      : in std_logic_vector (en_width-1 downto 0);
        q       : out std_logic_vector (q_width-1 downto 0));
end xldelay;
architecture behavior of xldelay is
   component synth_reg
      generic (width       : integer;
               latency     : integer);
      port (i           : in std_logic_vector(width-1 downto 0);
            ce      : in std_logic;
            clr     : in std_logic;
            clk     : in std_logic;
            o       : out std_logic_vector(width-1 downto 0));
   end component;
   component synth_reg_reg
      generic (width       : integer;
               latency     : integer);
      port (i           : in std_logic_vector(width-1 downto 0);
            ce      : in std_logic;
            clr     : in std_logic;
            clk     : in std_logic;
            o       : out std_logic_vector(width-1 downto 0));
   end component;
   signal internal_ce  : std_logic;
   signal internal_clr : std_logic;
begin
   internal_ce  <= ce and (en(0));
   internal_clr <= (clr or (rst(0))) and ce;
   srl_delay: if (not reg_retiming) or (latency<1) generate
     synth_reg_srl_inst : synth_reg
       generic map (
         width   => d_width,
         latency => latency)
       port map (
         i   => d,
         ce  => internal_ce,
         clr => internal_clr,
         clk => clk,
         o   => q);
   end generate srl_delay;
   reg_delay: if reg_retiming and (latency>=1) generate
     synth_reg_reg_inst : synth_reg_reg
       generic map (
         width   => d_width,
         latency => latency)
       port map (
         i   => d,
         ce  => internal_ce,
         clr => internal_clr,
         clk => clk,
         o   => q);
   end generate reg_delay;
end architecture behavior;
