library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;

--*****************************************************************************
--** ENTITY branch
--**
--** Deskripsi: menggambarkan instruksi branching mana yang digunakan.
--*****************************************************************************
ENTITY branch IS
    PORT(pc, displacement            : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
            reg            : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
         bsel                             : IN STD_LOGIC;
         newPC                            : OUT STD_LOGIC_VECTOR(16 DOWNTO 0));
END ENTITY branch;

ARCHITECTURE branch_behav OF branch IS
BEGIN
    name : PROCESS(pc, displacement,reg,bsel) IS
    
    BEGIN
        IF(bsel='1') THEN
            newPC <= UNSIGNED(pc) + SIGNED(displacement);
        ELSE
            newPC <= reg ;
        END IF;
    END PROCESS name;
END ARCHITECTURE branch_behav;
