-- C:\MATLAB6P5\WORK\ISNIAMY\XPID_DATA2
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Mon May 23 12:53:56 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.CONV_PKG.ALL;
USE WORK.CLOCK_PKG.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test4_tbw IS
END test4_tbw;

ARCHITECTURE testbench_arch OF test4_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\matlab6p5\work\isniamy\xpid_data2\test4_tbw.ano";
	COMPONENT pid_sysgen_clk_wrapper
		PORT (
			ce : In  std_logic;
			clk : In  std_logic;
			gateway_in1 : In  std_logic_vector (15 DOWNTO 0);
			gateway_out : Out  std_logic_vector (23 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL ce : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL gateway_in1 : std_logic_vector (15 DOWNTO 0);
	SIGNAL gateway_out : std_logic_vector (23 DOWNTO 0);

BEGIN
	UUT : pid_sysgen_clk_wrapper
	PORT MAP (
		ce => ce,
		clk => clk,
		gateway_in1 => gateway_in1,
		gateway_out => gateway_out
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_gateway_out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",gateway_out,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, gateway_out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 1 ms;
		TX_TIME := TX_TIME + 1;
		clk <= transport '1';
		WAIT FOR 1 ms;
		TX_TIME := TX_TIME + 1;
		ANNOTATE_gateway_out(TX_TIME);
		WAIT FOR 4 ms;
		TX_TIME := TX_TIME + 4;
		clk <= transport '0';
		WAIT FOR 4 ms;
		TX_TIME := TX_TIME + 4;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		ce <= transport '1';
		gateway_in1 <= transport std_logic_vector'("0000011000000000"); --600
		-- --------------------
		WAIT FOR 10 ms; -- Time=10 ms
		gateway_in1 <= transport std_logic_vector'("0000011100000000"); --700
		-- --------------------
		WAIT FOR 10 ms; -- Time=20 ms
		gateway_in1 <= transport std_logic_vector'("0000100000000000"); --800
		-- --------------------
		WAIT FOR 10 ms; -- Time=30 ms
		gateway_in1 <= transport std_logic_vector'("0000100100000000"); --900
		-- --------------------
		WAIT FOR 10 ms; -- Time=40 ms
		gateway_in1 <= transport std_logic_vector'("0000101000000000"); --A00
		-- --------------------
		WAIT FOR 10 ms; -- Time=50 ms
		gateway_in1 <= transport std_logic_vector'("0000101100000000"); --B00
		-- --------------------
		WAIT FOR 10 ms; -- Time=60 ms
		gateway_in1 <= transport std_logic_vector'("0000110000000000"); --C00
		-- --------------------
		WAIT FOR 10 ms; -- Time=70 ms
		gateway_in1 <= transport std_logic_vector'("0000110100000000"); --D00
		-- --------------------
		WAIT FOR 10 ms; -- Time=80 ms
		gateway_in1 <= transport std_logic_vector'("0000111000000000"); --E00
		-- --------------------
		WAIT FOR 10 ms; -- Time=90 ms
		gateway_in1 <= transport std_logic_vector'("0000111100000000"); --F00
		-- --------------------
		WAIT FOR 10 ms; -- Time=100 ms
		ce <= transport '0';
		gateway_in1 <= transport std_logic_vector'("0000110100000011"); --D03
		-- --------------------
		WAIT FOR 10 ms; -- Time=110 ms
		gateway_in1 <= transport std_logic_vector'("0000110100000100"); --D04
		-- --------------------
		WAIT FOR 10 ms; -- Time=120 ms
		gateway_in1 <= transport std_logic_vector'("0000110100000101"); --D05
		-- --------------------
		WAIT FOR 10 ms; -- Time=130 ms
		gateway_in1 <= transport std_logic_vector'("0000110100000110"); --D06
		-- --------------------
		WAIT FOR 10 ms; -- Time=140 ms
		gateway_in1 <= transport std_logic_vector'("0000110100000111"); --D07
		-- --------------------
		WAIT FOR 11 ms; -- Time=151 ms
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION pid_sysgen_clk_wrapper_cfg OF test4_tbw IS
	FOR testbench_arch
	END FOR;
END pid_sysgen_clk_wrapper_cfg;
