
Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
ERROR:Pack:12 - The RLOC value of R19C0.S1 on component
   test1_pid_top_addsub5_core_instance6/N20 in RPM
   test1_pid_top_addsub5_core_instance6/hset creates a macro that is too large
   for the device.  Use a bigger device.
ERROR:Pack:12 - The RLOC value of R20C0.S1 on component
   test1_pid_top_addsub4_core_instance6/N10 in RPM
   test1_pid_top_addsub4_core_instance6/hset creates a macro that is too large
   for the device.  Use a bigger device.
Problem encountered generating the NCD.

Mapping completed.
See MAP report file "test1_pid_clk_wrapper_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   2
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module test1_pid_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o test1_pid_clk_wrapper_map.ncd test1_pid_clk_wrapper.ngd test1_pid_clk_wrapper.pcf
Mapping Module test1_pid_clk_wrapper: failed

