-- D:\ENGINEERING\WORK\NASWI\XSKRIPSI
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sat Jul 23 18:38:53 2005
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY tv1_tbw IS
END tv1_tbw;

ARCHITECTURE testbench_arch OF tv1_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT top_level2
		PORT (
			ce_sg_n : In  std_logic;
			clk_sg : In  std_logic;
			in_x_0 : In  std_logic_vector (15 DOWNTO 0);
			reset : In  std_logic;
			anode0 : Out  std_logic;
			anode1 : Out  std_logic;
			anode2 : Out  std_logic;
			anode3 : Out  std_logic;
			cathode : Out  std_logic_vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL ce_sg_n : std_logic;
	SIGNAL clk_sg : std_logic;
	SIGNAL in_x_0 : std_logic_vector (15 DOWNTO 0);
	SIGNAL reset : std_logic;
	SIGNAL anode0 : std_logic;
	SIGNAL anode1 : std_logic;
	SIGNAL anode2 : std_logic;
	SIGNAL anode3 : std_logic;
	SIGNAL cathode : std_logic_vector (7 DOWNTO 0);

BEGIN
	UUT : top_level2
	PORT MAP (
		ce_sg_n => ce_sg_n,
		clk_sg => clk_sg,
		in_x_0 => in_x_0,
		reset => reset,
		anode0 => anode0,
		anode1 => anode1,
		anode2 => anode2,
		anode3 => anode3,
		cathode => cathode
	);

	PROCESS -- clock process for clk_sg,
	BEGIN
		CLOCK_LOOP : LOOP
		clk_sg <= transport '0';
		WAIT FOR 10 ns;
		clk_sg <= transport '1';
		WAIT FOR 10 ns;
		WAIT FOR 40 ns;
		clk_sg <= transport '0';
		WAIT FOR 40 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk_sg
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_anode0(
			next_anode0 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (anode0 /= next_anode0) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns anode0="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, anode0);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_anode0);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_anode1(
			next_anode1 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (anode1 /= next_anode1) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns anode1="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, anode1);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_anode1);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_anode2(
			next_anode2 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (anode2 /= next_anode2) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns anode2="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, anode2);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_anode2);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_anode3(
			next_anode3 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (anode3 /= next_anode3) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns anode3="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, anode3);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_anode3);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_cathode(
			next_cathode : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (cathode /= next_cathode) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns cathode="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, cathode);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_cathode);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		ce_sg_n <= transport '1';
		in_x_0 <= transport std_logic_vector'("0000000000000000"); --0
		reset <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		in_x_0 <= transport std_logic_vector'("0001001000110100"); --1234
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		in_x_0 <= transport std_logic_vector'("0000000100010001"); --111
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		in_x_0 <= transport std_logic_vector'("0000000000110011"); --33
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		in_x_0 <= transport std_logic_vector'("0001000000010000"); --1010
		-- --------------------
		WAIT FOR 500 ns; -- Time=900 ns
		ce_sg_n <= transport '0';
		-- --------------------
		WAIT FOR 110 ns; -- Time=1010 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION top_level2_cfg OF tv1_tbw IS
	FOR testbench_arch
	END FOR;
END top_level2_cfg;
