JDF G
// Created by Project Navigator ver 1.0
PROJECT simple1_clk_wrapper.npl
DESIGN simple1_clk_wrapper2
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE simple1_pkgs.vhd
SOURCE simple1_files.vhd
SOURCE simple1_clk_wrapper.vhd
SOURCE clk_div.v
SOURCE ..\xsimple1_1\top_level2.sch
SOURCE seg7_driver.v
SOURCE top_level2.sch
STIMULUS tv1_tbw.tbw
DEPASSOC simple1_clk_wrapper simple1_clk_wrapper.ucf
DEPASSOC top_level2 top_level2.ucf
[STATUS-ALL]
simple1_clk_wrapper.ncdFile=WARNINGS,1122003457
simple1_clk_wrapper.ngcFile=WARNINGS,1122003427
simple1_clk_wrapper.ngdFile=WARNINGS,1122003447
[STRATEGY-LIST]
Normal=True
