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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslv2sl is
  generic (
    din_width: integer := 1;
    din_bin_pt: integer := 0;
    din_arith: integer := xlUnsigned
  );
  port (
    din: in std_logic_vector(din_width - 1 downto 0);
    dout: out std_logic
  );
end xlslv2sl;
architecture behavior of xlslv2sl is
begin
    dout <= din(0);
end behavior;
