module clk_div (clock_sys, reset, clock_div);

// diasumsikan clk_sys 50Mhz -> clock_div ~ 50Hz
// parameter n = 20;

input clock_sys,reset;
output clock_div;

reg [17:0] clock_cnt;
wire clock_div;

always @ (posedge clock_sys or posedge reset)
begin
	if (reset)
		clock_cnt <= 0;
	else
		clock_cnt <= clock_cnt + 1;
end

assign clock_div = clock_cnt[17];

endmodule
