Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_div.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "seg7_driver.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <simple1_addsub1> (Architecture <behavior>) compiled.
Entity <simple1_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <simple1> (Architecture <structural>) compiled.
Entity <simple1_clock_driver> (Architecture <structural>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "seg7_driver.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "clk_div.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/top_level2.vhf in Library work.
Entity <top_level2> (Architecture <BEHAVIORAL>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_level2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_level2> (Architecture <BEHAVIORAL>).
WARNING:Xst:37 - Unknown property "n".
WARNING:Xst:37 - Unknown property "n".
Entity <top_level2> analyzed. Unit <top_level2> generated.

Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\simple1_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_136>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <simple1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <top_level2>.
    Related source file is D:/isnique/work/xskripsi/top_level2.vhf.
Unit <top_level2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_86c498140491d6df.edn" "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.edn" "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.edn" "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.edn" "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_fe654cf32dc31d3a.edn" "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_e880a1b4a8ae9201.edn" "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_22d1b55eb2467aac.edn" "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_level2> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\simple1_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 23.09 / 24.72 s | Elapsed : 23.00 / 25.00 s
 
--> 

Total memory usage is 70504 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/top_level2.vhf in Library work.
Architecture behavioral of Entity top_level2 is up to date.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_level2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_level2> (Architecture <behavioral>).
WARNING:Xst:37 - Unknown property "n".
WARNING:Xst:37 - Unknown property "n".
Entity <top_level2> analyzed. Unit <top_level2> generated.

Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\simple1_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_136>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <simple1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <top_level2>.
    Related source file is D:/isnique/work/xskripsi/top_level2.vhf.
Unit <top_level2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_level2> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\simple1_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block top_level2, actual ratio is 32.
FlipFlop XLXI_3_anode0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_3_anode1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_3_anode2 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     255  out of    768    33%  
 Number of Slice Flip Flops:            59  out of   1536     3%  
 Number of 4 input LUTs:               439  out of   1536    28%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_sg                             | BUFGP                  | 50    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.129ns (Maximum Frequency: 194.970MHz)
   Minimum input arrival time before clock: 6.581ns
   Maximum output required time after clock: 27.978ns
   Maximum combinational path delay: 29.514ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -i -p
xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_86c498140491d6df.edn"
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xskripsi/_ngo/adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_9b2656d23c19deaf.edn"
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xskripsi/_ngo/adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.edn"
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xskripsi/_ngo/adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa
"adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.edn"
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xskripsi/_ngo/adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_fe654cf32dc31d3a.edn"
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xskripsi/_ngo/multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_e880a1b4a8ae9201.edn"
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xskripsi/_ngo/multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_22d1b55eb2467aac.edn"
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to
"d:/isnique/work/xskripsi/_ngo/multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 39788 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 40752 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/top_level2.vhf in Library work.
Entity <top_level2> (Architecture <behavioral>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_level2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_level2> (Architecture <behavioral>).
WARNING:Xst:37 - Unknown property "n".
WARNING:Xst:37 - Unknown property "n".
Entity <top_level2> analyzed. Unit <top_level2> generated.

Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_136>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <simple1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <top_level2>.
    Related source file is D:/isnique/work/xskripsi/top_level2.vhf.
Unit <top_level2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_level2> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_level2, actual ratio is 33.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     253  out of    768    32%  
 Number of Slice Flip Flops:            56  out of   1536     3%  
 Number of 4 input LUTs:               439  out of   1536    28%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_sg                             | BUFGP                  | 50    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.129ns (Maximum Frequency: 194.970MHz)
   Minimum input arrival time before clock: 6.666ns
   Maximum output required time after clock: 27.978ns
   Maximum combinational path delay: 29.514ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...
ERROR:NgdBuild:755 - Line 5 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 6 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 7 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(10)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 8 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(11)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 9 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(12)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 10 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(13)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 11 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(14)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 12 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(15)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 13 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 14 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 15 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 16 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 17 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 18 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 19 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(8)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 20 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(9)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "top_level2.ucf".

Writing NGDBUILD log file "top_level2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...
ERROR:NgdBuild:755 - Line 5 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 6 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 7 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(10)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 8 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(11)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 9 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(12)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 10 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(13)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 11 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(14)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 12 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(15)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 13 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 14 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 15 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 16 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 17 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 18 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 19 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(8)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 20 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(9)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "top_level2.ucf".

Writing NGDBUILD log file "top_level2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 40752 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...
ERROR:NgdBuild:755 - Line 4 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 5 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 6 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(10)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 7 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(11)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 8 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(12)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 9 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(13)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 10 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(14)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 11 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(15)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 12 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 13 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 14 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 15 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 16 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 17 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 18 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(8)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 19 in 'top_level2.ucf': Could not find net(s)
   'in_x_0(9)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 20 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(0)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 21 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(1)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 22 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(10)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 23 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(11)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 24 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(12)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 25 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(13)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 26 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(14)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 27 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(15)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 28 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(16)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 29 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(17)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 30 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(18)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 31 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(19)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 32 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(2)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 33 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(20)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 34 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(21)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 35 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(22)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 36 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(23)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 37 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(3)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 38 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(4)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 39 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(5)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 40 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(6)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 41 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(7)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 42 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(8)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 43 in 'top_level2.ucf': Could not find net(s)
   'out_x_0(9)' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "top_level2.ucf".

Writing NGDBUILD log file "top_level2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 40752 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <simple1_addsub1> (Architecture <behavior>) compiled.
Entity <simple1_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <simple1> (Architecture <structural>) compiled.
Entity <simple1_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_clk_wrapper.vhd in Library
work.
Entity <simple1_clk_wrapper> (Architecture <structural>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "View RTL Schematic".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_clk_wrapper.vhd in Library work.
Architecture structural of Entity simple1_clk_wrapper is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <simple1_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <simple1_clk_wrapper> analyzed. Unit <simple1_clk_wrapper> generated.

Analyzing Entity <simple1_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <simple1_clock_driver> analyzed. Unit <simple1_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <simple1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <simple1_clock_driver>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <simple1_clock_driver> synthesized.


Synthesizing Unit <simple1_clk_wrapper>.
    Related source file is D:/isnique/work/xskripsi/simple1_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <simple1_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <simple1_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

=========================================================================
*                            Final Report                               *
=========================================================================
Completed process "View RTL Schematic".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_clk_wrapper.vhd in Library work.
Architecture structural of Entity simple1_clk_wrapper is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <simple1_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <simple1_clk_wrapper> analyzed. Unit <simple1_clk_wrapper> generated.

Analyzing Entity <simple1_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <simple1_clock_driver> analyzed. Unit <simple1_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <simple1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <simple1_clock_driver>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <simple1_clock_driver> synthesized.


Synthesizing Unit <simple1_clk_wrapper>.
    Related source file is D:/isnique/work/xskripsi/simple1_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <simple1_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <simple1_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <simple1_clk_wrapper> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block simple1_clk_wrapper, actual ratio is 30.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     235  out of    768    30%  
 Number of Slice Flip Flops:            32  out of   1536     2%  
 Number of 4 input LUTs:               399  out of   1536    25%  
 Number of bonded IOBs:                 40  out of    144    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 32    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.045ns (Maximum Frequency: 198.216MHz)
   Minimum input arrival time before clock: 6.581ns
   Maximum output required time after clock: 24.810ns
   Maximum combinational path delay: 26.346ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -i -p
xc2s50-pq208-6 simple1_clk_wrapper.ngc simple1_clk_wrapper.ngd 

Reading NGO file "D:/isnique/work/xskripsi/simple1_clk_wrapper.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub3_core_instance4/S(16)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(0)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(1)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(2)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(3)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(4)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(5)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(6)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(7)' has
   no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(32)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(33)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(34)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(35)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(36)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(37)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(38)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(39)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(40)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(41)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(42)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(43)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(44)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(45)'
   has no load
WARNING:NgdBuild:454 - logical net 'simple1_top_addsub4_core_instance6/S(46)'
   has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 39728 kilobytes

Writing NGD file "simple1_clk_wrapper.ngd" ...

Writing NGDBUILD log file "simple1_clk_wrapper.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        16 out of  1,536    1%
  Number of 4 input LUTs:           298 out of  1,536   19%
Logic Distribution:
    Number of occupied Slices:                         155 out of    768   20%
    Number of Slices containing only related logic:    155 out of    155  100%
    Number of Slices containing unrelated logic:         0 out of    155    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          301 out of  1,536   19%
      Number used as logic:                       298
      Number used as a route-thru:                  3
   Number of bonded IOBs:            40 out of    140   28%
      IOB Flip Flops:                              16
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,109
Additional JTAG gate count for IOBs:  1,968
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "simple1_clk_wrapper_map.mrp" for details.
Completed process "Map".

Mapping Module simple1_clk_wrapper . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o simple1_clk_wrapper_map.ncd simple1_clk_wrapper.ngd simple1_clk_wrapper.pcf
Mapping Module simple1_clk_wrapper: DONE



Started process "Place & Route".





Constraints file: simple1_clk_wrapper.pcf

Loading device database for application Par from file
"simple1_clk_wrapper_map.ncd".
   "simple1_clk_wrapper" is an NCD, version 2.38, device xc2s50, package pq208,
speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            40 out of 140    28%
      Number of LOCed External IOBs    0 out of 40      0%

   Number of SLICEs                  155 out of 768    20%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9898eb) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.......
Phase 5.8 (Checksum:9cb5c5) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file simple1_clk_wrapper.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 867 unrouted;       REAL time: 2 secs 

Phase 2: 843 unrouted;       REAL time: 2 secs 

Phase 3: 201 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   24   |  0.089     |  0.463      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  48 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file simple1_clk_wrapper.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 11:37:43 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module simple1_clk_wrapper . . .
PAR command line: par -w -intstyle ise -ol std -t 1 simple1_clk_wrapper_map.ncd simple1_clk_wrapper.ncd simple1_clk_wrapper.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/top_level2.vhf in Library work.
Architecture behavioral of Entity top_level2 is up to date.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_level2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_level2> (Architecture <behavioral>).
WARNING:Xst:37 - Unknown property "n".
WARNING:Xst:37 - Unknown property "n".
Entity <top_level2> analyzed. Unit <top_level2> generated.

Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_136>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <simple1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <top_level2>.
    Related source file is D:/isnique/work/xskripsi/top_level2.vhf.
Unit <top_level2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_level2> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_level2, actual ratio is 33.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     253  out of    768    32%  
 Number of Slice Flip Flops:            56  out of   1536     3%  
 Number of 4 input LUTs:               439  out of   1536    28%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_sg                             | BUFGP                  | 50    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.129ns (Maximum Frequency: 194.970MHz)
   Minimum input arrival time before clock: 6.666ns
   Maximum output required time after clock: 27.978ns
   Maximum combinational path delay: 29.514ns

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 40752 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs    0 out of 30      0%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9c8235) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 2 secs 

Phase 2: 960 unrouted;       REAL time: 5 secs 

Phase 3: 198 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.106     |  0.449      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  1.072     |  4.329      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 11:47:22 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   30 out of 30    100%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cc46b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 0 secs 

Phase 2: 961 unrouted;       REAL time: 5 secs 

Phase 3: 213 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.096     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  0.827     |  2.909      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 14:11:47 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   29 out of 30     96%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cb115) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 2 secs 

Phase 2: 960 unrouted;       REAL time: 5 secs 

Phase 3: 252 unrouted;       REAL time: 6 secs 

Phase 4: 0 unrouted;       REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.079     |  0.449      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  0.063     |  2.871      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  52 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 14:26:29 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:13 - Net "anode0" is connected to source pins and/or IO
   ports while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "anode1" is connected to source pins and/or IO
   ports while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "anode2" is connected to source pins and/or IO
   ports while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "anode3" is connected to source pins and/or IO
   ports while there is no load pin connected to it
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/top_level2.vhf in Library work.
Entity <top_level2> (Architecture <behavioral>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_level2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_level2> (Architecture <behavioral>).
WARNING:Xst:37 - Unknown property "n".
WARNING:Xst:37 - Unknown property "n".
Entity <top_level2> analyzed. Unit <top_level2> generated.

Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_136>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <simple1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <top_level2>.
    Related source file is D:/isnique/work/xskripsi/top_level2.vhf.
WARNING:Xst:646 - Signal <anode3_DUMMY> is assigned but never used.
WARNING:Xst:646 - Signal <anode2_DUMMY> is assigned but never used.
WARNING:Xst:646 - Signal <anode1_DUMMY> is assigned but never used.
WARNING:Xst:646 - Signal <anode0_DUMMY> is assigned but never used.
Unit <top_level2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.
WARNING:Xst:1291 - FF/Latch <anode3> is unconnected in block <XLXI_3>.

Optimizing unit <top_level2> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <XLXI_3_anode3> is unconnected in block <top_level2>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_level2, actual ratio is 33.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     252  out of    768    32%  
 Number of Slice Flip Flops:            55  out of   1536     3%  
 Number of 4 input LUTs:               438  out of   1536    28%  
 Number of bonded IOBs:                 26  out of    144    18%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_sg                             | BUFGP                  | 50    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 5     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.129ns (Maximum Frequency: 194.970MHz)
   Minimum input arrival time before clock: 6.666ns
   Maximum output required time after clock: 27.978ns
   Maximum combinational path delay: 29.514ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...
ERROR:NgdBuild:755 - Line 4 in 'top_level2.ucf': Could not find net(s) 'anode0'
   in the design.  To suppress this error specify the correct net name or remove
   the constraint.  The 'Ignore I\O constraints on Invalid Object Names'
   property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 5 in 'top_level2.ucf': Could not find net(s) 'anode1'
   in the design.  To suppress this error specify the correct net name or remove
   the constraint.  The 'Ignore I\O constraints on Invalid Object Names'
   property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 6 in 'top_level2.ucf': Could not find net(s) 'anode2'
   in the design.  To suppress this error specify the correct net name or remove
   the constraint.  The 'Ignore I\O constraints on Invalid Object Names'
   property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "top_level2.ucf".

Writing NGDBUILD log file "top_level2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...
ERROR:NgdBuild:755 - Line 4 in 'top_level2.ucf': Could not find net(s) 'anode1'
   in the design.  To suppress this error specify the correct net name or remove
   the constraint.  The 'Ignore I\O constraints on Invalid Object Names'
   property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 5 in 'top_level2.ucf': Could not find net(s) 'anode2'
   in the design.  To suppress this error specify the correct net name or remove
   the constraint.  The 'Ignore I\O constraints on Invalid Object Names'
   property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 6 in 'top_level2.ucf': Could not find net(s) 'anode3'
   in the design.  To suppress this error specify the correct net name or remove
   the constraint.  The 'Ignore I\O constraints on Invalid Object Names'
   property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "top_level2.ucf".

Writing NGDBUILD log file "top_level2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/top_level2.vhf in Library work.
Entity <top_level2> (Architecture <behavioral>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_level2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_level2> (Architecture <behavioral>).
WARNING:Xst:37 - Unknown property "n".
WARNING:Xst:37 - Unknown property "n".
Entity <top_level2> analyzed. Unit <top_level2> generated.

Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_136>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <simple1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <top_level2>.
    Related source file is D:/isnique/work/xskripsi/top_level2.vhf.
Unit <top_level2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_level2> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_level2, actual ratio is 33.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     253  out of    768    32%  
 Number of Slice Flip Flops:            56  out of   1536     3%  
 Number of 4 input LUTs:               439  out of   1536    28%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_sg                             | BUFGP                  | 50    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.129ns (Maximum Frequency: 194.970MHz)
   Minimum input arrival time before clock: 6.666ns
   Maximum output required time after clock: 27.978ns
   Maximum combinational path delay: 29.514ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   30 out of 30    100%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
......
Phase 5.8 (Checksum:9cd569) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 0 secs 

Phase 2: 960 unrouted;       REAL time: 5 secs 

Phase 3: 253 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.096     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  0.159     |  2.882      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 14:33:47 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   28 out of 30     93%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cc91b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 2 secs 

Phase 2: 961 unrouted;       REAL time: 5 secs 

Phase 3: 246 unrouted;       REAL time: 6 secs 

Phase 4: 0 unrouted;       REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.096     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  1.185     |  2.910      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 14:38:47 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   29 out of 30     96%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cc966) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 0 secs 

Phase 2: 961 unrouted;       REAL time: 5 secs 

Phase 3: 245 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.096     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  1.185     |  2.910      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 14:43:14 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   28 out of 30     93%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cc91b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 0 secs 

Phase 2: 961 unrouted;       REAL time: 5 secs 

Phase 3: 246 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.096     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  1.185     |  2.910      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 14:46:30 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   28 out of 30     93%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cbe8f) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 2 secs 

Phase 2: 960 unrouted;       REAL time: 5 secs 

Phase 3: 237 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.078     |  0.448      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  0.063     |  2.863      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 14:57:09 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   28 out of 30     93%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cc91b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 2 secs 

Phase 2: 961 unrouted;       REAL time: 5 secs 

Phase 3: 246 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.096     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  1.185     |  2.910      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 15:00:33 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   30 out of 30    100%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cc46b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 0 secs 

Phase 2: 961 unrouted;       REAL time: 5 secs 

Phase 3: 213 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.096     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  0.827     |  2.909      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 15:14:06 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   30 out of 30    100%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cc46b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 2 secs 

Phase 2: 961 unrouted;       REAL time: 5 secs 

Phase 3: 213 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.096     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  0.827     |  2.909      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 15:21:19 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "seg7_driver.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "seg7_driver.v"
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode0' as a reg
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode1' as a reg
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode2' as a reg
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode3' as a reg
Module <seg7_driver> compiled
Analysis of file <seg7_driver.prj> failed.
--> 

Total memory usage is 46728 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "seg7_driver.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "seg7_driver.v"
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode0' as a reg
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode1' as a reg
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode2' as a reg
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode3' as a reg
Module <seg7_driver> compiled
Analysis of file <seg7_driver.prj> failed.
--> 

Total memory usage is 46728 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "seg7_driver.v"
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode0' as a reg
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode1' as a reg
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode2' as a reg
ERROR:HDLCompilers:120 - seg7_driver.v line 12 Illegal redeclaration of input 'anode3' as a reg
Module <seg7_driver> compiled
Analysis of file <seg7_driver.prj> failed.
--> 

Total memory usage is 46728 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <seg7_driver.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seg7_driver, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      13  out of    768     1%  
 Number of Slice Flip Flops:             6  out of   1536     0%  
 Number of 4 input LUTs:                22  out of   1536     1%  
 Number of bonded IOBs:                 37  out of    144    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_200hz                          | BUFGP                  | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 4.008ns (Maximum Frequency: 249.501MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 10.829ns
   Maximum combinational path delay: 9.647ns

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/isnique/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/isnique/work/xskripsi/top_level2.vhf in Library work.
Entity <top_level2> (Architecture <behavioral>) compiled.
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <top_level2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_level2> (Architecture <behavioral>).
WARNING:Xst:37 - Unknown property "n".
WARNING:Xst:37 - Unknown property "n".
Entity <top_level2> analyzed. Unit <top_level2> generated.

Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/isnique/work/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/isnique/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_136>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <simple1>.
    Related source file is D:/isnique/work/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <top_level2>.
    Related source file is D:/isnique/work/xskripsi/top_level2.vhf.
Unit <top_level2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_level2> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_level2, actual ratio is 33.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     253  out of    768    32%  
 Number of Slice Flip Flops:            56  out of   1536     3%  
 Number of 4 input LUTs:               439  out of   1536    28%  
 Number of bonded IOBs:                 30  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_sg                             | BUFGP                  | 50    |
XLXI_4_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.129ns (Maximum Frequency: 194.970MHz)
   Minimum input arrival time before clock: 6.666ns
   Maximum output required time after clock: 27.978ns
   Maximum combinational path delay: 29.514ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   30 out of 30    100%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cc46b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 2 secs 

Phase 2: 961 unrouted;       REAL time: 5 secs 

Phase 3: 213 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.096     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  0.827     |  2.909      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 16:56:09 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_1_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  24

Total memory usage is 41776 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            30 out of    140   21%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,488
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            30 out of 140    21%
      Number of LOCed External IOBs   30 out of 30    100%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98993f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:9cc46b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1000 unrouted;       REAL time: 0 secs 

Phase 2: 961 unrouted;       REAL time: 5 secs 

Phase 3: 213 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.096     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_clock_cnt<17>    |   Local  |    5   |  0.827     |  2.909      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jul 22 17:01:36 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:11 - Net "anode0" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:11 - Net "anode1" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:11 - Net "anode2" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:11 - Net "anode3" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".



Project Navigator Auto-Make Log File
-------------------------------------


Launching Application for process "Generate Expected Simulation Results".

Reading d:/engineering/xilinx6_2i/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.7g

# do tv1_tbw.ado 
listening on address 127.0.0.1 port 1200
# resume
# Model Technology ModelSim XE II vlog 5.7g Compiler 2003.10 Oct 13 2003
# -- Compiling module clk_div
# 
# Top level modules:
# 	clk_div
# Model Technology ModelSim XE II vlog 5.7g Compiler 2003.10 Oct 13 2003
# -- Compiling module seg7_driver
# 
# Top level modules:
# 	seg7_driver
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# ** Error: (vcom-19) Failed to access library 'unisim' at "d:/engineering/xilinx6_2i/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim".
# No such file or directory. (errno = ENOENT)
# ** Error: simple1_files.vhd(48): Library unisim not found.
# ** Error: simple1_files.vhd(49): Unknown identifier: unisim
# ** Error: simple1_files.vhd(51): VHDL Compiler exiting
# ERROR: d:/engineering/xilinx6_2i/Modeltech_xe_starter/win32xoem/vcom failed.
# Executing ONERROR command at macro ./tv1_tbw.ado line 13
ERROR: VSim failed to simulate annotated testbench

Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:11 - Net "anode0" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:11 - Net "anode1" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:11 - Net "anode2" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
WARNING:DesignEntry:11 - Net "anode3" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_level2.prj> succeeded.
 
WARNING:HDLParsers:3215 - Unit work/SRL17E is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SRL17E/STRUCTURAL is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG/STRUCTURAL is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_REG is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_REG/BEHAV is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SINGLE_REG_W_INIT is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SINGLE_REG_W_INIT/STRUCTURAL is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_W_INIT is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_W_INIT/STRUCTURAL is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLKPROBE is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLKPROBE/BEHAVIOR is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKDRIVER is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKDRIVER/BEHAVIOR is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKGENERATOR is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKGENERATOR/STRUCTURAL is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSL2SLV is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSL2SLV/BEHAVIOR is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSLV2SL is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSLV2SL/BEHAVIOR is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_ADDSUB is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_ADDSUB/BEHAVIOR is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_ADDSUB1 is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_ADDSUB1/BEHAVIOR is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_KD is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_KD/BEHAVIOR is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLDELAY is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLDELAY/BEHAVIOR is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1 is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1/STRUCTURAL is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_CLOCK_DRIVER is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_CLOCK_DRIVER/STRUCTURAL is now defined in a different file: was D:/isnique/work/xskripsi/simple1_files.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/CONV_PKG is now defined in a different file: was D:/isnique/work/xskripsi/simple1_pkgs.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_pkgs.vhd
WARNING:HDLParsers:3215 - Unit work/CONV_PKG is now defined in a different file: was D:/isnique/work/xskripsi/simple1_pkgs.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_pkgs.vhd
WARNING:HDLParsers:3215 - Unit work/CLOCK_PKG is now defined in a different file: was D:/isnique/work/xskripsi/simple1_pkgs.vhd, now is D:/Engineering/Work/Naswi/xskripsi/simple1_pkgs.vhd
Compiling vhdl file D:/Engineering/Work/Naswi/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/Engineering/Work/Naswi/xskripsi/top_level2.vhf in Library work.
Entity <top_level2> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_level2> (Architecture <behavioral>).
Entity <top_level2> analyzed. Unit <top_level2> generated.

Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <seg7_driver>.
ERROR:Xst:871 - seg7_driver.v line 23: Invalid use of input signal <anode0> as target.
ERROR:Xst:871 - seg7_driver.v line 23: Invalid use of input signal <anode1> as target.
ERROR:Xst:871 - seg7_driver.v line 23: Invalid use of input signal <anode2> as target.
ERROR:Xst:871 - seg7_driver.v line 23: Invalid use of input signal <anode3> as target.
 
Found 4 error(s). Aborting synthesis.
--> 

Total memory usage is 47148 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling source file "seg7_driver.v"
tdtfi(verilog) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_level2.prj> succeeded.
 
Compiling vhdl file D:/Engineering/Work/Naswi/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file D:/Engineering/Work/Naswi/xskripsi/top_level2.vhf in Library work.
Entity <top_level2> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_level2> (Architecture <behavioral>).
Entity <top_level2> analyzed. Unit <top_level2> generated.

Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <simple1>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <top_level2>.
    Related source file is D:/Engineering/Work/Naswi/xskripsi/top_level2.vhf.
Unit <top_level2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_level2> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment D:/Engineering/Xilinx6_2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_level2, actual ratio is 33.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     253  out of    768    32%  
 Number of Slice Flip Flops:            56  out of   1536     3%  
 Number of 4 input LUTs:               439  out of   1536    28%  
 Number of bonded IOBs:                 29  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_sg                             | BUFGP                  | 50    |
XLXI_3_clock_cnt_17:Q              | NONE                   | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.129ns (Maximum Frequency: 194.970MHz)
   Minimum input arrival time before clock: 6.581ns
   Maximum output required time after clock: 27.978ns
   Maximum combinational path delay: 29.514ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\engineering\work\naswi\xskripsi/_ngo
-uc top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/Engineering/Work/Naswi/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\engineering\work\naswi\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140
491d6df.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\engineering\work\naswi\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23
c19deaf.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\engineering\work\naswi\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3
c6c3ed0.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\engineering\work\naswi\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a
7991da9.ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\engineering\work\naswi\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3
a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\engineering\work\naswi\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae920
1.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\engineering\work\naswi\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aa
c.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'ce_sg' has no load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  25

Total memory usage is 40148 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            29 out of    140   20%
      IOB Flip Flops:                              17
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,535
Additional JTAG gate count for IOBs:  1,440
Peak Memory Usage:  60 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
D:/Engineering/Xilinx6_2i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            29 out of 140    20%
      Number of LOCed External IOBs   29 out of 29    100%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989934) REAL time: 9 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 9 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 9 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 9 secs 

Phase 5.8
..........
Phase 5.8 (Checksum:9d1ef2) REAL time: 9 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 9 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 9 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 11 secs 
Total CPU time to Placer completion: 6 secs 


Phase 1: 976 unrouted;       REAL time: 12 secs 

Phase 2: 938 unrouted;       REAL time: 21 secs 

Phase 3: 235 unrouted;       REAL time: 22 secs 

Phase 4: 0 unrouted;       REAL time: 22 secs 

Total REAL time to Router completion: 23 secs 
Total CPU time to Router completion: 15 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.095     |  0.465      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_3_clock_cnt<17>    |   Local  |    5   |  0.900     |  2.893      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 25 secs 
Total CPU time to PAR completion: 17 secs 

Peak Memory Usage:  50 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sat Jul 23 19:02:31 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully




Started process "Programming File Generation Report".

Completed process "Programming File Generation Report".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\isnique\work\xskripsi/_ngo -uc
top_level2.ucf -p xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "D:/isnique/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ng
o"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"d:\isnique\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"...
mult_gen_v6_0, Coregen 6.2i

Annotating constraints to design from file "top_level2.ucf" ...
ERROR:NgdBuild:755 - Line 8 in 'top_level2.ucf': Could not find net(s)
   'cathode<0>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 9 in 'top_level2.ucf': Could not find net(s)
   'cathode<1>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 10 in 'top_level2.ucf': Could not find net(s)
   'cathode<2>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 11 in 'top_level2.ucf': Could not find net(s)
   'cathode<3>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 12 in 'top_level2.ucf': Could not find net(s)
   'cathode<4>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 13 in 'top_level2.ucf': Could not find net(s)
   'cathode<5>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 14 in 'top_level2.ucf': Could not find net(s)
   'cathode<6>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 15 in 'top_level2.ucf': Could not find net(s)
   'cathode<7>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 18 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<0>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 19 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<10>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 20 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<11>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 21 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<12>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 22 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<13>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 23 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<14>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 24 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<15>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 25 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<1>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 26 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<2>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 27 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<3>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 28 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<4>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 29 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<5>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 30 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<6>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 31 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<7>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 32 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<8>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:NgdBuild:755 - Line 33 in 'top_level2.ucf': Could not find net(s)
   'in_x_0<9>' in the design.  To suppress this error specify the correct net
   name or remove the constraint.  The 'Ignore I\O constraints on Invalid Object
   Names' property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "top_level2.ucf".

Writing NGDBUILD log file "top_level2.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_div.v"
Module <clk_div> compiled
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <top_level2.prj> succeeded.
 
WARNING:HDLParsers:3215 - Unit work/TOP_LEVEL2 is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/top_level2.vhf, now is C:/MATLAB6p5/work/xskripsi/top_level2.vhf
WARNING:HDLParsers:3215 - Unit work/TOP_LEVEL2/BEHAVIORAL is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/top_level2.vhf, now is C:/MATLAB6p5/work/xskripsi/top_level2.vhf
WARNING:HDLParsers:3215 - Unit work/SRL17E is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SRL17E/STRUCTURAL is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG/STRUCTURAL is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_REG is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_REG/BEHAV is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SINGLE_REG_W_INIT is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SINGLE_REG_W_INIT/STRUCTURAL is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_W_INIT is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_REG_W_INIT/STRUCTURAL is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLKPROBE is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLKPROBE/BEHAVIOR is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKDRIVER is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKDRIVER/BEHAVIOR is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKGENERATOR is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLCLOCKGENERATOR/STRUCTURAL is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSL2SLV is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSL2SLV/BEHAVIOR is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSLV2SL is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLSLV2SL/BEHAVIOR is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_ADDSUB is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SYNTH_ADDSUB/BEHAVIOR is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_ADDSUB1 is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_ADDSUB1/BEHAVIOR is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_KD is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_KD/BEHAVIOR is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLDELAY is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/XLDELAY/BEHAVIOR is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1 is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1/STRUCTURAL is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_CLOCK_DRIVER is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/SIMPLE1_CLOCK_DRIVER/STRUCTURAL is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_files.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd
WARNING:HDLParsers:3215 - Unit work/CONV_PKG is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_pkgs.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_pkgs.vhd
WARNING:HDLParsers:3215 - Unit work/CONV_PKG is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_pkgs.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_pkgs.vhd
WARNING:HDLParsers:3215 - Unit work/CLOCK_PKG is now defined in a different file: was D:/Engineering/Work/Naswi/xskripsi/simple1_pkgs.vhd, now is C:/MATLAB6p5/work/xskripsi/simple1_pkgs.vhd
Compiling vhdl file C:/MATLAB6p5/work/xskripsi/simple1_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/xskripsi/simple1_files.vhd in Library work.
Architecture structural of Entity srl17e is up to date.
Architecture structural of Entity synth_reg is up to date.
Architecture behav of Entity synth_reg_reg is up to date.
Architecture structural of Entity single_reg_w_init is up to date.
Architecture structural of Entity synth_reg_w_init is up to date.
Architecture behavior of Entity xlclkprobe is up to date.
Architecture behavior of Entity xlclockdriver is up to date.
Architecture structural of Entity xlclockgenerator is up to date.
Architecture behavior of Entity xlsl2slv is up to date.
Architecture behavior of Entity xlslv2sl is up to date.
Architecture behavior of Entity synth_addsub is up to date.
Architecture behavior of Entity simple1_addsub1 is up to date.
Architecture behavior of Entity simple1_kd is up to date.
Architecture behavior of Entity xldelay is up to date.
Architecture structural of Entity simple1 is up to date.
Architecture structural of Entity simple1_clock_driver is up to date.
Compiling vhdl file C:/MATLAB6p5/work/xskripsi/top_level2.vhf in Library work.
Architecture behavioral of Entity top_level2 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_level2> (Architecture <behavioral>).
Entity <top_level2> analyzed. Unit <top_level2> generated.

Analyzing module <clk_div>.
Module <clk_div> is correct for synthesis.
 
Analyzing module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 
Analyzing Entity <simple1> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2370: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2370: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2425: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2425: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2480: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2480: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2535: Unconnected input port 'c_in' of component 'simple1_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2535: Unconnected output port 'c_out' of component 'simple1_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2642: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2699: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_ce' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clr' of component 'simple1_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xskripsi/simple1_files.vhd line 2756: Unconnected input port 'core_clk' of component 'simple1_kd' is tied to default value.
Entity <simple1> analyzed. Unit <simple1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub1> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_9b2656d23c19deaf"
	a_width = 32
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 33
	b_bin_pt = 12
	b_arith = 2
	s_width = 40
	s_bin_pt = 18
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 40
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 40
	c_b_width = 40
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 40
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub10> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub11> generated.

Analyzing generic Entity <simple1_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9"
	a_width = 40
	a_bin_pt = 18
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 47
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 47
	c_b_width = 47
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 47
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_addsub1> analyzed. Unit <simple1_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_fe654cf32dc31d3a"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 33
	p_bin_pt = 12
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 33
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd3> generated.

Analyzing generic Entity <simple1_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_22d1b55eb2467aac"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 32
	p_bin_pt = 18
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <simple1_kd> analyzed. Unit <simple1_kd4> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.


Reading constraint file .\simple1_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <simple1_kd4>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd4> synthesized.


Synthesizing Unit <simple1_kd3>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd3> synthesized.


Synthesizing Unit <simple1_kd>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <simple1_kd> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <simple1_addsub12>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<46:32>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub12> synthesized.


Synthesizing Unit <simple1_addsub11>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub11> synthesized.


Synthesizing Unit <simple1_addsub10>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub10> synthesized.


Synthesizing Unit <simple1_addsub1>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <simple1_addsub1> synthesized.


Synthesizing Unit <simple1>.
    Related source file is C:/MATLAB6p5/work/xskripsi/simple1_files.vhd.
Unit <simple1> synthesized.


Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


Synthesizing Unit <top_level2>.
    Related source file is C:/MATLAB6p5/work/xskripsi/top_level2.vhf.
Unit <top_level2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Counters                         : 1
 18-bit up counter                 : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_9b2656d23c19deaf> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_47d1c1f0a7991da9> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_fe654cf32dc31d3a> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_22d1b55eb2467aac> for timing and area information for instance <core_instance4>.

Optimizing unit <top_level2> ...

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\simple1_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block top_level2, actual ratio is 32.
FlipFlop XLXI_4_anode0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_4_anode1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop XLXI_4_anode2 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     255  out of    768    33%  
 Number of Slice Flip Flops:            59  out of   1536     3%  
 Number of 4 input LUTs:               439  out of   1536    28%  
 Number of bonded IOBs:                 29  out of    144    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_sg                             | BUFGP                  | 50    |
XLXI_3_clock_cnt_17:Q              | NONE                   | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.129ns (Maximum Frequency: 194.970MHz)
   Minimum input arrival time before clock: 6.581ns
   Maximum output required time after clock: 27.978ns
   Maximum combinational path delay: 29.514ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\matlab6p5\work\xskripsi/_ngo -i -p
xc2s50-pq208-6 top_level2.ngc top_level2.ngd 

Reading NGO file "C:/MATLAB6p5/work/xskripsi/top_level2.ngc" ...
Reading component libraries for design expansion...
Launcher: "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_86c498140491d6df.
ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_9b2656d23c19deaf.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_9b2656d23c19deaf.
ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.
ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\xskripsi\_ngo\adder_subtracter_spartan2_6_0_47d1c1f0a7991da9.
ngo"...
C_ADDSUB_V6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\xskripsi\_ngo\multiplier_spartan2_6_0_fe654cf32dc31d3a.ngo"..
.
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\xskripsi\_ngo\multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"..
.
mult_gen_v6_0, Coregen 6.2i
Launcher: "multiplier_spartan2_6_0_22d1b55eb2467aac.ngo" is up to date.
Loading design module
"c:\matlab6p5\work\xskripsi\_ngo\multiplier_spartan2_6_0_22d1b55eb2467aac.ngo"..
.
mult_gen_v6_0, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'ce_sg' has no load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub3_core_instance4/S(16)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(0)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(1)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(2)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(3)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(4)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(5)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(6)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(7)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(32)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(33)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(34)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(35)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(36)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(37)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(38)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(39)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(40)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(41)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(42)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(43)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(44)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(45)' has no
   load
WARNING:NgdBuild:454 - logical net 'XLXI_9_addsub4_core_instance6/S(46)' has no
   load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  25

Total memory usage is 39812 kilobytes

Writing NGD file "top_level2.ngd" ...

Writing NGDBUILD log file "top_level2.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        39 out of  1,536    2%
  Number of 4 input LUTs:           320 out of  1,536   20%
Logic Distribution:
    Number of occupied Slices:                         175 out of    768   22%
    Number of Slices containing only related logic:    175 out of    175  100%
    Number of Slices containing unrelated logic:         0 out of    175    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          340 out of  1,536   22%
      Number used as logic:                       320
      Number used as a route-thru:                 20
   Number of bonded IOBs:            29 out of    140   20%
      IOB Flip Flops:                              20
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            6
Total equivalent gate count for design:  3,559
Additional JTAG gate count for IOBs:  1,440
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_level2_map.mrp" for details.
Completed process "Map".

Mapping Module top_level2 . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_level2_map.ncd top_level2.ngd top_level2.pcf
Mapping Module top_level2: DONE



Started process "Place & Route".





Constraints file: top_level2.pcf

Loading device database for application Par from file "top_level2_map.ncd".
   "top_level2" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/xilinx_62i.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            29 out of 140    20%
      Number of LOCed External IOBs    0 out of 29      0%

   Number of SLICEs                  175 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:989934) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.....
.
Phase 5.8 (Checksum:9c9a86) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file top_level2.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 982 unrouted;       REAL time: 3 secs 

Phase 2: 943 unrouted;       REAL time: 5 secs 

Phase 3: 234 unrouted;       REAL time: 5 secs 

Phase 4: 234 unrouted; (0)      REAL time: 5 secs 

Phase 5: 234 unrouted; (0)      REAL time: 5 secs 

Phase 6: 234 unrouted; (0)      REAL time: 5 secs 

Phase 7: 0 unrouted; (0)      REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      clk_sg_BUFGP          |  Global  |   33   |  0.107     |  0.450      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_3_clock_cnt(17)    |   Local  |    8   |  0.517     |  2.943      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_9bdee101 = PERIOD TIMEGRP "clk_9bd | 100.000ns  | 4.887ns    | 9    
  ee101"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  57 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file top_level2.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Jul 26 17:14:51 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top_level2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_level2_map.ncd top_level2.ncd top_level2.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clk_div.v"
Module <clk_div> compiled
No errors in compilation
Analysis of file <clk_div.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clk_div>.
Module <clk_div> is correct for synthesis.
 

Reading constraint file .\simple1_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_div>.
    Related source file is clk_div.v.
    Found 18-bit up counter for signal <clock_cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_div> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 18-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_div> ...
Loading device for application Xst from file 'v50.nph' in environment C:/xilinx_62i.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\simple1_clk_wrapper.xcf'
ERROR:Xst:1370 - Line 6: Signal name clk_sg not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed
CPU : 1.56 / 2.89 s | Elapsed : 2.00 / 3.00 s
 
--> 

Total memory usage is 54028 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------

