# XST (Creating Lso File) : 
clock_pkg.lso
# Check Syntax
clock_pkg.stx
# ProjNav -> New Source -> TBW
C:\MATLAB6p5\work\xpid1sg\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
pid1sg_tbw.ado
pid1sg_tbw.ano
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
pid1sg_tbw.ado
pid1sg_tbw.ano
# ProjNav -> New Source -> TBW
C:\MATLAB6p5\work\xpid1sg\__projnav\hb_cmds
# ProjNav -> New Source -> TBW
C:\MATLAB6p5\work\xpid1sg\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
pid1sg_tbw.vhw
pid1sg_tbw.ano
pid1sg_tbw.tfw
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
pid1sg_tbw.ado
pid1sg_tbw.ano
# ModelSim : Generate Expected Simulation Results
pid1sg_tbw.ado
pid1sg_tbw.ano
# XST (Creating Lso File) : 
pid1sg_clk_wrapper.lso
# xst flow : RunXST
pid1sg_clk_wrapper.syr
pid1sg_clk_wrapper.prj
pid1sg_clk_wrapper.sprj
pid1sg_clk_wrapper.ana
pid1sg_clk_wrapper.stx
pid1sg_clk_wrapper.cmd_log
pid1sg_clk_wrapper.ngc
pid1sg_clk_wrapper.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\matlab6p5\work\xpid1sg/_ngo
pid1sg_clk_wrapper.ngd
pid1sg_clk_wrapper_ngdbuild.nav
pid1sg_clk_wrapper.bld
.untf
pid1sg_clk_wrapper.cmd_log
# Implementation : Map
pid1sg_clk_wrapper_map.ncd
pid1sg_clk_wrapper.ngm
pid1sg_clk_wrapper.pcf
pid1sg_clk_wrapper.nc1
pid1sg_clk_wrapper.mrp
pid1sg_clk_wrapper_map.mrp
pid1sg_clk_wrapper.mdf
__projnav/map.log
pid1sg_clk_wrapper.cmd_log
MAP_NO_GUIDE_FILE_CPF "pid1sg_clk_wrapper"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
pid1sg_clk_wrapper.twr
pid1sg_clk_wrapper.twx
pid1sg_clk_wrapper.tsi
pid1sg_clk_wrapper.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
pid1sg_clk_wrapper.ncd
pid1sg_clk_wrapper.par
pid1sg_clk_wrapper.pad
pid1sg_clk_wrapper_pad.txt
pid1sg_clk_wrapper_pad.csv
pid1sg_clk_wrapper.pad_txt
pid1sg_clk_wrapper.dly
reportgen.log
pid1sg_clk_wrapper.xpi
pid1sg_clk_wrapper.grf
pid1sg_clk_wrapper.itr
pid1sg_clk_wrapper_last_par.ncd
__projnav/par.log
pid1sg_clk_wrapper.placed_ncd_tracker
pid1sg_clk_wrapper.routed_ncd_tracker
pid1sg_clk_wrapper.cmd_log
PAR_NO_GUIDE_FILE_CPF "pid1sg_clk_wrapper"
# Implementation : View/Edit Routed Design (FPGA Editor)
pid1sg_clk_wrapper_map_fpga_editor.log
pid1sg_clk_wrapper_fpga_editor.out
pid1sg_clk_wrapper_fpga_editor.log
__projnav/pfea_tcl.rsp
