Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: seg7_driver.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : seg7_driver.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : seg7_driver
Output Format                      : NGC
Target Device                      : xc2s50-6-pq208

---- Source Options
Top Module Name                    : seg7_driver
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : seg7_driver.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "seg7_driver.v"
Module <seg7_driver> compiled
No errors in compilation
Analysis of file <seg7_driver.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <seg7_driver>.
Module <seg7_driver> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seg7_driver>.
    Related source file is seg7_driver.v.
    Found 1-bit register for signal <anode0>.
    Found 1-bit register for signal <anode1>.
    Found 1-bit register for signal <anode2>.
    Found 1-bit register for signal <anode3>.
    Found 2-bit adder for signal <$old_clk_int_1>.
    Found 2-bit register for signal <clk_int>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <seg7_driver> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit adder                       : 1
# Registers                        : 5
 1-bit register                    : 4
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg7_driver> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seg7_driver, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : seg7_driver.ngr
Top Level Output File Name         : seg7_driver
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 38

Macro Statistics :
# Registers                        : 5
#      1-bit register              : 4
#      2-bit register              : 1

Cell Usage :
# BELS                             : 22
#      LUT1_L                      : 1
#      LUT2_L                      : 5
#      LUT3                        : 8
#      LUT4                        : 8
# FlipFlops/Latches                : 6
#      FDC                         : 3
#      FDP                         : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 37
#      IBUF                        : 25
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                      13  out of    768     1%  
 Number of Slice Flip Flops:             6  out of   1536     0%  
 Number of 4 input LUTs:                22  out of   1536     1%  
 Number of bonded IOBs:                 37  out of    144    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_200hz                          | BUFGP                  | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 4.008ns (Maximum Frequency: 249.501MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 10.829ns
   Maximum combinational path delay: 9.647ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk_200hz'
Delay:               4.008ns (Levels of Logic = 1)
  Source:            clk_int_0 (FF)
  Destination:       clk_int_0 (FF)
  Source Clock:      clk_200hz rising
  Destination Clock: clk_200hz rising

  Data Path: clk_int_0 to clk_int_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              6   1.085   1.665  clk_int_0 (clk_int_0)
     LUT2_L:I0->LO         1   0.549   0.000  _n00001 (_n0000)
     FDP:D                     0.709          anode3
    ----------------------------------------
    Total                      4.008ns (2.343ns logic, 1.665ns route)
                                       (58.5% logic, 41.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_200hz'
Offset:              10.829ns (Levels of Logic = 3)
  Source:            anode1 (FF)
  Destination:       digit<7> (PAD)
  Source Clock:      clk_200hz rising

  Data Path: anode1 to digit<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              9   1.085   1.908  anode1 (anode1_OBUF)
     LUT4:I0->O            1   0.549   1.035  digit<0>_SW0 (N656)
     LUT3:I1->O            1   0.549   1.035  digit<0> (digit_0_OBUF)
     OBUF:I->O                 4.668          digit_0_OBUF (digit<0>)
    ----------------------------------------
    Total                     10.829ns (6.851ns logic, 3.978ns route)
                                       (63.3% logic, 36.7% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               9.647ns (Levels of Logic = 4)
  Source:            dig2<7> (PAD)
  Destination:       digit<7> (PAD)

  Data Path: dig2<7> to digit<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.776   1.035  dig2_7_IBUF (dig2_7_IBUF)
     LUT4:I2->O            1   0.549   1.035  digit<7>_SW0 (N780)
     LUT3:I1->O            1   0.549   1.035  digit<7> (digit_7_OBUF)
     OBUF:I->O                 4.668          digit_7_OBUF (digit<7>)
    ----------------------------------------
    Total                      9.647ns (6.542ns logic, 3.105ns route)
                                       (67.8% logic, 32.2% route)

=========================================================================
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Total memory usage is 53944 kilobytes


