Release 6.2i - netgen G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Reading design pid_sysgen_clk_wrapper.ngd ...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
Adding the appropriate PHYSONLY signals to the appropriate simprims.
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist pid_sysgen_clk_wrapper_translate.vhd ...
Total memory usage is 37232 kilobytes
