-- VHDL model created from top_level2.sch - Sat Jul 23 18:59:18 2005


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity top_level2 is
   port ( clk_sg  : in    std_logic; 
          in_x_0  : in    std_logic_vector (15 downto 0); 
          reset   : in    std_logic; 
          anode0  : out   std_logic; 
          anode1  : out   std_logic; 
          anode2  : out   std_logic; 
          anode3  : out   std_logic; 
          cathode : out   std_logic_vector (7 downto 0));
end top_level2;

architecture BEHAVIORAL of top_level2 is
   attribute BOX_TYPE   : STRING ;
   signal ce_sg   : std_logic;
   signal out_led : std_logic_vector (23 downto 0);
   signal XLXN_1  : std_logic;
   component clk_div
      port ( clock_sys : in    std_logic; 
             reset     : in    std_logic; 
             clock_div : out   std_logic);
   end component;
   
   component seg7_driver
      port ( clk_200hz : in    std_logic; 
             reset     : in    std_logic; 
             dig0      : in    std_logic_vector (7 downto 0); 
             dig1      : in    std_logic_vector (7 downto 0); 
             dig2      : in    std_logic_vector (7 downto 0); 
             anode0    : out   std_logic; 
             anode1    : out   std_logic; 
             anode2    : out   std_logic; 
             anode3    : out   std_logic; 
             digit     : out   std_logic_vector (7 downto 0));
   end component;
   
   component simple1
      port ( ce_sg   : in    std_logic; 
             clk_sg  : in    std_logic; 
             in_x_0  : in    std_logic_vector (15 downto 0); 
             out_x_0 : out   std_logic_vector (23 downto 0));
   end component;
   
   component VCC
      port ( P : out   std_logic);
   end component;
   attribute BOX_TYPE of VCC : COMPONENT is "BLACK_BOX";
   
begin
   XLXI_3 : clk_div
      port map (clock_sys=>clk_sg, reset=>reset, clock_div=>XLXN_1);
   
   XLXI_4 : seg7_driver
      port map (clk_200hz=>XLXN_1, dig0(7 downto 0)=>out_led(7 downto 0),
            dig1(7 downto 0)=>out_led(15 downto 8), dig2(7 downto
            0)=>out_led(23 downto 16), reset=>reset, anode0=>anode0,
            anode1=>anode1, anode2=>anode2, anode3=>anode3, digit(7 downto
            0)=>cathode(7 downto 0));
   
   XLXI_9 : simple1
      port map (ce_sg=>ce_sg, clk_sg=>clk_sg, in_x_0(15 downto 0)=>in_x_0(15
            downto 0), out_x_0(23 downto 0)=>out_led(23 downto 0));
   
   XLXI_10 : VCC
      port map (P=>ce_sg);
   
end BEHAVIORAL;


