Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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CPU : 0.00 / 0.56 s | Elapsed : 0.00 / 0.00 s
 
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xdcsp/pid_sysgen2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/xdcsp/pid_sysgen2_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <pid_sysgen2_addsub1> (Architecture <behavior>) compiled.
Entity <pid_sysgen2_cmult3> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <pid_sysgen2> (Architecture <structural>) compiled.
Entity <pid_sysgen2_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file C:/MATLAB6p5/work/xdcsp/pid_sysgen2_clk_wrapper.vhd in Library work.
Entity <pid_sysgen2_clk_wrapper> (Architecture <structural>) compiled.
CPU : 0.45 / 1.01 s | Elapsed : 1.00 / 1.00 s
 
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Total memory usage is 47844 kilobytes


