-- C:\MATLAB6P5\WORK\XDCSP3\XDCSP_3
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 26 13:56:26 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.CONV_PKG.ALL;
USE WORK.CLOCK_PKG.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test3 IS
END test3;

ARCHITECTURE testbench_arch OF test3 IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\matlab6p5\work\xdcsp3\xdcsp_3\test3.ano";
	COMPONENT pid_sysgen_clk_wrapper
		PORT (
			ce : In  std_logic;
			clk : In  std_logic;
			gateway_in1 : In  std_logic_vector (15 DOWNTO 0);
			gateway_out : Out  std_logic_vector (23 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL ce : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL gateway_in1 : std_logic_vector (15 DOWNTO 0);
	SIGNAL gateway_out : std_logic_vector (23 DOWNTO 0);

BEGIN
	UUT : pid_sysgen_clk_wrapper
	PORT MAP (
		ce => ce,
		clk => clk,
		gateway_in1 => gateway_in1,
		gateway_out => gateway_out
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_gateway_out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",gateway_out,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, gateway_out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 1 ms;
		TX_TIME := TX_TIME + 1;
		clk <= transport '1';
		WAIT FOR 1 ms;
		TX_TIME := TX_TIME + 1;
		ANNOTATE_gateway_out(TX_TIME);
		WAIT FOR 4 ms;
		TX_TIME := TX_TIME + 4;
		clk <= transport '0';
		WAIT FOR 4 ms;
		TX_TIME := TX_TIME + 4;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		ce <= transport '0';
		gateway_in1 <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 10 ms; -- Time=10 ms
		gateway_in1 <= transport std_logic_vector'("1010101111001101"); --ABCD
		-- --------------------
		WAIT FOR 10 ms; -- Time=20 ms
		gateway_in1 <= transport std_logic_vector'("0000000111111111"); --1FF
		-- --------------------
		WAIT FOR 10 ms; -- Time=30 ms
		gateway_in1 <= transport std_logic_vector'("1110110000010000"); --EC10
		-- --------------------
		WAIT FOR 11 ms; -- Time=41 ms
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION pid_sysgen_clk_wrapper_cfg OF test3 IS
	FOR testbench_arch
	END FOR;
END pid_sysgen_clk_wrapper_cfg;
