(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2005 7 12 11 15 34)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.2i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2003 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_has_bypass_with_cin = false ")
       (comment "c_a_type = 0 ")
       (comment "c_has_sclr = true ")
       (comment "c_sync_priority = 1 ")
       (comment "c_has_aset = false ")
       (comment "c_has_b_out = false ")
       (comment "c_has_s = true ")
       (comment "c_has_q = false ")
       (comment "InstanceName = adder_subtracter_spartan2_6_0_20d492340947cbb3 ")
       (comment "c_family = virtex ")
       (comment "c_bypass_enable = false ")
       (comment "c_b_constant = false ")
       (comment "c_has_ovfl = false ")
       (comment "c_high_bit = 8 ")
       (comment "c_latency = 0 ")
       (comment "c_sinit_val = 0 ")
       (comment "c_has_bypass = false ")
       (comment "c_pipe_stages = 1 ")
       (comment "c_has_sset = false ")
       (comment "c_has_ainit = false ")
       (comment "c_has_a_signed = false ")
       (comment "c_has_q_c_out = false ")
       (comment "c_b_type = 0 ")
       (comment "c_has_add = false ")
       (comment "c_has_sinit = false ")
       (comment "c_has_b_in = false ")
       (comment "c_has_b_signed = false ")
       (comment "c_bypass_low = false ")
       (comment "c_enable_rlocs = true ")
       (comment "c_b_value = 0 ")
       (comment "c_add_mode = 1 ")
       (comment "c_has_aclr = false ")
       (comment "c_out_width = 9 ")
       (comment "c_ainit_val = 0000 ")
       (comment "c_low_bit = 0 ")
       (comment "c_has_q_ovfl = false ")
       (comment "c_has_q_b_out = false ")
       (comment "c_has_c_out = false ")
       (comment "c_b_width = 9 ")
       (comment "c_a_width = 9 ")
       (comment "c_sync_enable = 0 ")
       (comment "c_has_ce = true ")
       (comment "c_has_c_in = false ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell XORCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port LI (direction INPUT))
                   (port CI (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell adder_subtracter_spartan2_6_0_20d492340947cbb3
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename A_0_ "A(0)") (direction INPUT))
   (port ( rename A_1_ "A(1)") (direction INPUT))
   (port ( rename A_2_ "A(2)") (direction INPUT))
   (port ( rename A_3_ "A(3)") (direction INPUT))
   (port ( rename A_4_ "A(4)") (direction INPUT))
   (port ( rename A_5_ "A(5)") (direction INPUT))
   (port ( rename A_6_ "A(6)") (direction INPUT))
   (port ( rename A_7_ "A(7)") (direction INPUT))
   (port ( rename A_8_ "A(8)") (direction INPUT))
   (port ( rename B_0_ "B(0)") (direction INPUT))
   (port ( rename B_1_ "B(1)") (direction INPUT))
   (port ( rename B_2_ "B(2)") (direction INPUT))
   (port ( rename B_3_ "B(3)") (direction INPUT))
   (port ( rename B_4_ "B(4)") (direction INPUT))
   (port ( rename B_5_ "B(5)") (direction INPUT))
   (port ( rename B_6_ "B(6)") (direction INPUT))
   (port ( rename B_7_ "B(7)") (direction INPUT))
   (port ( rename B_8_ "B(8)") (direction INPUT))
   (port ( rename S_0_ "S(0)") (direction OUTPUT))
   (port ( rename S_1_ "S(1)") (direction OUTPUT))
   (port ( rename S_2_ "S(2)") (direction OUTPUT))
   (port ( rename S_3_ "S(3)") (direction OUTPUT))
   (port ( rename S_4_ "S(4)") (direction OUTPUT))
   (port ( rename S_5_ "S(5)") (direction OUTPUT))
   (port ( rename S_6_ "S(6)") (direction OUTPUT))
   (port ( rename S_7_ "S(7)") (direction OUTPUT))
   (port ( rename S_8_ "S(8)") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU3
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "r4c0.S1"))
      (property INIT (string "9999"))
   )
   (instance BU4
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "r4c0.S1"))
   )
   (instance BU5
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "r4c0.S1"))
   )
   (instance BU7
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "r4c0.S1"))
      (property INIT (string "9999"))
   )
   (instance BU8
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "r4c0.S1"))
   )
   (instance BU9
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "r4c0.S1"))
   )
   (instance BU11
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
      (property INIT (string "9999"))
   )
   (instance BU12
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
   )
   (instance BU13
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
   )
   (instance BU15
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
      (property INIT (string "9999"))
   )
   (instance BU16
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
   )
   (instance BU17
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
   )
   (instance BU19
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
      (property INIT (string "9999"))
   )
   (instance BU20
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
   )
   (instance BU21
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
   )
   (instance BU23
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
      (property INIT (string "9999"))
   )
   (instance BU24
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
   )
   (instance BU25
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
   )
   (instance BU27
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
      (property INIT (string "9999"))
   )
   (instance BU28
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
   )
   (instance BU29
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
   )
   (instance BU31
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
      (property INIT (string "9999"))
   )
   (instance BU32
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
   )
   (instance BU33
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
   )
   (instance BU35
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "r0c0.S1"))
      (property INIT (string "9999"))
   )
   (instance BU36
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "r0c0.S1"))
   )
   (net N0
    (joined
      (portRef G (instanceRef GND))
      (portRef I2 (instanceRef BU3))
      (portRef I3 (instanceRef BU3))
      (portRef I2 (instanceRef BU7))
      (portRef I3 (instanceRef BU7))
      (portRef I2 (instanceRef BU11))
      (portRef I3 (instanceRef BU11))
      (portRef I2 (instanceRef BU15))
      (portRef I3 (instanceRef BU15))
      (portRef I2 (instanceRef BU19))
      (portRef I3 (instanceRef BU19))
      (portRef I2 (instanceRef BU23))
      (portRef I3 (instanceRef BU23))
      (portRef I2 (instanceRef BU27))
      (portRef I3 (instanceRef BU27))
      (portRef I2 (instanceRef BU31))
      (portRef I3 (instanceRef BU31))
      (portRef I2 (instanceRef BU35))
      (portRef I3 (instanceRef BU35))
    )
   )
   (net N1
    (joined
      (portRef P (instanceRef VCC))
      (portRef CI (instanceRef BU4))
      (portRef CI (instanceRef BU5))
    )
   )
   (net N2
    (joined
      (portRef S (instanceRef BU4))
      (portRef LI (instanceRef BU5))
      (portRef O (instanceRef BU3))
    )
   )
   (net N5
    (joined
      (portRef O (instanceRef BU4))
      (portRef CI (instanceRef BU8))
      (portRef CI (instanceRef BU9))
    )
   )
   (net N7
    (joined
      (portRef S (instanceRef BU8))
      (portRef LI (instanceRef BU9))
      (portRef O (instanceRef BU7))
    )
   )
   (net N10
    (joined
      (portRef O (instanceRef BU8))
      (portRef CI (instanceRef BU12))
      (portRef CI (instanceRef BU13))
    )
   )
   (net N12
    (joined
      (portRef S (instanceRef BU12))
      (portRef LI (instanceRef BU13))
      (portRef O (instanceRef BU11))
    )
   )
   (net N15
    (joined
      (portRef O (instanceRef BU12))
      (portRef CI (instanceRef BU16))
      (portRef CI (instanceRef BU17))
    )
   )
   (net N17
    (joined
      (portRef S (instanceRef BU16))
      (portRef LI (instanceRef BU17))
      (portRef O (instanceRef BU15))
    )
   )
   (net N20
    (joined
      (portRef O (instanceRef BU16))
      (portRef CI (instanceRef BU20))
      (portRef CI (instanceRef BU21))
    )
   )
   (net N22
    (joined
      (portRef S (instanceRef BU20))
      (portRef LI (instanceRef BU21))
      (portRef O (instanceRef BU19))
    )
   )
   (net N25
    (joined
      (portRef O (instanceRef BU20))
      (portRef CI (instanceRef BU24))
      (portRef CI (instanceRef BU25))
    )
   )
   (net N27
    (joined
      (portRef S (instanceRef BU24))
      (portRef LI (instanceRef BU25))
      (portRef O (instanceRef BU23))
    )
   )
   (net N30
    (joined
      (portRef O (instanceRef BU24))
      (portRef CI (instanceRef BU28))
      (portRef CI (instanceRef BU29))
    )
   )
   (net N32
    (joined
      (portRef S (instanceRef BU28))
      (portRef LI (instanceRef BU29))
      (portRef O (instanceRef BU27))
    )
   )
   (net N35
    (joined
      (portRef O (instanceRef BU28))
      (portRef CI (instanceRef BU32))
      (portRef CI (instanceRef BU33))
    )
   )
   (net N37
    (joined
      (portRef S (instanceRef BU32))
      (portRef LI (instanceRef BU33))
      (portRef O (instanceRef BU31))
    )
   )
   (net N40
    (joined
      (portRef O (instanceRef BU32))
      (portRef CI (instanceRef BU36))
    )
   )
   (net N42
    (joined
      (portRef LI (instanceRef BU36))
      (portRef O (instanceRef BU35))
    )
   )
   (net (rename N46 "A(0)")
    (joined
      (portRef A_0_)
      (portRef DI (instanceRef BU4))
      (portRef I0 (instanceRef BU3))
    )
   )
   (net (rename N47 "A(1)")
    (joined
      (portRef A_1_)
      (portRef DI (instanceRef BU8))
      (portRef I0 (instanceRef BU7))
    )
   )
   (net (rename N48 "A(2)")
    (joined
      (portRef A_2_)
      (portRef DI (instanceRef BU12))
      (portRef I0 (instanceRef BU11))
    )
   )
   (net (rename N49 "A(3)")
    (joined
      (portRef A_3_)
      (portRef DI (instanceRef BU16))
      (portRef I0 (instanceRef BU15))
    )
   )
   (net (rename N50 "A(4)")
    (joined
      (portRef A_4_)
      (portRef DI (instanceRef BU20))
      (portRef I0 (instanceRef BU19))
    )
   )
   (net (rename N51 "A(5)")
    (joined
      (portRef A_5_)
      (portRef DI (instanceRef BU24))
      (portRef I0 (instanceRef BU23))
    )
   )
   (net (rename N52 "A(6)")
    (joined
      (portRef A_6_)
      (portRef DI (instanceRef BU28))
      (portRef I0 (instanceRef BU27))
    )
   )
   (net (rename N53 "A(7)")
    (joined
      (portRef A_7_)
      (portRef DI (instanceRef BU32))
      (portRef I0 (instanceRef BU31))
    )
   )
   (net (rename N54 "A(8)")
    (joined
      (portRef A_8_)
      (portRef I0 (instanceRef BU35))
    )
   )
   (net (rename N55 "B(0)")
    (joined
      (portRef B_0_)
      (portRef I1 (instanceRef BU3))
    )
   )
   (net (rename N56 "B(1)")
    (joined
      (portRef B_1_)
      (portRef I1 (instanceRef BU7))
    )
   )
   (net (rename N57 "B(2)")
    (joined
      (portRef B_2_)
      (portRef I1 (instanceRef BU11))
    )
   )
   (net (rename N58 "B(3)")
    (joined
      (portRef B_3_)
      (portRef I1 (instanceRef BU15))
    )
   )
   (net (rename N59 "B(4)")
    (joined
      (portRef B_4_)
      (portRef I1 (instanceRef BU19))
    )
   )
   (net (rename N60 "B(5)")
    (joined
      (portRef B_5_)
      (portRef I1 (instanceRef BU23))
    )
   )
   (net (rename N61 "B(6)")
    (joined
      (portRef B_6_)
      (portRef I1 (instanceRef BU27))
    )
   )
   (net (rename N62 "B(7)")
    (joined
      (portRef B_7_)
      (portRef I1 (instanceRef BU31))
    )
   )
   (net (rename N63 "B(8)")
    (joined
      (portRef B_8_)
      (portRef I1 (instanceRef BU35))
    )
   )
   (net (rename N64 "S(0)")
    (joined
      (portRef S_0_)
      (portRef O (instanceRef BU5))
    )
   )
   (net (rename N65 "S(1)")
    (joined
      (portRef S_1_)
      (portRef O (instanceRef BU9))
    )
   )
   (net (rename N66 "S(2)")
    (joined
      (portRef S_2_)
      (portRef O (instanceRef BU13))
    )
   )
   (net (rename N67 "S(3)")
    (joined
      (portRef S_3_)
      (portRef O (instanceRef BU17))
    )
   )
   (net (rename N68 "S(4)")
    (joined
      (portRef S_4_)
      (portRef O (instanceRef BU21))
    )
   )
   (net (rename N69 "S(5)")
    (joined
      (portRef S_5_)
      (portRef O (instanceRef BU25))
    )
   )
   (net (rename N70 "S(6)")
    (joined
      (portRef S_6_)
      (portRef O (instanceRef BU29))
    )
   )
   (net (rename N71 "S(7)")
    (joined
      (portRef S_7_)
      (portRef O (instanceRef BU33))
    )
   )
   (net (rename N72 "S(8)")
    (joined
      (portRef S_8_)
      (portRef O (instanceRef BU36))
    )
   )
))))
(design adder_subtracter_spartan2_6_0_20d492340947cbb3 (cellRef adder_subtracter_spartan2_6_0_20d492340947cbb3 (libraryRef test_lib))
  (property X_CORE_INFO (string "C_ADDSUB_V6_0, Coregen 6.2i"))
  (property PART (string "XCV100BG256") (owner "Xilinx")))
)
