
SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = true
CSET latency = 0
CSET operation = add
CSET output_options = non_registered
CSET output_width = 68
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 68
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 68
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_5c367c18f02e1774
GENERATE

SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = true
CSET latency = 0
CSET operation = add
CSET output_options = non_registered
CSET output_width = 67
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 67
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 67
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_7f6afff41f5f7a54
GENERATE

SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = true
CSET latency = 0
CSET operation = add
CSET output_options = non_registered
CSET output_width = 40
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 40
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 40
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_9b2656d23c19deaf
GENERATE

SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = true
CSET latency = 0
CSET operation = subtract
CSET output_options = non_registered
CSET output_width = 21
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 21
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 21
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf
GENERATE

SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = false
CSET latency = 0
CSET operation = add
CSET output_options = non_registered
CSET output_width = 69
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 69
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 69
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_c14c50981235b92f
GENERATE

SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Adder_Subtracter Spartan2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET asynchronous_settings = none
CSET bypass = false
CSET bypass_sense = active_high
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET ce_override_for_bypass = true
CSET ce_overrides = sync_controls_override_ce
CSET clock_enable = true
CSET create_rpm = true
CSET latency = 0
CSET operation = subtract
CSET output_options = non_registered
CSET output_width = 39
CSET overflow_output = false
CSET port_a_sign = signed
CSET port_a_width = 39
CSET port_b_constant = false
CSET port_b_constant_value = 0
CSET port_b_sign = signed
CSET port_b_width = 39
CSET set_clear_priority = clear_overrides_set
CSET sync_init_value = 0
CSET synchronous_settings = clear
CSET component_name = adder_subtracter_spartan2_6_0_c9cda3f921770426
GENERATE

SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET asynchronous_clear = false
CSET clk_cycles_per_input = 1
CSET clock_enable = false
CSET create_rpm = true
CSET memory_type = Distributed_Memory
CSET multiplier_type = Parallel
CSET nd = false
CSET output_hold_register = false
CSET output_options = Non_Registered
CSET output_width = 56
CSET pipelined = Minimum
CSET port_a_data = Signed
CSET port_a_width = 40
CSET port_b_constant = true
CSET port_b_constant_value = 7800
CSET port_b_data = Unsigned
CSET port_b_width = 13
CSET rdy = false
CSET register_input = false
CSET reloadable = false
CSET rfd = false
CSET style = Rectangular_Shape
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_1b58cf9c5190cfad
GENERATE

SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET asynchronous_clear = false
CSET clk_cycles_per_input = 1
CSET clock_enable = false
CSET create_rpm = true
CSET memory_type = Distributed_Memory
CSET multiplier_type = Parallel
CSET nd = false
CSET output_hold_register = false
CSET output_options = Non_Registered
CSET output_width = 37
CSET pipelined = Minimum
CSET port_a_data = Signed
CSET port_a_width = 21
CSET port_b_constant = true
CSET port_b_constant_value = 4475
CSET port_b_data = Unsigned
CSET port_b_width = 13
CSET rdy = false
CSET register_input = false
CSET reloadable = false
CSET rfd = false
CSET style = Rectangular_Shape
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_7808bd7aeb700524
GENERATE

SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET asynchronous_clear = false
CSET clk_cycles_per_input = 1
CSET clock_enable = false
CSET create_rpm = true
CSET memory_type = Distributed_Memory
CSET multiplier_type = Parallel
CSET nd = false
CSET output_hold_register = false
CSET output_options = Non_Registered
CSET output_width = 38
CSET pipelined = Minimum
CSET port_a_data = Signed
CSET port_a_width = 20
CSET port_b_constant = true
CSET port_b_constant_value = 128
CSET port_b_data = Unsigned
CSET port_b_width = 8
CSET rdy = false
CSET register_input = false
CSET reloadable = false
CSET rfd = false
CSET style = Rectangular_Shape
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_d65c3216ed700608
GENERATE

SETPROJECT ./
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET asynchronous_clear = false
CSET clk_cycles_per_input = 1
CSET clock_enable = false
CSET create_rpm = true
CSET memory_type = Distributed_Memory
CSET multiplier_type = Parallel
CSET nd = false
CSET output_hold_register = false
CSET output_options = Non_Registered
CSET output_width = 38
CSET pipelined = Minimum
CSET port_a_data = Signed
CSET port_a_width = 20
CSET port_b_constant = true
CSET port_b_constant_value = 3
CSET port_b_data = Unsigned
CSET port_b_width = 2
CSET rdy = false
CSET register_input = false
CSET reloadable = false
CSET rfd = false
CSET style = Rectangular_Shape
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_eb0d20c59a93ecea
GENERATE
