-- C:\MATLAB6P5\WORK\XDCSP2
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Apr 28 17:07:53 2005
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.CONV_PKG.ALL;
USE WORK.CLOCK_PKG.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test6_tbw IS
END test6_tbw;

ARCHITECTURE testbench_arch OF test6_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT pid_sysgen_clk_wrapper
		PORT (
			ce : In  std_logic;
			clk : In  std_logic;
			gateway_in1 : In  std_logic_vector (15 DOWNTO 0);
			gateway_out : Out  std_logic_vector (23 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL ce : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL gateway_in1 : std_logic_vector (15 DOWNTO 0);
	SIGNAL gateway_out : std_logic_vector (23 DOWNTO 0);

BEGIN
	UUT : pid_sysgen_clk_wrapper
	PORT MAP (
		ce => ce,
		clk => clk,
		gateway_in1 => gateway_in1,
		gateway_out => gateway_out
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 1 ms;
		clk <= transport '1';
		WAIT FOR 1 ms;
		WAIT FOR 4 ms;
		clk <= transport '0';
		WAIT FOR 4 ms;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_gateway_out(
			next_gateway_out : std_logic_vector (23 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (gateway_out /= next_gateway_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ms gateway_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, gateway_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_gateway_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		ce <= transport '0';
		gateway_in1 <= transport std_logic_vector'("0000000110000000"); --180
		-- --------------------
		WAIT FOR 2 ms; -- Time=2 ms
		CHECK_gateway_out("000001101000111000110100",2); --68E34
		-- --------------------
		WAIT FOR 8 ms; -- Time=10 ms
		gateway_in1 <= transport std_logic_vector'("0000001010000000"); --280
		-- --------------------
		WAIT FOR 2 ms; -- Time=12 ms
		CHECK_gateway_out("000010101110110100001100",12); --AED0C
		-- --------------------
		WAIT FOR 8 ms; -- Time=20 ms
		gateway_in1 <= transport std_logic_vector'("0000001110000000"); --380
		-- --------------------
		WAIT FOR 2 ms; -- Time=22 ms
		CHECK_gateway_out("000011110100101111101011",22); --F4BEB
		-- --------------------
		WAIT FOR 8 ms; -- Time=30 ms
		gateway_in1 <= transport std_logic_vector'("0000010010000000"); --480
		-- --------------------
		WAIT FOR 2 ms; -- Time=32 ms
		CHECK_gateway_out("000100111010101011010001",32); --13AAD1
		-- --------------------
		WAIT FOR 8 ms; -- Time=40 ms
		gateway_in1 <= transport std_logic_vector'("0000010110000000"); --580
		-- --------------------
		WAIT FOR 2 ms; -- Time=42 ms
		CHECK_gateway_out("000110000000100110111110",42); --1809BE
		-- --------------------
		WAIT FOR 8 ms; -- Time=50 ms
		gateway_in1 <= transport std_logic_vector'("0000011010000000"); --680
		-- --------------------
		WAIT FOR 2 ms; -- Time=52 ms
		CHECK_gateway_out("000111000110100010110010",52); --1C68B2
		-- --------------------
		WAIT FOR 8 ms; -- Time=60 ms
		gateway_in1 <= transport std_logic_vector'("0000011110000000"); --780
		-- --------------------
		WAIT FOR 2 ms; -- Time=62 ms
		CHECK_gateway_out("001000001100011110101101",62); --20C7AD
		-- --------------------
		WAIT FOR 8 ms; -- Time=70 ms
		gateway_in1 <= transport std_logic_vector'("0000100110000000"); --980
		-- --------------------
		WAIT FOR 2 ms; -- Time=72 ms
		CHECK_gateway_out("001010011000010101111101",72); --29857D
		-- --------------------
		WAIT FOR 8 ms; -- Time=80 ms
		gateway_in1 <= transport std_logic_vector'("0000101010000000"); --A80
		-- --------------------
		WAIT FOR 2 ms; -- Time=82 ms
		CHECK_gateway_out("001011011110010010001101",82); --2DE48D
		-- --------------------
		WAIT FOR 8 ms; -- Time=90 ms
		gateway_in1 <= transport std_logic_vector'("0000101110000000"); --B80
		-- --------------------
		WAIT FOR 2 ms; -- Time=92 ms
		CHECK_gateway_out("001100100100001110100100",92); --3243A4
		-- --------------------
		WAIT FOR 8 ms; -- Time=100 ms
		ce <= transport '1';
		gateway_in1 <= transport std_logic_vector'("0000110010000000"); --C80
		-- --------------------
		WAIT FOR 2 ms; -- Time=102 ms
		CHECK_gateway_out("001101101010001011000010",102); --36A2C2
		-- --------------------
		WAIT FOR 8 ms; -- Time=110 ms
		gateway_in1 <= transport std_logic_vector'("0000110110000000"); --D80
		-- --------------------
		WAIT FOR 2 ms; -- Time=112 ms
		CHECK_gateway_out("001110110000000111100111",112); --3B01E7
		-- --------------------
		WAIT FOR 8 ms; -- Time=120 ms
		gateway_in1 <= transport std_logic_vector'("0000111010000000"); --E80
		-- --------------------
		WAIT FOR 2 ms; -- Time=122 ms
		CHECK_gateway_out("001111110110000100010011",122); --3F6113
		-- --------------------
		WAIT FOR 8 ms; -- Time=130 ms
		gateway_in1 <= transport std_logic_vector'("0000111110000000"); --F80
		-- --------------------
		WAIT FOR 2 ms; -- Time=132 ms
		CHECK_gateway_out("010000111100000001000110",132); --43C046
		-- --------------------
		WAIT FOR 8 ms; -- Time=140 ms
		gateway_in1 <= transport std_logic_vector'("0001000010000000"); --1080
		-- --------------------
		WAIT FOR 2 ms; -- Time=142 ms
		CHECK_gateway_out("010010000001111110000000",142); --481F80
		-- --------------------
		WAIT FOR 8 ms; -- Time=150 ms
		gateway_in1 <= transport std_logic_vector'("0001000110000000"); --1180
		-- --------------------
		WAIT FOR 2 ms; -- Time=152 ms
		CHECK_gateway_out("010011000111111011000001",152); --4C7EC1
		-- --------------------
		WAIT FOR 8 ms; -- Time=160 ms
		gateway_in1 <= transport std_logic_vector'("0001001010000000"); --1280
		-- --------------------
		WAIT FOR 2 ms; -- Time=162 ms
		CHECK_gateway_out("010100001101111000001001",162); --50DE09
		-- --------------------
		WAIT FOR 8 ms; -- Time=170 ms
		gateway_in1 <= transport std_logic_vector'("0001001110000000"); --1380
		-- --------------------
		WAIT FOR 2 ms; -- Time=172 ms
		CHECK_gateway_out("010101010011110101011000",172); --553D58
		-- --------------------
		WAIT FOR 8 ms; -- Time=180 ms
		gateway_in1 <= transport std_logic_vector'("0001010010000000"); --1480
		-- --------------------
		WAIT FOR 2 ms; -- Time=182 ms
		CHECK_gateway_out("010110011001110010101110",182); --599CAE
		-- --------------------
		WAIT FOR 8 ms; -- Time=190 ms
		gateway_in1 <= transport std_logic_vector'("0000100010000000"); --880
		-- --------------------
		WAIT FOR 2 ms; -- Time=192 ms
		CHECK_gateway_out("001001010010101110010101",192); --252B95
		-- --------------------
		WAIT FOR 10 ms; -- Time=202 ms
		CHECK_gateway_out("001001010010101111010000",202); --252BD0
		-- --------------------
		WAIT FOR 4 ms; -- Time=206 ms
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION pid_sysgen_clk_wrapper_cfg OF test6_tbw IS
	FOR testbench_arch
	END FOR;
END pid_sysgen_clk_wrapper_cfg;
