Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.56 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.56 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: test1_pid_clk_wrapper.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : test1_pid_clk_wrapper.prj
Input Format                       : mixed
Synthesis Constraint File          : .\test1_pid_clk_wrapper.xcf
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : test1_pid_clk_wrapper
Output Format                      : NGC
Target Device                      : xc2s50-6-pq208

---- Source Options
Top Module Name                    : test1_pid_clk_wrapper
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : YES
Hierarchy Separator                : _
Bus Delimiter                      : ()
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : test1_pid_clk_wrapper.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xtest1_pid/test1_pid_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <test1_pid_addsub1> (Architecture <behavior>) compiled.
Entity <test1_pid_cmult3> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <test1_pid> (Architecture <structural>) compiled.
Entity <test1_pid_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file C:/MATLAB6p5/work/xtest1_pid/test1_pid_clk_wrapper.vhd in Library work.
Entity <test1_pid_clk_wrapper> (Architecture <structural>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <test1_pid_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <test1_pid_clk_wrapper> analyzed. Unit <test1_pid_clk_wrapper> generated.

Analyzing Entity <test1_pid_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 3498: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <test1_pid_clock_driver> analyzed. Unit <test1_pid_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <test1_pid> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2523: Unconnected input port 'c_in' of component 'test1_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2523: Unconnected output port 'c_out' of component 'test1_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2578: Unconnected input port 'c_in' of component 'test1_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2578: Unconnected output port 'c_out' of component 'test1_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2633: Unconnected input port 'c_in' of component 'test1_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2633: Unconnected output port 'c_out' of component 'test1_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2688: Unconnected input port 'c_in' of component 'test1_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2688: Unconnected output port 'c_out' of component 'test1_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2743: Unconnected input port 'c_in' of component 'test1_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2743: Unconnected output port 'c_out' of component 'test1_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2798: Unconnected input port 'c_in' of component 'test1_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2798: Unconnected output port 'c_out' of component 'test1_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2853: Unconnected input port 'core_ce' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2853: Unconnected input port 'core_clr' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2853: Unconnected input port 'core_clk' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2988: Unconnected input port 'core_ce' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2988: Unconnected input port 'core_clr' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 2988: Unconnected input port 'core_clk' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 3045: Unconnected input port 'core_ce' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 3045: Unconnected input port 'core_clr' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 3045: Unconnected input port 'core_clk' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 3102: Unconnected input port 'core_ce' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 3102: Unconnected input port 'core_clr' of component 'test1_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd line 3102: Unconnected input port 'core_clk' of component 'test1_pid_cmult3' is tied to default value.
Entity <test1_pid> analyzed. Unit <test1_pid> generated.

Analyzing generic Entity <test1_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_0acb0aea557e5b82"
	a_width = 20
	a_bin_pt = 12
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 24
	b_arith = 2
	s_width = 20
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 41
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 41
	c_b_width = 41
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 41
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test1_pid_addsub1> analyzed. Unit <test1_pid_addsub1> generated.

Analyzing generic Entity <test1_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_adf215fec985a9ef"
	a_width = 20
	a_bin_pt = 16
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 20
	b_bin_pt = 12
	b_arith = 2
	s_width = 20
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 25
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 25
	c_b_width = 25
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 25
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test1_pid_addsub1> analyzed. Unit <test1_pid_addsub10> generated.

Analyzing generic Entity <test1_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf"
	a_width = 20
	a_bin_pt = 12
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 20
	b_bin_pt = 12
	b_arith = 2
	s_width = 20
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 21
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 21
	c_b_width = 21
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 21
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test1_pid_addsub1> analyzed. Unit <test1_pid_addsub11> generated.

Analyzing generic Entity <test1_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_90518b17c7b8e21d"
	a_width = 20
	a_bin_pt = 16
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 32
	b_arith = 2
	s_width = 20
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 41
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 41
	c_b_width = 41
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 41
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test1_pid_addsub1> analyzed. Unit <test1_pid_addsub12> generated.

Analyzing generic Entity <test1_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_90518b17c7b8e21d"
	a_width = 40
	a_bin_pt = 32
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 40
	b_bin_pt = 32
	b_arith = 2
	s_width = 20
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 41
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 41
	c_b_width = 41
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 41
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test1_pid_addsub1> analyzed. Unit <test1_pid_addsub13> generated.

Analyzing generic Entity <test1_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_bfeb857b6aedd324"
	a_width = 20
	a_bin_pt = 16
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 20
	b_bin_pt = 16
	b_arith = 2
	s_width = 20
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 21
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 21
	c_b_width = 21
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 21
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test1_pid_addsub1> analyzed. Unit <test1_pid_addsub14> generated.

Analyzing generic Entity <test1_pid_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_563a757879af2243"
	a_width = 20
	a_bin_pt = 12
	a_arith = 2
	b_width = 4
	b_bin_pt = 12
	b_arith = 2
	p_width = 40
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 20
	c_b_width = 14
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 20
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 12
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 8192
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test1_pid_cmult3> analyzed. Unit <test1_pid_cmult3> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 20
	d_bin_pt = 12
	d_arith = 2
	q_width = 20
	q_bin_pt = 12
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 20
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 20
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 20
	d_bin_pt = 16
	d_arith = 2
	q_width = 20
	q_bin_pt = 16
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay5> generated.

Analyzing generic Entity <test1_pid_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_a8c29d1da441d87a"
	a_width = 20
	a_bin_pt = 16
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 32
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 20
	c_b_width = 20
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 20
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 1048575
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test1_pid_cmult3> analyzed. Unit <test1_pid_cmult36> generated.

Analyzing generic Entity <test1_pid_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_56bc14d72684fa6b"
	a_width = 20
	a_bin_pt = 12
	a_arith = 2
	b_width = 4
	b_bin_pt = 20
	b_arith = 2
	p_width = 40
	p_bin_pt = 32
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 20
	c_b_width = 7
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 20
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 20
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 105
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test1_pid_cmult3> analyzed. Unit <test1_pid_cmult37> generated.

Analyzing generic Entity <test1_pid_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_1b7fd325de7a184a"
	a_width = 20
	a_bin_pt = 16
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 40
	p_bin_pt = 32
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 20
	c_b_width = 19
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 20
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 286392
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 40
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test1_pid_cmult3> analyzed. Unit <test1_pid_cmult38> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


Reading constraint file .\test1_pid_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <test1_pid_cmult38>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test1_pid_cmult38> synthesized.


Synthesizing Unit <test1_pid_cmult37>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test1_pid_cmult37> synthesized.


Synthesizing Unit <test1_pid_cmult36>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test1_pid_cmult36> synthesized.


Synthesizing Unit <xldelay5>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
Unit <xldelay5> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <test1_pid_cmult3>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test1_pid_cmult3> synthesized.


Synthesizing Unit <test1_pid_addsub14>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<20>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test1_pid_addsub14> synthesized.


Synthesizing Unit <test1_pid_addsub13>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<40:36>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<15:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test1_pid_addsub13> synthesized.


Synthesizing Unit <test1_pid_addsub12>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<40:36>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<15:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test1_pid_addsub12> synthesized.


Synthesizing Unit <test1_pid_addsub11>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<20:16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test1_pid_addsub11> synthesized.


Synthesizing Unit <test1_pid_addsub10>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<24:20>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test1_pid_addsub10> synthesized.


Synthesizing Unit <test1_pid_addsub1>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<40:28>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<7:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test1_pid_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <test1_pid>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
Unit <test1_pid> synthesized.


Synthesizing Unit <test1_pid_clock_driver>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <test1_pid_clock_driver> synthesized.


Synthesizing Unit <test1_pid_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/xtest1_pid/test1_pid_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <test1_pid_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <test1_pid_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_0acb0aea557e5b82.edn" "adder_subtracter_spartan2_6_0_0acb0aea557e5b82.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_0acb0aea557e5b82.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_adf215fec985a9ef.edn" "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_adf215fec985a9ef.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.edn" "adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_90518b17c7b8e21d.edn" "adder_subtracter_spartan2_6_0_90518b17c7b8e21d.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_90518b17c7b8e21d.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_bfeb857b6aedd324.edn" "adder_subtracter_spartan2_6_0_bfeb857b6aedd324.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_bfeb857b6aedd324.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_563a757879af2243.edn" "multiplier_spartan2_6_0_563a757879af2243.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_563a757879af2243.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_a8c29d1da441d87a.edn" "multiplier_spartan2_6_0_a8c29d1da441d87a.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_a8c29d1da441d87a.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_56bc14d72684fa6b.edn" "multiplier_spartan2_6_0_56bc14d72684fa6b.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_56bc14d72684fa6b.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_1b7fd325de7a184a.edn" "multiplier_spartan2_6_0_1b7fd325de7a184a.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_1b7fd325de7a184a.ngo"...
Loading core <adder_subtracter_spartan2_6_0_0acb0aea557e5b82> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_adf215fec985a9ef> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_ab6dddc65e4e93cf> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_90518b17c7b8e21d> for timing and area information for instance <core_instance6>.
Loading core <adder_subtracter_spartan2_6_0_90518b17c7b8e21d> for timing and area information for instance <core_instance6>.
Loading core <adder_subtracter_spartan2_6_0_bfeb857b6aedd324> for timing and area information for instance <core_instance10>.
Loading core <multiplier_spartan2_6_0_563a757879af2243> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_a8c29d1da441d87a> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_56bc14d72684fa6b> for timing and area information for instance <core_instance4>.
Loading core <multiplier_spartan2_6_0_1b7fd325de7a184a> for timing and area information for instance <core_instance6>.

Optimizing unit <test1_pid_clk_wrapper> ...

Optimizing unit <srl17e> ...
Loading device for application Xst from file 'v50.nph' in environment E:/xilinx_62.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\test1_pid_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block test1_pid_clk_wrapper, actual ratio is 51.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : test1_pid_clk_wrapper.ngr
Top Level Output File Name         : test1_pid_clk_wrapper
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 42

Cell Usage :
# BELS                             : 1699
#      BUF                         : 160
#      GND                         : 11
#      LUT4                        : 678
#      MUXCY                       : 419
#      VCC                         : 3
#      XORCY                       : 428
# FlipFlops/Latches                : 60
#      FDE                         : 60
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 40
#      IBUF                        : 20
#      OBUF                        : 20
# Others                           : 1
#      TIMESPEC                    : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     398  out of    768    51%  
 Number of Slice Flip Flops:            60  out of   1536     3%  
 Number of 4 input LUTs:               678  out of   1536    44%  
 Number of bonded IOBs:                 40  out of    144    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 60    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 31.135ns (Maximum Frequency: 32.118MHz)
   Minimum input arrival time before clock: 27.491ns
   Maximum output required time after clock: 36.300ns
   Maximum combinational path delay: 32.656ns
-------------------------------------------------------------------------

Timing constraint: TS_clk_3d74174a = PERIOD TIMEGRP "clk_3d74174a" 100 nS HIGH 50 nS
-------------------------------------------------------------------------
Slack:                  68.865ns
  Source:               test1_pid_top_delay_synth_reg_srl_inst_last_srl17e_u20 (FF)
  Destination:          test1_pid_top_delay1_synth_reg_srl_inst_last_srl17e_u219 (FF)
  Data Path Delay:      31.135ns (Levels of Logic = 58)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 100.000ns

  Data Path: test1_pid_top_delay_synth_reg_srl_inst_last_srl17e_u20 (FF) to test1_pid_top_delay1_synth_reg_srl_inst_last_srl17e_u219 (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   1.085   1.332  test1_pid_top_delay_synth_reg_srl_inst_last_srl17e_u20 (test1_pid_top_q(0))
     begin scope: 'test1_pid_top_cmult3_core_instance0'
     BUF:I->O              1   0.549   1.035  BU36 (o(13))
     end scope: 'test1_pid_top_cmult3_core_instance0'
     begin scope: 'test1_pid_top_addsub1_core_instance0'
     LUT4:I1->O            1   0.549   0.000  BU55 (N67)
     MUXCY:S->O            1   0.659   0.000  BU56 (N70)
     MUXCY:CI->O           1   0.042   0.000  BU60 (N75)
     MUXCY:CI->O           1   0.042   0.000  BU64 (N80)
     MUXCY:CI->O           1   0.042   0.000  BU68 (N85)
     MUXCY:CI->O           1   0.042   0.000  BU72 (N90)
     MUXCY:CI->O           1   0.042   0.000  BU76 (N95)
     MUXCY:CI->O           1   0.042   0.000  BU80 (N100)
     MUXCY:CI->O           1   0.042   0.000  BU84 (N105)
     MUXCY:CI->O           1   0.042   0.000  BU88 (N110)
     XORCY:CI->O           1   0.420   1.035  BU93 (S(22))
     end scope: 'test1_pid_top_addsub1_core_instance0'
     begin scope: 'test1_pid_top_addsub2_core_instance2'
     LUT4:I0->O            1   0.549   0.000  BU59 (N72)
     MUXCY:S->O            1   0.659   0.000  BU60 (N75)
     XORCY:CI->O          23   0.420   3.015  BU65 (S(15))
     end scope: 'test1_pid_top_addsub2_core_instance2'
     begin scope: 'test1_pid_top_kd_core_instance2'
     LUT4:I3->O            1   0.549   1.035  BU469 (N3678)
     LUT4:I1->O            1   0.549   0.000  BU572 (N11572)
     MUXCY:S->O            1   0.659   0.000  BU573 (N11575)
     MUXCY:CI->O           1   0.042   0.000  BU577 (N11580)
     MUXCY:CI->O           1   0.042   0.000  BU581 (N11585)
     MUXCY:CI->O           1   0.042   0.000  BU585 (N11590)
     MUXCY:CI->O           1   0.042   0.000  BU589 (N11595)
     MUXCY:CI->O           1   0.042   0.000  BU593 (N11600)
     MUXCY:CI->O           1   0.042   0.000  BU597 (N11605)
     MUXCY:CI->O           1   0.042   0.000  BU601 (N11610)
     MUXCY:CI->O           1   0.042   0.000  BU605 (N11615)
     MUXCY:CI->O           1   0.042   0.000  BU609 (N11620)
     MUXCY:CI->O           1   0.042   0.000  BU613 (N11625)
     MUXCY:CI->O           1   0.042   0.000  BU617 (N11630)
     MUXCY:CI->O           1   0.042   0.000  BU621 (N11635)
     MUXCY:CI->O           1   0.042   0.000  BU625 (N11640)
     MUXCY:CI->O           1   0.042   0.000  BU629 (N11645)
     MUXCY:CI->O           1   0.042   0.000  BU633 (N11650)
     MUXCY:CI->O           1   0.042   0.000  BU637 (N11655)
     XORCY:CI->O           1   0.420   1.035  BU642 (N1639)
     LUT4:I1->O            1   0.549   0.000  BU759 (N13197)
     MUXCY:S->O            1   0.659   0.000  BU760 (N13200)
     XORCY:CI->O           1   0.420   1.035  BU765 (N1671)
     LUT4:I0->O            1   0.549   0.000  BU965 (N14638)
     MUXCY:S->O            1   0.659   0.000  BU966 (N14641)
     XORCY:CI->O           1   0.420   1.035  BU971 (N274)
     BUF:I->O              1   0.549   1.035  BU1035 (o(32))
     end scope: 'test1_pid_top_kd_core_instance2'
     begin scope: 'test1_pid_top_addsub5_core_instance6'
     LUT4:I0->O            1   0.549   0.000  BU131 (N162)
     MUXCY:S->O            1   0.659   0.000  BU132 (N165)
     XORCY:CI->O           1   0.420   1.035  BU137 (S(33))
     end scope: 'test1_pid_top_addsub5_core_instance6'
     begin scope: 'test1_pid_top_addsub4_core_instance6'
     LUT4:I0->O            1   0.549   0.000  BU135 (N167)
     MUXCY:S->O            1   0.659   0.000  BU136 (N170)
     XORCY:CI->O           1   0.420   1.035  BU141 (S(34))
     end scope: 'test1_pid_top_addsub4_core_instance6'
     begin scope: 'test1_pid_top_addsub6_core_instance10'
     LUT4:I0->O            1   0.549   0.000  BU75 (N92)
     MUXCY:S->O            1   0.659   0.000  BU76 (N95)
     XORCY:CI->O           2   0.420   0.000  BU81 (S(19))
     end scope: 'test1_pid_top_addsub6_core_instance10'
     FDE:D                     0.709          test1_pid_top_delay1_synth_reg_srl_inst_last_srl17e_u219
    ----------------------------------------
    Total                     31.135ns (17.473ns logic, 13.662ns route)
                                       (56.1% logic, 43.9% route)

=========================================================================
CPU : 27.55 / 28.70 s | Elapsed : 28.00 / 29.00 s
 
--> 

Total memory usage is 78928 kilobytes


