## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Fri Jul 22 15:37:52 China Standard Time 2005
##
vlib work
vcom -93 -explicit  simple1_pkgs.vhd
vcom -93 -explicit  simple1_files.vhd
vlog  seg7_driver.v
vlog  clk_div.v
vcom -93 -explicit  top_level2.vhf
vcom -93 -explicit  tv1_tbw.vhw
vlog  "C:/Xilinx/verilog/src/glbl.v"
vsim -t 1ps  -L xilinxcorelib_ver -L unisims_ver  -lib work tv1_tbw glbl
do tv1_tbw.udo
view wave
add wave *
view structure
view signals
run -all
