# Xilinx CORE Generator 6.2i
# Username = Valencia
# COREGenPath = C:\ISEFndtn\coregen
# ProjectPath = C:\MATLAB6p5\work\DCSP\xdcsp\temp\coregen_tmp
# ExpandedProjectPath = C:\MATLAB6p5\work\DCSP\xdcsp\temp\coregen_tmp
# OverwriteFiles = True
# Core name: multiplier_spartan2_6_0_869519d31060e1ec
# Number of Primitives in design: 325
# Number of CLBs used in design: 44
# Number of Slices used in design: 76
# Number of LUT sites used in design: 149
# Number of LUTs used in design: 149
# Number of REG used in design: 0
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 1
# Huset "multiplier_spartan2_6_0_869519d31060e1ec/top_level/cc_mult/m3/r1" = (0, 0) to (5, 11) in CLBs
# 
SET BusFormat = BusFormatParen
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Other
SET FormalVerification = None
SET OutputProducts = ImpNetlist
SET SimElabOptions = CreateNdf
SELECT Multiplier Spartan2 Xilinx,_Inc. 6.0
CSET create_rpm = true
CSET clock_enable = false
CSET output_options = Non_Registered
CSET port_b_constant = true
CSET reloadable = false
CSET port_b_width = 13
CSET nd = false
CSET multiplier_type = Parallel
CSET port_a_width = 17
CSET memory_type = Distributed_Memory
CSET port_a_data = Signed
CSET rdy = false
CSET register_input = false
CSET synchronous_clear = false
CSET component_name = multiplier_spartan2_6_0_869519d31060e1ec
CSET port_b_data = Unsigned
CSET asynchronous_clear = false
CSET rfd = false
CSET clk_cycles_per_input = 1
CSET port_b_constant_value = 4475
CSET style = Rectangular_Shape
CSET pipelined = Minimum
CSET output_hold_register = false
CSET output_width = 33
GENERATE
