# Xilinx CORE Generator 6.2i
# User = WinXp
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in C:\MATLAB6p5\work\xskripsi\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=C:\MATLAB6p5\work\xskripsi
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=C:\MATLAB6p5\work\xskripsi
SETPROJECT .
Set current Project to C:\MATLAB6p5\work\xskripsi
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 3272
XIPCPJSENDCORES spartan2
