-- C:\MATLAB6P5\WORK\XDCSP2
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 26 07:34:13 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testdcsp_tbw IS
END testdcsp_tbw;

ARCHITECTURE testbench_arch OF testdcsp_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\matlab6p5\work\xdcsp2\testdcsp_tbw.ano";
	COMPONENT 
		PORT (
		);
	END COMPONENT;


BEGIN
	UUT : 
	PORT MAP (
	);

	PROCESS -- Annotate outputs process
		VARIABLE TX_TIME : INTEGER :=0;

	BEGIN
		CHECK_LOOP : LOOP
