-- C:\MATLAB6P5\WORK\XDCSP
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Mon Apr 11 12:33:50 2005
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.CONV_PKG.ALL;
USE WORK.CLOCK_PKG.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test_tbw IS
END test_tbw;

ARCHITECTURE testbench_arch OF test_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT pid_sysgen2_clk_wrapper
		PORT (
			ce : In  std_logic;
			clk : In  std_logic;
			gateway_in1 : In  std_logic_vector (19 DOWNTO 0);
			gateway_out : Out  std_logic_vector (23 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL ce : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL gateway_in1 : std_logic_vector (19 DOWNTO 0);
	SIGNAL gateway_out : std_logic_vector (23 DOWNTO 0);

BEGIN
	UUT : pid_sysgen2_clk_wrapper
	PORT MAP (
		ce => ce,
		clk => clk,
		gateway_in1 => gateway_in1,
		gateway_out => gateway_out
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		clk <= transport '1';
		WAIT FOR 10 ns;
		WAIT FOR 40 ns;
		clk <= transport '0';
		WAIT FOR 40 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_gateway_out(
			next_gateway_out : std_logic_vector (23 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (gateway_out /= next_gateway_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns gateway_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, gateway_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_gateway_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		ce <= transport '1';
		gateway_in1 <= transport std_logic_vector'("00000000000000001100"); --C
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		ce <= transport '0';
		-- --------------------
		WAIT FOR 800 ns; -- Time=900 ns
		ce <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		gateway_in1 <= transport std_logic_vector'("00000000000000010110"); --16
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION pid_sysgen2_clk_wrapper_cfg OF test_tbw IS
	FOR testbench_arch
	END FOR;
END pid_sysgen2_clk_wrapper_cfg;
