
-- VHDL Instantiation Created from source file pid_sysgen.vhd -- 22:07:29 04/11/2005
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT pid_sysgen
	PORT(
		ce_sg : IN std_logic;
		clk_sg : IN std_logic;
		gateway_in1 : IN std_logic_vector(15 downto 0);          
		gateway_out : OUT std_logic_vector(23 downto 0)
		);
	END COMPONENT;

	Inst_pid_sysgen: pid_sysgen PORT MAP(
		ce_sg => ,
		clk_sg => ,
		gateway_in1 => ,
		gateway_out => 
	);


