Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

TPSDP::  Mon Apr 04 14:28:08 2005


E:/xilinx_62/bin/nt/par.exe -w -intstyle ise -ol std -t 1
pid1sg_clk_wrapper_map.ncd pid1sg_clk_wrapper.ncd pid1sg_clk_wrapper.pcf 


Constraints file: pid1sg_clk_wrapper.pcf

Loading device database for application Par from file
"pid1sg_clk_wrapper_map.ncd".
   "pid1sg_clk_wrapper" is an NCD, version 2.38, device xc2s50, package pq208,
speed -6
Loading device for application Par from file 'v50.nph' in environment
E:/xilinx_62.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            32 out of 140    22%
      Number of LOCed External IOBs    0 out of 32      0%

   Number of SLICEs                  139 out of 768    18%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:9898ef) REAL time: 3 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.8
........
.
Phase 5.8 (Checksum:9c8ece) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file pid1sg_clk_wrapper.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 735 unrouted;       REAL time: 3 secs 

Phase 2: 706 unrouted;       REAL time: 3 secs 

Phase 3: 158 unrouted;       REAL time: 3 secs 

Phase 4: 158 unrouted; (0)      REAL time: 3 secs 

Phase 5: 158 unrouted; (0)      REAL time: 3 secs 

Phase 6: 158 unrouted; (0)      REAL time: 3 secs 

Phase 7: 0 unrouted; (0)      REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   29   |  0.079     |  0.464      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 177


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.290
   The MAXIMUM PIN DELAY IS:                               3.024
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.392

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         235         402          97           1           0           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clk_983892a7 = PERIOD TIMEGRP "clk_983 | 100.000ns  | 22.696ns   | 11   
  892a7"  100 nS   HIGH 50.000000 %         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  53 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file pid1sg_clk_wrapper.ncd.


PAR done.
