
-------------------------------------------------------------------
-- System Generator version 6.2 VHDL source file.
--
-- Copyright(C) 2004 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to any warranties or
-- representations that this implementation is free from claims of
-- infringement, implied warranties of merchantability or fitness for a
-- particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user’s
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2004 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

library IEEE;
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity test2_pid_addsub1 is
  generic (
    core_name0: string := "";
    a_width: integer := 16;
    a_bin_pt: integer := 4;
    a_arith: integer := xlUnsigned;
    c_in_width: integer := 16;
    c_in_bin_pt: integer := 4;
    c_in_arith: integer := xlUnsigned;
    c_out_width: integer := 16;
    c_out_bin_pt: integer := 4;
    c_out_arith: integer := xlUnsigned;
    b_width: integer := 8;
    b_bin_pt: integer := 2;
    b_arith: integer := xlUnsigned;
    s_width: integer := 17;
    s_bin_pt: integer := 4;
    s_arith: integer := xlUnsigned;
    rst_width: integer := 1;
    rst_bin_pt: integer := 0;
    rst_arith: integer := xlUnsigned;
    en_width: integer := 1;
    en_bin_pt: integer := 0;
    en_arith: integer := xlUnsigned;
    full_s_width: integer := 17;
    full_s_arith: integer := xlUnsigned;
    mode: integer := xlAddMode;
    extra_registers: integer := 0;
    latency: integer := 0;
    quantization: integer := xlTruncate;
    overflow: integer := xlWrap;
    c_a_width: integer := 16;
    c_b_width: integer := 8;
    c_a_type: integer := 1;
    c_b_type: integer := 1;
    c_add_mode: integer := 0;
    c_has_s: integer := 1;
    c_has_q: integer := 0;
    c_has_sclr: integer := 0;
    c_has_ce: integer := 0;
    c_latency: integer := 0;
    c_output_width: integer := 17;
    c_enable_rlocs: integer := 1;
    c_has_c_in  : integer := 0;
    c_has_b_in  : integer := 0;
    c_has_c_out : integer := 0;
    c_has_q_c_out : integer := 0;
    c_has_b_out : integer := 0;
    c_has_q_b_out : integer := 0;
    c_has_q_ovfl : integer := 0;
    c_has_ovfl : integer := 0;
    core: boolean := false
  );
  port (
    a: in std_logic_vector(a_width - 1 downto 0);
    b: in std_logic_vector(b_width - 1 downto 0);
    c_in : in std_logic_vector (0 downto 0) := "0";
    ce: in std_logic;
    clr: in std_logic;
    clk: in std_logic;
    rst: in std_logic_vector(rst_width - 1 downto 0);
    en: in std_logic_vector(en_width - 1 downto 0);
    c_out : out std_logic_vector (0 downto 0);
    s: out std_logic_vector(s_width - 1 downto 0)
  );
end test2_pid_addsub1;
architecture behavior of test2_pid_addsub1 is
  component synth_addsub
    generic (
      arith_type: integer;
      a_width: integer;
      b_width: integer;
      s_width: integer;
      mode: integer;
      use_cin : integer;
      use_bin : integer;
      latency: integer
    );
    port (
      a: in std_logic_vector(a_width - 1 downto 0);
      b: in std_logic_vector(b_width - 1 downto 0);
      cin : in std_logic_vector(0 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      cout : out std_logic_vector(0 downto 0);
      s: out std_logic_vector(s_width - 1 downto 0)
    );
  end component;
  component synth_reg
    generic (
      width: integer := 16;
      latency: integer := 5
    );
    port (
      i: in std_logic_vector(width - 1 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      o: out std_logic_vector(width - 1 downto 0)
    );
  end component;
  function format_input(inp: std_logic_vector; old_width, delta, new_arith,
                        new_width: integer)
    return std_logic_vector
  is
    variable vec: std_logic_vector(old_width-1 downto 0);
    variable padded_inp: std_logic_vector((old_width + delta)-1  downto 0);
    variable result: std_logic_vector(new_width-1 downto 0);
  begin
    vec := inp;
    if delta > 0 then
      padded_inp := pad_LSB(vec, old_width+delta);
      result := extend_MSB(padded_inp, new_width, new_arith);
    else
      result := extend_MSB(vec, new_width, new_arith);
    end if;
    return result;
  end;
  constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
  constant full_a_width: integer := full_s_width;
  constant full_b_width: integer := full_s_width;
  signal full_a: std_logic_vector(full_a_width - 1 downto 0);
  signal full_b: std_logic_vector(full_b_width - 1 downto 0);
  signal full_s: std_logic_vector(full_s_width - 1 downto 0);
  signal core_s: std_logic_vector(full_s_width - 1 downto 0);
  signal conv_s: std_logic_vector(s_width - 1 downto 0);
  signal temp_cout : std_logic;
  -- synopsys translate_off
  signal real_a, real_b, real_s: real;
  -- synopsys translate_on
  signal internal_clr: std_logic;
  signal internal_ce: std_logic;
  signal extra_reg_ce: std_logic;
  signal override: std_logic;
  signal logic1: std_logic_vector(0 downto 0);
  component adder_subtracter_spartan2_6_0_daf87e23a67e46f5
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_daf87e23a67e46f5:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_daf87e23a67e46f5:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_daf87e23a67e46f5:
    component  is "black_box";
  component adder_subtracter_spartan2_6_0_199c1e18e4579dff
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_199c1e18e4579dff:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_199c1e18e4579dff:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_199c1e18e4579dff:
    component  is "black_box";
  component adder_subtracter_spartan2_6_0_86c498140491d6df
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_86c498140491d6df:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_86c498140491d6df:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_86c498140491d6df:
    component  is "black_box";
  component adder_subtracter_spartan2_6_0_1d2af19e33936da7
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_1d2af19e33936da7:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_1d2af19e33936da7:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_1d2af19e33936da7:
    component  is "black_box";
  component adder_subtracter_spartan2_6_0_70b89f2715a50f71
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_70b89f2715a50f71:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_70b89f2715a50f71:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_70b89f2715a50f71:
    component  is "black_box";
  component adder_subtracter_spartan2_6_0_081a91230b2114f0
    port (
      a: in std_logic_vector(c_a_width - 1 downto 0);
      s: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(c_b_width - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_spartan2_6_0_081a91230b2114f0:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_spartan2_6_0_081a91230b2114f0:
    component is "true";
  attribute box_type of adder_subtracter_spartan2_6_0_081a91230b2114f0:
    component  is "black_box";
begin
  internal_clr <= (clr or (rst(0))) and ce;
  internal_ce <= ce and en(0);
  logic1(0) <= '1';
  addsub_process: process(a, b, core_s)
  begin
    full_a <= format_input(a, a_width, b_bin_pt - a_bin_pt, a_arith,
                           full_a_width);
    full_b <= format_input(b, b_width, a_bin_pt - b_bin_pt, b_arith,
                           full_b_width);
    conv_s <= convert_type(core_s, full_s_width, full_s_bin_pt, full_s_arith,
                           s_width, s_bin_pt, s_arith, quantization, overflow);
    -- synopsys translate_off
    -- synopsys translate_on
  end process addsub_process;
  synth_behavioral_inst: if not(core) generate
    synth_addsub_inst: synth_addsub
      generic map (
        arith_type => full_s_arith,
        a_width => full_a_width,
        b_width => full_b_width,
        s_width => full_s_width,
        mode => mode,
        use_cin => c_has_c_in,
        use_bin => c_has_b_in,
        latency => latency
      )
      port map (
        a => full_a,
        b => full_b,
        cin => c_in,
        ce => internal_ce,
        clr => internal_clr,
        clk => clk,
        cout(0) => temp_cout,
        s => core_s
      );
  end generate;
  comp0: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_daf87e23a67e46f5")) generate
    core_instance0: adder_subtracter_spartan2_6_0_daf87e23a67e46f5
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp1: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_daf87e23a67e46f5")) generate
    core_instance1: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  comp2: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_199c1e18e4579dff")) generate
    core_instance2: adder_subtracter_spartan2_6_0_199c1e18e4579dff
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp3: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_199c1e18e4579dff")) generate
    core_instance3: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  comp4: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df")) generate
    core_instance4: adder_subtracter_spartan2_6_0_86c498140491d6df
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp5: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df")) generate
    core_instance5: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  comp6: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_1d2af19e33936da7")) generate
    core_instance6: adder_subtracter_spartan2_6_0_1d2af19e33936da7
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp7: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_1d2af19e33936da7")) generate
    core_instance7: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  comp8: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_70b89f2715a50f71")) generate
    core_instance8: adder_subtracter_spartan2_6_0_70b89f2715a50f71
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp9: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_70b89f2715a50f71")) generate
    core_instance9: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  comp10: if (not simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_081a91230b2114f0")) generate
    core_instance10: adder_subtracter_spartan2_6_0_081a91230b2114f0
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_off
  comp11: if (simulating and
             (core_name0 = "adder_subtracter_spartan2_6_0_081a91230b2114f0")) generate
    core_instance11: entity XilinxCoreLib.c_addsub_v6_0(behavioral)
      generic map (
        c_sinit_val => "0",
        c_a_type => c_a_type,
        c_sync_enable => 0,
        c_has_ainit => 0,
        c_sync_priority => 1,
        c_b_type => c_b_type,
        c_has_c_out => c_has_c_out,
        c_has_sinit => 0,
        c_has_c_in => c_has_c_in,
        c_has_b_out => c_has_b_out,
        c_ainit_val => "0000",
        c_b_width => c_b_width,
        c_add_mode => c_add_mode,
        c_has_sset => 0,
        c_bypass_low => 0,
        c_has_q_ovfl => c_has_q_ovfl,
        c_bypass_enable => 0,
        c_has_ovfl => c_has_ovfl,
        c_has_s => c_has_s,
        c_has_q => c_has_q,
        c_has_a_signed => 0,
        c_has_aset => 0,
        c_has_add => 0,
        c_has_sclr => c_has_sclr,
        c_latency => c_latency,
        c_has_q_c_out => c_has_q_c_out,
        c_pipe_stages => 1,
        c_b_value => "0",
        c_out_width => c_output_width,
        c_a_width => c_a_width,
        c_has_q_b_out => c_has_q_b_out,
        c_has_b_in => c_has_b_in,
        c_b_constant => 0,
        c_has_ce => c_has_ce,
        c_low_bit => 0,
        c_has_b_signed => 0,
        c_has_bypass => 0,
        c_has_bypass_with_cin => 0,
        c_has_aclr => 0,
        c_high_bit => c_output_width - 1,
        c_enable_rlocs => c_enable_rlocs
      )
      port map (
        a => full_a,
        s => core_s,
        b => full_b
      );
  end generate;
-- synopsys translate_on
  latency_test: if (core) and (extra_registers > 0) generate
      override_test: if (c_latency > 1) generate
       override_pipe: synth_reg
          generic map (
            width => 1,
            latency => c_latency)
          port map (
            i => logic1,
            ce => internal_ce,
            clr => internal_clr,
            clk => clk,
            o(0) => override);
       extra_reg_ce <= ce and en(0) and override;
      end generate override_test;
      no_override: if (c_latency = 0) or (c_latency = 1) generate
       extra_reg_ce <= ce and en(0);
      end generate no_override;
      extra_reg: synth_reg
        generic map (
          width => s_width,
          latency => extra_registers
        )
        port map (
          i => conv_s,
          ce => extra_reg_ce,
          clr => internal_clr,
          clk => clk,
          o => s
        );
      cout_test : if((c_has_c_out = 1) or
                (c_has_b_out = 1) or
                (c_has_q_c_out = 1) or
                (c_has_q_b_out = 1)) generate
      c_out_extra_reg: synth_reg
        generic map (
          width => 1,
          latency => extra_registers
        )
        port map (
          i(0) => temp_cout,
          ce => extra_reg_ce,
          clr => internal_clr,
          clk => clk,
          o => c_out
        );
      end generate cout_test;
  end generate;
  latency_s: if  (not(core) or (latency = 0) or (extra_registers = 0))  generate
    s <= conv_s;
  end generate latency_s;
  latency0: if ( (not(core) or (latency = 0) or (extra_registers = 0)) and
                ((c_has_b_out = 1) or
                (c_has_q_c_out = 1) or
                (c_has_c_out = 1) or
                (c_has_q_b_out = 1)))  generate
    c_out(0) <= temp_cout;
  end generate latency0;
  tie_dangling_cout: if ((c_has_c_out = 0) and
                        (c_has_b_out = 0) and
                        (c_has_q_c_out = 0) and
                        (c_has_q_b_out = 0)) generate
    c_out <= "0";
  end generate tie_dangling_cout;
end architecture behavior;
