Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.73 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.73 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: alone2_clk_wrapper.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : alone2_clk_wrapper.prj
Input Format                       : mixed
Synthesis Constraint File          : .\alone2_clk_wrapper.xcf
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : alone2_clk_wrapper
Output Format                      : NGC
Target Device                      : xc2s50-6-pq208

---- Source Options
Top Module Name                    : alone2_clk_wrapper
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : YES
Hierarchy Separator                : _
Bus Delimiter                      : ()
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : alone2_clk_wrapper.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xalone2/alone2_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/xalone2/alone2_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <alone2_addsub1> (Architecture <behavior>) compiled.
Entity <alone2_kd> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <alone2> (Architecture <structural>) compiled.
Entity <alone2_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file C:/MATLAB6p5/work/xalone2/alone2_clk_wrapper.vhd in Library work.
Architecture structural of Entity alone2_clk_wrapper is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <alone2_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xalone2/alone2_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <alone2_clk_wrapper> analyzed. Unit <alone2_clk_wrapper> generated.

Analyzing Entity <alone2> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2370: Unconnected input port 'c_in' of component 'alone2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2370: Unconnected output port 'c_out' of component 'alone2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2425: Unconnected input port 'c_in' of component 'alone2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2425: Unconnected output port 'c_out' of component 'alone2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2480: Unconnected input port 'c_in' of component 'alone2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2480: Unconnected output port 'c_out' of component 'alone2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2535: Unconnected input port 'c_in' of component 'alone2_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2535: Unconnected output port 'c_out' of component 'alone2_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2642: Unconnected input port 'core_ce' of component 'alone2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2642: Unconnected input port 'core_clr' of component 'alone2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2642: Unconnected input port 'core_clk' of component 'alone2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2699: Unconnected input port 'core_ce' of component 'alone2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2699: Unconnected input port 'core_clr' of component 'alone2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2699: Unconnected input port 'core_clk' of component 'alone2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2756: Unconnected input port 'core_ce' of component 'alone2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2756: Unconnected input port 'core_clr' of component 'alone2_kd' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 2756: Unconnected input port 'core_clk' of component 'alone2_kd' is tied to default value.
Entity <alone2> analyzed. Unit <alone2> generated.

Analyzing generic Entity <alone2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_20d492340947cbb3"
	a_width = 8
	a_bin_pt = 4
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 8
	b_bin_pt = 4
	b_arith = 2
	s_width = 9
	s_bin_pt = 4
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 9
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 9
	c_b_width = 9
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 9
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <alone2_addsub1> analyzed. Unit <alone2_addsub1> generated.

Analyzing generic Entity <alone2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_23786a6ca9307430"
	a_width = 24
	a_bin_pt = 14
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 25
	b_bin_pt = 8
	b_arith = 2
	s_width = 32
	s_bin_pt = 14
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 32
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 32
	c_b_width = 32
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 32
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <alone2_addsub1> analyzed. Unit <alone2_addsub10> generated.

Analyzing generic Entity <alone2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0"
	a_width = 8
	a_bin_pt = 4
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 16
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <alone2_addsub1> analyzed. Unit <alone2_addsub11> generated.

Analyzing generic Entity <alone2_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_76b75f709cf09b35"
	a_width = 32
	a_bin_pt = 14
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 32
	b_bin_pt = 24
	b_arith = 2
	s_width = 8
	s_bin_pt = 4
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 43
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 43
	c_b_width = 43
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 43
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <alone2_addsub1> analyzed. Unit <alone2_addsub12> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 8
	d_bin_pt = 4
	d_arith = 2
	q_width = 8
	q_bin_pt = 4
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 8
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 8
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay3> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg6> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e7> generated.

Analyzing generic Entity <alone2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_741889f5f570cd27"
	a_width = 9
	a_bin_pt = 4
	a_arith = 2
	b_width = 4
	b_bin_pt = 4
	b_arith = 2
	p_width = 25
	p_bin_pt = 8
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 9
	c_b_width = 12
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 9
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 4
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 3120
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 25
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <alone2_kd> analyzed. Unit <alone2_kd> generated.

Analyzing generic Entity <alone2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_e880a1b4a8ae9201"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 32
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 3
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 7
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 32
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <alone2_kd> analyzed. Unit <alone2_kd4> generated.

Analyzing generic Entity <alone2_kd> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_45d7b402c1ef3689"
	a_width = 8
	a_bin_pt = 4
	a_arith = 2
	b_width = 4
	b_bin_pt = 10
	b_arith = 2
	p_width = 24
	p_bin_pt = 14
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 8
	c_b_width = 13
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 8
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 10
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 4475
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 24
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <alone2_kd> analyzed. Unit <alone2_kd5> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <alone2_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xalone2/alone2_files.vhd line 3072: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <alone2_clock_driver> analyzed. Unit <alone2_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


Reading constraint file .\alone2_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <srl17e7>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
Unit <srl17e7> synthesized.


Synthesizing Unit <synth_reg6>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg6> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <alone2_kd5>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <alone2_kd5> synthesized.


Synthesizing Unit <alone2_kd4>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <alone2_kd4> synthesized.


Synthesizing Unit <alone2_kd>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <alone2_kd> synthesized.


Synthesizing Unit <xldelay3>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
Unit <xldelay3> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <alone2_addsub12>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<42:28>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<19:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <alone2_addsub12> synthesized.


Synthesizing Unit <alone2_addsub11>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<16>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <alone2_addsub11> synthesized.


Synthesizing Unit <alone2_addsub10>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <alone2_addsub10> synthesized.


Synthesizing Unit <alone2_addsub1>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <alone2_addsub1> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <alone2_clock_driver>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <alone2_clock_driver> synthesized.


Synthesizing Unit <alone2>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_files.vhd.
Unit <alone2> synthesized.


Synthesizing Unit <alone2_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/xalone2/alone2_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <alone2_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <alone2_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_20d492340947cbb3.edn" "adder_subtracter_spartan2_6_0_20d492340947cbb3.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_20d492340947cbb3.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_23786a6ca9307430.edn" "adder_subtracter_spartan2_6_0_23786a6ca9307430.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_23786a6ca9307430.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.edn" "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_76b75f709cf09b35.edn" "adder_subtracter_spartan2_6_0_76b75f709cf09b35.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_76b75f709cf09b35.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_741889f5f570cd27.edn" "multiplier_spartan2_6_0_741889f5f570cd27.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_741889f5f570cd27.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_e880a1b4a8ae9201.edn" "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_e880a1b4a8ae9201.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_45d7b402c1ef3689.edn" "multiplier_spartan2_6_0_45d7b402c1ef3689.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_45d7b402c1ef3689.ngo"...
Loading core <adder_subtracter_spartan2_6_0_20d492340947cbb3> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_23786a6ca9307430> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_8c3a892e3c6c3ed0> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_76b75f709cf09b35> for timing and area information for instance <core_instance6>.
Loading core <multiplier_spartan2_6_0_741889f5f570cd27> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_e880a1b4a8ae9201> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_45d7b402c1ef3689> for timing and area information for instance <core_instance4>.

Optimizing unit <alone2_clk_wrapper> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\alone2_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block alone2_clk_wrapper, actual ratio is 19.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : alone2_clk_wrapper.ngr
Top Level Output File Name         : alone2_clk_wrapper
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 18

Cell Usage :
# BELS                             : 676
#      BUF                         : 81
#      GND                         : 8
#      LUT4                        : 255
#      MUXCY                       : 161
#      VCC                         : 2
#      XORCY                       : 169
# FlipFlops/Latches                : 24
#      FDE                         : 24
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 16
#      IBUF                        : 8
#      OBUF                        : 8
# Others                           : 1
#      TIMESPEC                    : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     151  out of    768    19%  
 Number of Slice Flip Flops:            24  out of   1536     1%  
 Number of 4 input LUTs:               255  out of   1536    16%  
 Number of bonded IOBs:                 16  out of    144    11%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 24    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.045ns (Maximum Frequency: 198.216MHz)
   Minimum input arrival time before clock: 6.413ns
   Maximum output required time after clock: 23.683ns
   Maximum combinational path delay: 25.051ns
-------------------------------------------------------------------------

Timing constraint: TS_clk_cb20dc04 = PERIOD TIMEGRP "clk_cb20dc04" 100 nS HIGH 50 nS
-------------------------------------------------------------------------
Slack:                  94.955ns
  Source:               alone2_top_delay1_synth_reg_srl_inst_last_srl17e_u20 (FF)
  Destination:          alone2_top_delay1_synth_reg_srl_inst_last_srl17e_u215 (FF)
  Data Path Delay:      5.045ns (Levels of Logic = 18)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 100.000ns

  Data Path: alone2_top_delay1_synth_reg_srl_inst_last_srl17e_u20 (FF) to alone2_top_delay1_synth_reg_srl_inst_last_srl17e_u215 (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   1.085   1.035  alone2_top_delay1_synth_reg_srl_inst_last_srl17e_u20 (alone2_top_q_x_0(0))
     begin scope: 'alone2_top_addsub3_core_instance4'
     LUT4:I1->O            1   0.549   0.000  BU3 (N2)
     MUXCY:S->O            1   0.659   0.000  BU4 (N5)
     MUXCY:CI->O           1   0.042   0.000  BU8 (N10)
     MUXCY:CI->O           1   0.042   0.000  BU12 (N15)
     MUXCY:CI->O           1   0.042   0.000  BU16 (N20)
     MUXCY:CI->O           1   0.042   0.000  BU20 (N25)
     MUXCY:CI->O           1   0.042   0.000  BU24 (N30)
     MUXCY:CI->O           1   0.042   0.000  BU28 (N35)
     MUXCY:CI->O           1   0.042   0.000  BU32 (N40)
     MUXCY:CI->O           1   0.042   0.000  BU36 (N45)
     MUXCY:CI->O           1   0.042   0.000  BU40 (N50)
     MUXCY:CI->O           1   0.042   0.000  BU44 (N55)
     MUXCY:CI->O           1   0.042   0.000  BU48 (N60)
     MUXCY:CI->O           1   0.042   0.000  BU52 (N65)
     MUXCY:CI->O           1   0.042   0.000  BU56 (N70)
     MUXCY:CI->O           1   0.042   0.000  BU60 (N75)
     XORCY:CI->O           7   0.420   0.000  BU65 (S(15))
     end scope: 'alone2_top_addsub3_core_instance4'
     FDE:D                     0.709          alone2_top_delay1_synth_reg_srl_inst_last_srl17e_u215
    ----------------------------------------
    Total                      5.045ns (4.010ns logic, 1.035ns route)
                                       (79.5% logic, 20.5% route)

=========================================================================
CPU : 22.16 / 23.64 s | Elapsed : 22.00 / 23.00 s
 
--> 

Total memory usage is 68340 kilobytes


