source {C:/xilinx_62i/data/projnav/scripts/VsimStopServer.tcl}
initIPC 1200
-- Auto Generated by Project Navigator to simulate
-- HDL Bencher Annotated Test Bench
--
vlib work
onbreak {resume}
onerror {quit -code 99 -force}
onElabError {resume}
vcom -93 -explicit  pid_sysgen_pkgs.vhd
vcom -93 -explicit  pid_sysgen_files.vhd
vcom -93 -explicit  pid_sysgen_clk_wrapper.vhd
vcom -93 -explicit  est8_tbw.ant
vsim -t 1ps  -lib work est8_tbw
run -all
quit -force
