Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.64 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.64 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: test2_pid_clk_wrapper.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : test2_pid_clk_wrapper.prj
Input Format                       : mixed
Synthesis Constraint File          : .\test2_pid_clk_wrapper.xcf
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : test2_pid_clk_wrapper
Output Format                      : NGC
Target Device                      : xc2s50-6-pq208

---- Source Options
Top Module Name                    : test2_pid_clk_wrapper
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : YES
Hierarchy Separator                : _
Bus Delimiter                      : ()
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : test2_pid_clk_wrapper.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/MATLAB6p5/work/xtest2_pid/test2_pid_pkgs.vhd in Library work.
Architecture conv_pkg of Entity conv_pkg is up to date.
Compiling vhdl file C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd in Library work.
Entity <srl17e> (Architecture <structural>) compiled.
Entity <synth_reg> (Architecture <structural>) compiled.
Entity <synth_reg_reg> (Architecture <behav>) compiled.
Entity <single_reg_w_init> (Architecture <structural>) compiled.
Entity <synth_reg_w_init> (Architecture <structural>) compiled.
Entity <xlclkprobe> (Architecture <behavior>) compiled.
Entity <xlclockdriver> (Architecture <behavior>) compiled.
Entity <xlclockgenerator> (Architecture <structural>) compiled.
Entity <xlsl2slv> (Architecture <behavior>) compiled.
Entity <xlslv2sl> (Architecture <behavior>) compiled.
Entity <synth_addsub> (Architecture <behavior>) compiled.
Entity <test2_pid_addsub1> (Architecture <behavior>) compiled.
Entity <test2_pid_cmult3> (Architecture <behavior>) compiled.
Entity <xldelay> (Architecture <behavior>) compiled.
Entity <test2_pid> (Architecture <structural>) compiled.
Entity <test2_pid_clock_driver> (Architecture <structural>) compiled.
Compiling vhdl file C:/MATLAB6p5/work/xtest2_pid/test2_pid_clk_wrapper.vhd in Library work.
Entity <test2_pid_clk_wrapper> (Architecture <structural>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <test2_pid_clk_wrapper> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_clk_wrapper.vhd line 105: Unconnected output port 'fakeoutforxst' of component 'xlclkprobe'.
Entity <test2_pid_clk_wrapper> analyzed. Unit <test2_pid_clk_wrapper> generated.

Analyzing Entity <test2_pid_clock_driver> (Architecture <structural>).
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 3574: Unconnected output port 'clr' of component 'xlclockdriver'.
Entity <test2_pid_clock_driver> analyzed. Unit <test2_pid_clock_driver> generated.

Analyzing generic Entity <xlclockdriver> (Architecture <behavior>).
	period = 1
	use_bufg = <u>0
Entity <xlclockdriver> analyzed. Unit <xlclockdriver> generated.

Analyzing generic Entity <synth_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
	latency = 1
Entity <synth_reg_w_init> analyzed. Unit <synth_reg_w_init> generated.

Analyzing generic Entity <single_reg_w_init> (Architecture <structural>).
	width = 1
	init_index = 0
	init_value = <u>0000
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <single_reg_w_init> analyzed. Unit <single_reg_w_init> generated.

Analyzing Entity <test2_pid> (Architecture <structural>).
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2599: Unconnected input port 'c_in' of component 'test2_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2599: Unconnected output port 'c_out' of component 'test2_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2654: Unconnected input port 'c_in' of component 'test2_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2654: Unconnected output port 'c_out' of component 'test2_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2709: Unconnected input port 'c_in' of component 'test2_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2709: Unconnected output port 'c_out' of component 'test2_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2764: Unconnected input port 'c_in' of component 'test2_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2764: Unconnected output port 'c_out' of component 'test2_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2819: Unconnected input port 'c_in' of component 'test2_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2819: Unconnected output port 'c_out' of component 'test2_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2874: Unconnected input port 'c_in' of component 'test2_pid_addsub1' is tied to default value.
WARNING:Xst:753 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2874: Unconnected output port 'c_out' of component 'test2_pid_addsub1'.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2929: Unconnected input port 'core_ce' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2929: Unconnected input port 'core_clr' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 2929: Unconnected input port 'core_clk' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 3064: Unconnected input port 'core_ce' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 3064: Unconnected input port 'core_clr' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 3064: Unconnected input port 'core_clk' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 3121: Unconnected input port 'core_ce' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 3121: Unconnected input port 'core_clr' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 3121: Unconnected input port 'core_clk' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 3178: Unconnected input port 'core_ce' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 3178: Unconnected input port 'core_clr' of component 'test2_pid_cmult3' is tied to default value.
WARNING:Xst:752 - C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd line 3178: Unconnected input port 'core_clk' of component 'test2_pid_cmult3' is tied to default value.
Entity <test2_pid> analyzed. Unit <test2_pid> generated.

Analyzing generic Entity <test2_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_daf87e23a67e46f5"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 36
	b_bin_pt = 20
	b_arith = 2
	s_width = 37
	s_bin_pt = 20
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 37
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 37
	c_b_width = 37
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 37
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test2_pid_addsub1> analyzed. Unit <test2_pid_addsub1> generated.

Analyzing generic Entity <test2_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_199c1e18e4579dff"
	a_width = 37
	a_bin_pt = 20
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 38
	s_bin_pt = 20
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 38
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 38
	c_b_width = 38
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 38
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test2_pid_addsub1> analyzed. Unit <test2_pid_addsub10> generated.

Analyzing generic Entity <test2_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_86c498140491d6df"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 16
	b_bin_pt = 8
	b_arith = 2
	s_width = 17
	s_bin_pt = 8
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 17
	full_s_arith = 2
	mode = 2
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 17
	c_b_width = 17
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 1
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 17
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test2_pid_addsub1> analyzed. Unit <test2_pid_addsub11> generated.

Analyzing generic Entity <test2_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_1d2af19e33936da7"
	a_width = 59
	a_bin_pt = 36
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 37
	b_bin_pt = 24
	b_arith = 2
	s_width = 60
	s_bin_pt = 36
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 60
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 60
	c_b_width = 60
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 60
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test2_pid_addsub1> analyzed. Unit <test2_pid_addsub12> generated.

Analyzing generic Entity <test2_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_70b89f2715a50f71"
	a_width = 58
	a_bin_pt = 36
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 36
	b_bin_pt = 28
	b_arith = 2
	s_width = 59
	s_bin_pt = 36
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 59
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 59
	c_b_width = 59
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 59
	c_enable_rlocs = 1
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test2_pid_addsub1> analyzed. Unit <test2_pid_addsub13> generated.

Analyzing generic Entity <test2_pid_addsub1> (Architecture <behavior>).
	core_name0 = "adder_subtracter_spartan2_6_0_081a91230b2114f0"
	a_width = 60
	a_bin_pt = 36
	a_arith = 2
	c_in_width = 16
	c_in_bin_pt = 4
	c_in_arith = 1
	c_out_width = 16
	c_out_bin_pt = 4
	c_out_arith = 1
	b_width = 24
	b_bin_pt = 16
	b_arith = 2
	s_width = 24
	s_bin_pt = 16
	s_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	full_s_width = 61
	full_s_arith = 2
	mode = 1
	extra_registers = 0
	latency = 0
	quantization = 1
	overflow = 1
	c_a_width = 61
	c_b_width = 61
	c_a_type = 0
	c_b_type = 0
	c_add_mode = 0
	c_has_s = 1
	c_has_q = 0
	c_has_sclr = 0
	c_has_ce = 0
	c_latency = 0
	c_output_width = 61
	c_enable_rlocs = 0
	c_has_c_in = 0
	c_has_b_in = 0
	c_has_c_out = 0
	c_has_q_c_out = 0
	c_has_b_out = 0
	c_has_q_b_out = 0
	c_has_q_ovfl = 0
	c_has_ovfl = 0
	core = <u>1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test2_pid_addsub1> analyzed. Unit <test2_pid_addsub14> generated.

Analyzing generic Entity <test2_pid_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_b9038ba71093207b"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 12
	b_arith = 2
	p_width = 36
	p_bin_pt = 20
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 14
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 12
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 8192
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 36
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test2_pid_cmult3> analyzed. Unit <test2_pid_cmult3> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 16
	d_bin_pt = 8
	d_arith = 2
	q_width = 16
	q_bin_pt = 8
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 16
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 16
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e> generated.

Analyzing generic Entity <xldelay> (Architecture <behavior>).
	d_width = 24
	d_bin_pt = 16
	d_arith = 2
	q_width = 24
	q_bin_pt = 16
	q_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	rst_arith = 1
	latency = 1
	reg_retiming = <u>0
Entity <xldelay> analyzed. Unit <xldelay5> generated.

Analyzing generic Entity <synth_reg> (Architecture <structural>).
	width = 24
	latency = 1
Entity <synth_reg> analyzed. Unit <synth_reg9> generated.

Analyzing generic Entity <srl17e> (Architecture <structural>).
	width = 24
	latency = 1
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <srl17e> analyzed. Unit <srl17e10> generated.

Analyzing generic Entity <test2_pid_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_9037c1044a9f9f55"
	a_width = 38
	a_bin_pt = 20
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 58
	p_bin_pt = 36
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 38
	c_b_width = 20
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 38
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 1048575
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 58
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test2_pid_cmult3> analyzed. Unit <test2_pid_cmult36> generated.

Analyzing generic Entity <test2_pid_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_5beb205b1874c8e3"
	a_width = 16
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 20
	b_arith = 2
	p_width = 36
	p_bin_pt = 28
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 16
	c_b_width = 7
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 16
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 20
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 105
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 36
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test2_pid_cmult3> analyzed. Unit <test2_pid_cmult37> generated.

Analyzing generic Entity <test2_pid_cmult3> (Architecture <behavior>).
	core_name0 = "multiplier_spartan2_6_0_91582c6cefb29f01"
	a_width = 17
	a_bin_pt = 8
	a_arith = 2
	b_width = 4
	b_bin_pt = 16
	b_arith = 2
	p_width = 37
	p_bin_pt = 24
	p_arith = 2
	rst_width = 1
	rst_bin_pt = 0
	rst_arith = 1
	en_width = 1
	en_bin_pt = 0
	en_arith = 1
	latency = 0
	multsign = 2
	quantization = 1
	overflow = 1
	extra_registers = 0
	c_a_width = 17
	c_b_width = 19
	c_a_type = 0
	c_b_type = 1
	c_type = 0
	c_pipelined = 0
	bram_addr_width = 8
	c_baat = 17
	c_mult_type = 2
	c_has_q = 0
	c_has_nd = 0
	c_has_o = 1
	oversample = 1
	const_bin_pt = 16
	c_reg_inputs = 0
	c_enable_rlocs = 1
	c_b_value_hi = 0
	c_b_value_low = 286392
	c_has_b = 0
	c_has_loadb = 0
	c_b_constant = 1
	c_mem_type = 0
	c_output_width = 37
	c_output_hold = 0
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <test2_pid_cmult3> analyzed. Unit <test2_pid_cmult38> generated.

Analyzing generic Entity <xlsl2slv> (Architecture <behavior>).
	dout_width = 1
	dout_bin_pt = 0
	dout_arith = 1
Entity <xlsl2slv> analyzed. Unit <xlsl2slv> generated.

Analyzing Entity <xlclkprobe> (Architecture <behavior>).
Entity <xlclkprobe> analyzed. Unit <xlclkprobe> generated.


Reading constraint file .\test2_pid_clk_wrapper.xcf.
XCF parsing done.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <srl17e10>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
Unit <srl17e10> synthesized.


Synthesizing Unit <synth_reg9>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg9> synthesized.


Synthesizing Unit <srl17e>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
Unit <srl17e> synthesized.


Synthesizing Unit <synth_reg>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clr> is never used.
Unit <synth_reg> synthesized.


Synthesizing Unit <xlsl2slv>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
Unit <xlsl2slv> synthesized.


Synthesizing Unit <test2_pid_cmult38>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test2_pid_cmult38> synthesized.


Synthesizing Unit <test2_pid_cmult37>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test2_pid_cmult37> synthesized.


Synthesizing Unit <test2_pid_cmult36>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test2_pid_cmult36> synthesized.


Synthesizing Unit <xldelay5>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
Unit <xldelay5> synthesized.


Synthesizing Unit <xldelay>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
Unit <xldelay> synthesized.


Synthesizing Unit <test2_pid_cmult3>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <core_clk> is never used.
WARNING:Xst:647 - Input <core_clr> is never used.
WARNING:Xst:646 - Signal <nd> is assigned but never used.
WARNING:Xst:646 - Signal <internal_core_ce> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
Unit <test2_pid_cmult3> synthesized.


Synthesizing Unit <test2_pid_addsub14>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:646 - Signal <core_s<60:44>> is assigned but never used.
WARNING:Xst:646 - Signal <core_s<19:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test2_pid_addsub14> synthesized.


Synthesizing Unit <test2_pid_addsub13>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test2_pid_addsub13> synthesized.


Synthesizing Unit <test2_pid_addsub12>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test2_pid_addsub12> synthesized.


Synthesizing Unit <test2_pid_addsub11>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test2_pid_addsub11> synthesized.


Synthesizing Unit <test2_pid_addsub10>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test2_pid_addsub10> synthesized.


Synthesizing Unit <test2_pid_addsub1>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <c_in<0>> is never used.
WARNING:Xst:1780 - Signal <override> is never used or assigned.
WARNING:Xst:1780 - Signal <full_s> is never used or assigned.
WARNING:Xst:1780 - Signal <temp_cout> is never used or assigned.
WARNING:Xst:1780 - Signal <extra_reg_ce> is never used or assigned.
WARNING:Xst:646 - Signal <logic1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <internal_clr> is assigned but never used.
WARNING:Xst:646 - Signal <internal_ce> is assigned but never used.
Unit <test2_pid_addsub1> synthesized.


Synthesizing Unit <single_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
Unit <single_reg_w_init> synthesized.


Synthesizing Unit <synth_reg_w_init>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
Unit <synth_reg_w_init> synthesized.


Synthesizing Unit <xlclockdriver>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:1780 - Signal <ce_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <internal_ce> is never used or assigned.
    Found T flip-flop for signal <clk_num<0>>.
    Summary:
	inferred   1 T-type flip-flop(s).
Unit <xlclockdriver> synthesized.


Synthesizing Unit <xlclkprobe>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <clr> is never used.
WARNING:Xst:647 - Input <ce> is never used.
Unit <xlclkprobe> synthesized.


Synthesizing Unit <test2_pid>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
Unit <test2_pid> synthesized.


Synthesizing Unit <test2_pid_clock_driver>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_files.vhd.
WARNING:Xst:647 - Input <sysce> is never used.
Unit <test2_pid_clock_driver> synthesized.


Synthesizing Unit <test2_pid_clk_wrapper>.
    Related source file is C:/MATLAB6p5/work/xtest2_pid/test2_pid_clk_wrapper.vhd.
WARNING:Xst:647 - Input <ce> is never used.
Unit <test2_pid_clk_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <clr_reg> of the block <synth_reg_w_init> are unconnected in block <xlclockdriver>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <xlclkprobe_x_0> of the block <xlclkprobe> are unconnected in block <test2_pid_clk_wrapper>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_daf87e23a67e46f5.edn" "adder_subtracter_spartan2_6_0_daf87e23a67e46f5.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_daf87e23a67e46f5.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_199c1e18e4579dff.edn" "adder_subtracter_spartan2_6_0_199c1e18e4579dff.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_199c1e18e4579dff.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_86c498140491d6df.edn" "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_86c498140491d6df.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_1d2af19e33936da7.edn" "adder_subtracter_spartan2_6_0_1d2af19e33936da7.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_1d2af19e33936da7.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_70b89f2715a50f71.edn" "adder_subtracter_spartan2_6_0_70b89f2715a50f71.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_70b89f2715a50f71.ngo"...
Launcher: Executing edif2ngd -noa "adder_subtracter_spartan2_6_0_081a91230b2114f0.edn" "adder_subtracter_spartan2_6_0_081a91230b2114f0.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "adder_subtracter_spartan2_6_0_081a91230b2114f0.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_b9038ba71093207b.edn" "multiplier_spartan2_6_0_b9038ba71093207b.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_b9038ba71093207b.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_9037c1044a9f9f55.edn" "multiplier_spartan2_6_0_9037c1044a9f9f55.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_9037c1044a9f9f55.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_5beb205b1874c8e3.edn" "multiplier_spartan2_6_0_5beb205b1874c8e3.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_5beb205b1874c8e3.ngo"...
Launcher: Executing edif2ngd -noa "multiplier_spartan2_6_0_91582c6cefb29f01.edn" "multiplier_spartan2_6_0_91582c6cefb29f01.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier_spartan2_6_0_91582c6cefb29f01.ngo"...
Loading core <adder_subtracter_spartan2_6_0_daf87e23a67e46f5> for timing and area information for instance <core_instance0>.
Loading core <adder_subtracter_spartan2_6_0_199c1e18e4579dff> for timing and area information for instance <core_instance2>.
Loading core <adder_subtracter_spartan2_6_0_86c498140491d6df> for timing and area information for instance <core_instance4>.
Loading core <adder_subtracter_spartan2_6_0_1d2af19e33936da7> for timing and area information for instance <core_instance6>.
Loading core <adder_subtracter_spartan2_6_0_70b89f2715a50f71> for timing and area information for instance <core_instance8>.
Loading core <adder_subtracter_spartan2_6_0_081a91230b2114f0> for timing and area information for instance <core_instance10>.
Loading core <multiplier_spartan2_6_0_b9038ba71093207b> for timing and area information for instance <core_instance0>.
Loading core <multiplier_spartan2_6_0_9037c1044a9f9f55> for timing and area information for instance <core_instance2>.
Loading core <multiplier_spartan2_6_0_5beb205b1874c8e3> for timing and area information for instance <core_instance4>.
Loading core <multiplier_spartan2_6_0_91582c6cefb29f01> for timing and area information for instance <core_instance6>.

Optimizing unit <test2_pid_clk_wrapper> ...

Optimizing unit <srl17e10> ...
Loading device for application Xst from file 'v50.nph' in environment E:/xilinx_62.

Mapping all equations...
Building and optimizing final netlist ...
Annotating constraints using XCF file '.\test2_pid_clk_wrapper.xcf'
XCF parsing done.
Found area constraint ratio of 100 (+ 5) on block test2_pid_clk_wrapper, actual ratio is 72.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : test2_pid_clk_wrapper.ngr
Top Level Output File Name         : test2_pid_clk_wrapper
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 42

Cell Usage :
# BELS                             : 2439
#      BUF                         : 167
#      GND                         : 11
#      LUT4                        : 991
#      MUXCY                       : 628
#      VCC                         : 3
#      XORCY                       : 639
# FlipFlops/Latches                : 56
#      FDE                         : 56
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 40
#      IBUF                        : 16
#      OBUF                        : 24
# Others                           : 1
#      TIMESPEC                    : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                     560  out of    768    72%  
 Number of Slice Flip Flops:            56  out of   1536     3%  
 Number of 4 input LUTs:               991  out of   1536    64%  
 Number of bonded IOBs:                 40  out of    144    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 56    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 33.864ns (Maximum Frequency: 29.530MHz)
   Minimum input arrival time before clock: 30.292ns
   Maximum output required time after clock: 39.029ns
   Maximum combinational path delay: 35.457ns
-------------------------------------------------------------------------

Timing constraint: TS_clk_de20a3dc = PERIOD TIMEGRP "clk_de20a3dc" 100 nS HIGH 50 nS
-------------------------------------------------------------------------
Slack:                  66.136ns
  Source:               test2_pid_top_delay_synth_reg_srl_inst_last_srl17e_u215 (FF)
  Destination:          test2_pid_top_delay1_synth_reg_srl_inst_last_srl17e_u223 (FF)
  Data Path Delay:      33.864ns (Levels of Logic = 45)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 100.000ns

  Data Path: test2_pid_top_delay_synth_reg_srl_inst_last_srl17e_u215 (FF) to test2_pid_top_delay1_synth_reg_srl_inst_last_srl17e_u223 (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             11   1.085   2.070  test2_pid_top_delay_synth_reg_srl_inst_last_srl17e_u215 (test2_pid_top_q(15))
     begin scope: 'test2_pid_top_cmult3_core_instance0'
     BUF:I->O              1   0.549   1.035  BU48 (o(28))
     end scope: 'test2_pid_top_cmult3_core_instance0'
     begin scope: 'test2_pid_top_addsub1_core_instance0'
     LUT4:I1->O            1   0.549   0.000  BU115 (N142)
     MUXCY:S->O            1   0.659   0.000  BU116 (N145)
     MUXCY:CI->O           1   0.042   0.000  BU120 (N150)
     XORCY:CI->O           1   0.420   1.035  BU125 (S(30))
     end scope: 'test2_pid_top_addsub1_core_instance0'
     begin scope: 'test2_pid_top_addsub2_core_instance2'
     LUT4:I0->O            1   0.549   0.000  BU123 (N152)
     MUXCY:S->O            1   0.659   0.000  BU124 (N155)
     XORCY:CI->O          23   0.420   3.015  BU129 (S(31))
     end scope: 'test2_pid_top_addsub2_core_instance2'
     begin scope: 'test2_pid_top_kd_core_instance2'
     LUT4:I3->O            1   0.549   1.035  BU1249 (N9693)
     LUT4:I1->O            1   0.549   0.000  BU1352 (N26307)
     MUXCY:S->O            1   0.659   0.000  BU1353 (N26310)
     MUXCY:CI->O           1   0.042   0.000  BU1357 (N26315)
     MUXCY:CI->O           1   0.042   0.000  BU1361 (N26320)
     MUXCY:CI->O           1   0.042   0.000  BU1365 (N26325)
     MUXCY:CI->O           1   0.042   0.000  BU1369 (N26330)
     MUXCY:CI->O           1   0.042   0.000  BU1373 (N26335)
     MUXCY:CI->O           1   0.042   0.000  BU1377 (N26340)
     MUXCY:CI->O           1   0.042   0.000  BU1381 (N26345)
     XORCY:CI->O           1   0.420   1.035  BU1386 (N3824)
     LUT4:I1->O            1   0.549   0.000  BU1502 (N29472)
     MUXCY:S->O            1   0.659   0.000  BU1503 (N29475)
     XORCY:CI->O           1   0.420   1.035  BU1508 (N3875)
     LUT4:I1->O            1   0.549   0.000  BU1661 (N31469)
     MUXCY:S->O            1   0.659   0.000  BU1662 (N31472)
     XORCY:CI->O           1   0.420   1.035  BU1667 (N3918)
     LUT4:I0->O            1   0.549   0.000  BU2070 (N33206)
     MUXCY:S->O            1   0.659   0.000  BU2071 (N33209)
     XORCY:CI->O           1   0.420   1.035  BU2076 (N392)
     BUF:I->O              1   0.549   1.035  BU2192 (o(40))
     end scope: 'test2_pid_top_kd_core_instance2'
     begin scope: 'test2_pid_top_addsub5_core_instance8'
     LUT4:I0->O            1   0.549   0.000  BU163 (N202)
     MUXCY:S->O            1   0.659   0.000  BU164 (N205)
     XORCY:CI->O           1   0.420   1.035  BU169 (S(41))
     end scope: 'test2_pid_top_addsub5_core_instance8'
     begin scope: 'test2_pid_top_addsub4_core_instance6'
     LUT4:I0->O            1   0.549   0.000  BU167 (N207)
     MUXCY:S->O            1   0.659   0.000  BU168 (N210)
     XORCY:CI->O           1   0.420   1.035  BU173 (S(42))
     end scope: 'test2_pid_top_addsub4_core_instance6'
     begin scope: 'test2_pid_top_addsub6_core_instance10'
     LUT4:I0->O            1   0.549   0.000  BU171 (N212)
     MUXCY:S->O            1   0.659   0.000  BU172 (N215)
     XORCY:CI->O           2   0.420   0.000  BU177 (S(43))
     end scope: 'test2_pid_top_addsub6_core_instance10'
     FDE:D                     0.709          test2_pid_top_delay1_synth_reg_srl_inst_last_srl17e_u223
    ----------------------------------------
    Total                     33.864ns (18.429ns logic, 15.435ns route)
                                       (54.4% logic, 45.6% route)

=========================================================================
CPU : 35.61 / 36.88 s | Elapsed : 36.00 / 37.00 s
 
--> 

Total memory usage is 84880 kilobytes


