## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model for Module pid_sysgen_clk_wrapper
vcom -87 -explicit  pid_sysgen_clk_wrapper_translate.vhd
vcom -93 -explicit  testdcsp2_tbw.translate_vhw
vsim -t 1ps    -lib work testdcsp2_tbw
do testdcsp2_tbw.udo
view wave
add wave *
view structure
view signals
run -all
## End
